Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205251 |
1 |
|
|
T1 |
958 |
|
T2 |
501 |
|
T11 |
135 |
| auto[1] |
6002492 |
1 |
|
|
T1 |
974 |
|
T2 |
437 |
|
T13 |
505 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11757260 |
1 |
|
|
T1 |
1105 |
|
T2 |
555 |
|
T11 |
135 |
| auto[1] |
2450483 |
1 |
|
|
T1 |
827 |
|
T2 |
383 |
|
T13 |
234 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216774 |
1 |
|
|
T1 |
840 |
|
T2 |
472 |
|
T11 |
135 |
| auto[1] |
5990969 |
1 |
|
|
T1 |
1092 |
|
T2 |
466 |
|
T13 |
507 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1759968 |
1 |
|
|
T1 |
125 |
|
T2 |
57 |
|
T13 |
140 |
| auto[1] |
auto[0] |
auto[1] |
1221328 |
1 |
|
|
T1 |
390 |
|
T2 |
217 |
|
T13 |
105 |
| auto[1] |
auto[1] |
auto[0] |
1780518 |
1 |
|
|
T1 |
140 |
|
T2 |
26 |
|
T13 |
133 |
| auto[1] |
auto[1] |
auto[1] |
1229155 |
1 |
|
|
T1 |
437 |
|
T2 |
166 |
|
T13 |
129 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |