Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8188392 |
1 |
|
|
T1 |
973 |
|
T2 |
415 |
|
T11 |
135 |
| auto[1] |
6019351 |
1 |
|
|
T1 |
959 |
|
T2 |
523 |
|
T13 |
406 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11751716 |
1 |
|
|
T1 |
1305 |
|
T2 |
671 |
|
T11 |
135 |
| auto[1] |
2456027 |
1 |
|
|
T1 |
627 |
|
T2 |
267 |
|
T13 |
190 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217016 |
1 |
|
|
T1 |
1079 |
|
T2 |
621 |
|
T11 |
135 |
| auto[1] |
5990727 |
1 |
|
|
T1 |
853 |
|
T2 |
317 |
|
T13 |
411 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1764637 |
1 |
|
|
T1 |
112 |
|
T2 |
16 |
|
T13 |
147 |
| auto[1] |
auto[0] |
auto[1] |
1220299 |
1 |
|
|
T1 |
373 |
|
T2 |
100 |
|
T13 |
132 |
| auto[1] |
auto[1] |
auto[0] |
1770063 |
1 |
|
|
T1 |
114 |
|
T2 |
34 |
|
T13 |
74 |
| auto[1] |
auto[1] |
auto[1] |
1235728 |
1 |
|
|
T1 |
254 |
|
T2 |
167 |
|
T13 |
58 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |