Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214015 |
1 |
|
|
T1 |
925 |
|
T2 |
626 |
|
T11 |
135 |
| auto[1] |
5993728 |
1 |
|
|
T1 |
1007 |
|
T2 |
312 |
|
T13 |
404 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11751994 |
1 |
|
|
T1 |
1111 |
|
T2 |
593 |
|
T11 |
135 |
| auto[1] |
2455749 |
1 |
|
|
T1 |
821 |
|
T2 |
345 |
|
T13 |
371 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205365 |
1 |
|
|
T1 |
940 |
|
T2 |
392 |
|
T11 |
135 |
| auto[1] |
6002378 |
1 |
|
|
T1 |
992 |
|
T2 |
546 |
|
T13 |
809 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1767799 |
1 |
|
|
T1 |
75 |
|
T2 |
104 |
|
T13 |
297 |
| auto[1] |
auto[0] |
auto[1] |
1222674 |
1 |
|
|
T1 |
452 |
|
T2 |
224 |
|
T13 |
260 |
| auto[1] |
auto[1] |
auto[0] |
1778830 |
1 |
|
|
T1 |
96 |
|
T2 |
97 |
|
T13 |
141 |
| auto[1] |
auto[1] |
auto[1] |
1233075 |
1 |
|
|
T1 |
369 |
|
T2 |
121 |
|
T13 |
111 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |