Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207757 |
1 |
|
|
T1 |
1026 |
|
T2 |
485 |
|
T11 |
135 |
| auto[1] |
5999986 |
1 |
|
|
T1 |
906 |
|
T2 |
453 |
|
T13 |
435 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11749371 |
1 |
|
|
T1 |
998 |
|
T2 |
623 |
|
T11 |
135 |
| auto[1] |
2458372 |
1 |
|
|
T1 |
934 |
|
T2 |
315 |
|
T13 |
260 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8202039 |
1 |
|
|
T1 |
735 |
|
T2 |
531 |
|
T11 |
135 |
| auto[1] |
6005704 |
1 |
|
|
T1 |
1197 |
|
T2 |
407 |
|
T13 |
524 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1773573 |
1 |
|
|
T1 |
100 |
|
T2 |
45 |
|
T13 |
155 |
| auto[1] |
auto[0] |
auto[1] |
1231867 |
1 |
|
|
T1 |
440 |
|
T2 |
167 |
|
T13 |
164 |
| auto[1] |
auto[1] |
auto[0] |
1773759 |
1 |
|
|
T1 |
163 |
|
T2 |
47 |
|
T13 |
109 |
| auto[1] |
auto[1] |
auto[1] |
1226505 |
1 |
|
|
T1 |
494 |
|
T2 |
148 |
|
T13 |
96 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |