Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205060 |
1 |
|
|
T1 |
1118 |
|
T2 |
439 |
|
T11 |
135 |
| auto[1] |
6002683 |
1 |
|
|
T1 |
814 |
|
T2 |
499 |
|
T13 |
567 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11769978 |
1 |
|
|
T1 |
1097 |
|
T2 |
509 |
|
T11 |
135 |
| auto[1] |
2437765 |
1 |
|
|
T1 |
835 |
|
T2 |
429 |
|
T13 |
222 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8262850 |
1 |
|
|
T1 |
883 |
|
T2 |
383 |
|
T11 |
135 |
| auto[1] |
5944893 |
1 |
|
|
T1 |
1049 |
|
T2 |
555 |
|
T13 |
433 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1753892 |
1 |
|
|
T1 |
111 |
|
T2 |
85 |
|
T13 |
105 |
| auto[1] |
auto[0] |
auto[1] |
1222275 |
1 |
|
|
T1 |
475 |
|
T2 |
215 |
|
T13 |
113 |
| auto[1] |
auto[1] |
auto[0] |
1753236 |
1 |
|
|
T1 |
103 |
|
T2 |
41 |
|
T13 |
106 |
| auto[1] |
auto[1] |
auto[1] |
1215490 |
1 |
|
|
T1 |
360 |
|
T2 |
214 |
|
T13 |
109 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |