Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239539 |
1 |
|
|
T1 |
1005 |
|
T2 |
467 |
|
T11 |
135 |
| auto[1] |
5968204 |
1 |
|
|
T1 |
927 |
|
T2 |
471 |
|
T13 |
368 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11751936 |
1 |
|
|
T1 |
1174 |
|
T2 |
639 |
|
T11 |
135 |
| auto[1] |
2455807 |
1 |
|
|
T1 |
758 |
|
T2 |
299 |
|
T13 |
203 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8224820 |
1 |
|
|
T1 |
926 |
|
T2 |
513 |
|
T11 |
135 |
| auto[1] |
5982923 |
1 |
|
|
T1 |
1006 |
|
T2 |
425 |
|
T13 |
424 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1771108 |
1 |
|
|
T1 |
139 |
|
T2 |
53 |
|
T13 |
146 |
| auto[1] |
auto[0] |
auto[1] |
1232528 |
1 |
|
|
T1 |
353 |
|
T2 |
131 |
|
T13 |
140 |
| auto[1] |
auto[1] |
auto[0] |
1756008 |
1 |
|
|
T1 |
109 |
|
T2 |
73 |
|
T13 |
75 |
| auto[1] |
auto[1] |
auto[1] |
1223279 |
1 |
|
|
T1 |
405 |
|
T2 |
168 |
|
T13 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |