Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8215368 |
1 |
|
|
T1 |
959 |
|
T2 |
583 |
|
T11 |
135 |
| auto[1] |
5992375 |
1 |
|
|
T1 |
973 |
|
T2 |
355 |
|
T13 |
491 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11748786 |
1 |
|
|
T1 |
1150 |
|
T2 |
620 |
|
T11 |
135 |
| auto[1] |
2458957 |
1 |
|
|
T1 |
782 |
|
T2 |
318 |
|
T13 |
255 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8211025 |
1 |
|
|
T1 |
933 |
|
T2 |
545 |
|
T11 |
135 |
| auto[1] |
5996718 |
1 |
|
|
T1 |
999 |
|
T2 |
393 |
|
T13 |
519 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1779053 |
1 |
|
|
T1 |
99 |
|
T2 |
35 |
|
T13 |
146 |
| auto[1] |
auto[0] |
auto[1] |
1240001 |
1 |
|
|
T1 |
375 |
|
T2 |
174 |
|
T13 |
128 |
| auto[1] |
auto[1] |
auto[0] |
1758708 |
1 |
|
|
T1 |
118 |
|
T2 |
40 |
|
T13 |
118 |
| auto[1] |
auto[1] |
auto[1] |
1218956 |
1 |
|
|
T1 |
407 |
|
T2 |
144 |
|
T13 |
127 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |