Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218700 |
1 |
|
|
T1 |
975 |
|
T2 |
472 |
|
T11 |
135 |
| auto[1] |
5989043 |
1 |
|
|
T1 |
957 |
|
T2 |
466 |
|
T13 |
714 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13449499 |
1 |
|
|
T1 |
1898 |
|
T2 |
923 |
|
T11 |
135 |
| auto[1] |
758244 |
1 |
|
|
T1 |
34 |
|
T2 |
15 |
|
T13 |
125 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239398 |
1 |
|
|
T1 |
956 |
|
T2 |
518 |
|
T11 |
135 |
| auto[1] |
5968345 |
1 |
|
|
T1 |
976 |
|
T2 |
420 |
|
T13 |
630 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2589407 |
1 |
|
|
T1 |
442 |
|
T2 |
194 |
|
T13 |
181 |
| auto[1] |
auto[0] |
auto[1] |
375772 |
1 |
|
|
T1 |
15 |
|
T2 |
4 |
|
T13 |
38 |
| auto[1] |
auto[1] |
auto[0] |
2620694 |
1 |
|
|
T1 |
500 |
|
T2 |
211 |
|
T13 |
324 |
| auto[1] |
auto[1] |
auto[1] |
382472 |
1 |
|
|
T1 |
19 |
|
T2 |
11 |
|
T13 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |