Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205273 |
1 |
|
|
T1 |
916 |
|
T2 |
481 |
|
T11 |
135 |
| auto[1] |
6002470 |
1 |
|
|
T1 |
1016 |
|
T2 |
457 |
|
T13 |
527 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11753881 |
1 |
|
|
T1 |
1077 |
|
T2 |
599 |
|
T11 |
135 |
| auto[1] |
2453862 |
1 |
|
|
T1 |
855 |
|
T2 |
339 |
|
T13 |
298 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8223978 |
1 |
|
|
T1 |
778 |
|
T2 |
579 |
|
T11 |
135 |
| auto[1] |
5983765 |
1 |
|
|
T1 |
1154 |
|
T2 |
359 |
|
T13 |
578 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1770591 |
1 |
|
|
T1 |
138 |
|
T2 |
14 |
|
T13 |
153 |
| auto[1] |
auto[0] |
auto[1] |
1229255 |
1 |
|
|
T1 |
357 |
|
T2 |
184 |
|
T13 |
153 |
| auto[1] |
auto[1] |
auto[0] |
1759312 |
1 |
|
|
T1 |
161 |
|
T2 |
6 |
|
T13 |
127 |
| auto[1] |
auto[1] |
auto[1] |
1224607 |
1 |
|
|
T1 |
498 |
|
T2 |
155 |
|
T13 |
145 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |