Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8244776 |
1 |
|
|
T1 |
912 |
|
T2 |
497 |
|
T11 |
135 |
| auto[1] |
5962967 |
1 |
|
|
T1 |
1020 |
|
T2 |
441 |
|
T13 |
432 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11748398 |
1 |
|
|
T1 |
1097 |
|
T2 |
516 |
|
T11 |
135 |
| auto[1] |
2459345 |
1 |
|
|
T1 |
835 |
|
T2 |
422 |
|
T13 |
390 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217103 |
1 |
|
|
T1 |
877 |
|
T2 |
403 |
|
T11 |
135 |
| auto[1] |
5990640 |
1 |
|
|
T1 |
1055 |
|
T2 |
535 |
|
T13 |
764 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1776241 |
1 |
|
|
T1 |
130 |
|
T2 |
53 |
|
T13 |
246 |
| auto[1] |
auto[0] |
auto[1] |
1237297 |
1 |
|
|
T1 |
369 |
|
T2 |
211 |
|
T13 |
265 |
| auto[1] |
auto[1] |
auto[0] |
1755054 |
1 |
|
|
T1 |
90 |
|
T2 |
60 |
|
T13 |
128 |
| auto[1] |
auto[1] |
auto[1] |
1222048 |
1 |
|
|
T1 |
466 |
|
T2 |
211 |
|
T13 |
125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |