Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8255106 |
1 |
|
|
T1 |
1226 |
|
T2 |
440 |
|
T11 |
135 |
| auto[1] |
5952637 |
1 |
|
|
T1 |
706 |
|
T2 |
498 |
|
T13 |
695 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11744658 |
1 |
|
|
T1 |
1151 |
|
T2 |
526 |
|
T11 |
135 |
| auto[1] |
2463085 |
1 |
|
|
T1 |
781 |
|
T2 |
412 |
|
T13 |
236 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8193099 |
1 |
|
|
T1 |
912 |
|
T2 |
389 |
|
T11 |
135 |
| auto[1] |
6014644 |
1 |
|
|
T1 |
1020 |
|
T2 |
549 |
|
T13 |
490 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1787590 |
1 |
|
|
T1 |
176 |
|
T2 |
72 |
|
T13 |
117 |
| auto[1] |
auto[0] |
auto[1] |
1236496 |
1 |
|
|
T1 |
518 |
|
T2 |
180 |
|
T13 |
90 |
| auto[1] |
auto[1] |
auto[0] |
1763969 |
1 |
|
|
T1 |
63 |
|
T2 |
65 |
|
T13 |
137 |
| auto[1] |
auto[1] |
auto[1] |
1226589 |
1 |
|
|
T1 |
263 |
|
T2 |
232 |
|
T13 |
146 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |