Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8229854 |
1 |
|
|
T1 |
952 |
|
T2 |
565 |
|
T11 |
135 |
| auto[1] |
5977889 |
1 |
|
|
T1 |
980 |
|
T2 |
373 |
|
T13 |
612 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13446841 |
1 |
|
|
T1 |
1899 |
|
T2 |
924 |
|
T11 |
135 |
| auto[1] |
760902 |
1 |
|
|
T1 |
33 |
|
T2 |
14 |
|
T13 |
77 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8222800 |
1 |
|
|
T1 |
1068 |
|
T2 |
605 |
|
T11 |
135 |
| auto[1] |
5984943 |
1 |
|
|
T1 |
864 |
|
T2 |
333 |
|
T13 |
403 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2633420 |
1 |
|
|
T1 |
411 |
|
T2 |
180 |
|
T13 |
74 |
| auto[1] |
auto[0] |
auto[1] |
385244 |
1 |
|
|
T1 |
11 |
|
T2 |
11 |
|
T13 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2590621 |
1 |
|
|
T1 |
420 |
|
T2 |
139 |
|
T13 |
252 |
| auto[1] |
auto[1] |
auto[1] |
375658 |
1 |
|
|
T1 |
22 |
|
T2 |
3 |
|
T13 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |