Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8220250 |
1 |
|
|
T1 |
959 |
|
T2 |
444 |
|
T11 |
135 |
| auto[1] |
5987493 |
1 |
|
|
T1 |
973 |
|
T2 |
494 |
|
T13 |
604 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13446789 |
1 |
|
|
T1 |
1901 |
|
T2 |
923 |
|
T11 |
135 |
| auto[1] |
760954 |
1 |
|
|
T1 |
31 |
|
T2 |
15 |
|
T13 |
153 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214426 |
1 |
|
|
T1 |
1053 |
|
T2 |
604 |
|
T11 |
135 |
| auto[1] |
5993317 |
1 |
|
|
T1 |
879 |
|
T2 |
334 |
|
T13 |
836 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2627841 |
1 |
|
|
T1 |
457 |
|
T2 |
151 |
|
T13 |
311 |
| auto[1] |
auto[0] |
auto[1] |
381913 |
1 |
|
|
T1 |
14 |
|
T2 |
7 |
|
T13 |
64 |
| auto[1] |
auto[1] |
auto[0] |
2604522 |
1 |
|
|
T1 |
391 |
|
T2 |
168 |
|
T13 |
372 |
| auto[1] |
auto[1] |
auto[1] |
379041 |
1 |
|
|
T1 |
17 |
|
T2 |
8 |
|
T13 |
89 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |