Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8233063 |
1 |
|
|
T1 |
1032 |
|
T2 |
446 |
|
T11 |
135 |
| auto[1] |
5974680 |
1 |
|
|
T1 |
900 |
|
T2 |
492 |
|
T13 |
242 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13442483 |
1 |
|
|
T1 |
1893 |
|
T2 |
923 |
|
T11 |
135 |
| auto[1] |
765260 |
1 |
|
|
T1 |
39 |
|
T2 |
15 |
|
T13 |
118 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8196521 |
1 |
|
|
T1 |
933 |
|
T2 |
474 |
|
T11 |
135 |
| auto[1] |
6011222 |
1 |
|
|
T1 |
999 |
|
T2 |
464 |
|
T13 |
593 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2639298 |
1 |
|
|
T1 |
488 |
|
T2 |
206 |
|
T13 |
356 |
| auto[1] |
auto[0] |
auto[1] |
384838 |
1 |
|
|
T1 |
21 |
|
T2 |
6 |
|
T13 |
89 |
| auto[1] |
auto[1] |
auto[0] |
2606664 |
1 |
|
|
T1 |
472 |
|
T2 |
243 |
|
T13 |
119 |
| auto[1] |
auto[1] |
auto[1] |
380422 |
1 |
|
|
T1 |
18 |
|
T2 |
9 |
|
T13 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |