Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8206407 |
1 |
|
|
T1 |
995 |
|
T2 |
483 |
|
T11 |
135 |
| auto[1] |
6001336 |
1 |
|
|
T1 |
937 |
|
T2 |
455 |
|
T13 |
759 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13442574 |
1 |
|
|
T1 |
1902 |
|
T2 |
921 |
|
T11 |
135 |
| auto[1] |
765169 |
1 |
|
|
T1 |
30 |
|
T2 |
17 |
|
T13 |
109 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8197892 |
1 |
|
|
T1 |
989 |
|
T2 |
386 |
|
T11 |
135 |
| auto[1] |
6009851 |
1 |
|
|
T1 |
943 |
|
T2 |
552 |
|
T13 |
552 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2620382 |
1 |
|
|
T1 |
480 |
|
T2 |
264 |
|
T13 |
139 |
| auto[1] |
auto[0] |
auto[1] |
381335 |
1 |
|
|
T1 |
12 |
|
T2 |
11 |
|
T13 |
33 |
| auto[1] |
auto[1] |
auto[0] |
2624300 |
1 |
|
|
T1 |
433 |
|
T2 |
271 |
|
T13 |
304 |
| auto[1] |
auto[1] |
auto[1] |
383834 |
1 |
|
|
T1 |
18 |
|
T2 |
6 |
|
T13 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |