Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8213459 |
1 |
|
|
T1 |
1040 |
|
T2 |
530 |
|
T11 |
135 |
| auto[1] |
5994284 |
1 |
|
|
T1 |
892 |
|
T2 |
408 |
|
T13 |
596 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13446773 |
1 |
|
|
T1 |
1895 |
|
T2 |
921 |
|
T11 |
135 |
| auto[1] |
760970 |
1 |
|
|
T1 |
37 |
|
T2 |
17 |
|
T13 |
70 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8213564 |
1 |
|
|
T1 |
857 |
|
T2 |
497 |
|
T11 |
135 |
| auto[1] |
5994179 |
1 |
|
|
T1 |
1075 |
|
T2 |
441 |
|
T13 |
385 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2620495 |
1 |
|
|
T1 |
535 |
|
T2 |
262 |
|
T13 |
118 |
| auto[1] |
auto[0] |
auto[1] |
380815 |
1 |
|
|
T1 |
23 |
|
T2 |
12 |
|
T13 |
20 |
| auto[1] |
auto[1] |
auto[0] |
2612714 |
1 |
|
|
T1 |
503 |
|
T2 |
162 |
|
T13 |
197 |
| auto[1] |
auto[1] |
auto[1] |
380155 |
1 |
|
|
T1 |
14 |
|
T2 |
5 |
|
T13 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |