Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8173634 |
1 |
|
|
T1 |
960 |
|
T2 |
504 |
|
T11 |
135 |
| auto[1] |
6034109 |
1 |
|
|
T1 |
972 |
|
T2 |
434 |
|
T13 |
583 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13450452 |
1 |
|
|
T1 |
1897 |
|
T2 |
915 |
|
T11 |
135 |
| auto[1] |
757291 |
1 |
|
|
T1 |
35 |
|
T2 |
23 |
|
T13 |
73 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239399 |
1 |
|
|
T1 |
1046 |
|
T2 |
481 |
|
T11 |
135 |
| auto[1] |
5968344 |
1 |
|
|
T1 |
886 |
|
T2 |
457 |
|
T13 |
414 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2591670 |
1 |
|
|
T1 |
390 |
|
T2 |
228 |
|
T13 |
136 |
| auto[1] |
auto[0] |
auto[1] |
375238 |
1 |
|
|
T1 |
19 |
|
T2 |
11 |
|
T13 |
28 |
| auto[1] |
auto[1] |
auto[0] |
2619383 |
1 |
|
|
T1 |
461 |
|
T2 |
206 |
|
T13 |
205 |
| auto[1] |
auto[1] |
auto[1] |
382053 |
1 |
|
|
T1 |
16 |
|
T2 |
12 |
|
T13 |
45 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |