Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 944
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T762 /workspace/coverage/cover_reg_top/16.gpio_intr_test.2505832737 Jul 22 04:32:18 PM PDT 24 Jul 22 04:32:20 PM PDT 24 32886463 ps
T763 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3322758908 Jul 22 04:34:13 PM PDT 24 Jul 22 04:34:14 PM PDT 24 13167481 ps
T764 /workspace/coverage/cover_reg_top/34.gpio_intr_test.168673860 Jul 22 04:32:26 PM PDT 24 Jul 22 04:32:33 PM PDT 24 31722241 ps
T765 /workspace/coverage/cover_reg_top/39.gpio_intr_test.403894974 Jul 22 04:32:06 PM PDT 24 Jul 22 04:32:08 PM PDT 24 40659187 ps
T766 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2837541283 Jul 22 04:32:07 PM PDT 24 Jul 22 04:32:10 PM PDT 24 405156814 ps
T767 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.426697277 Jul 22 04:32:17 PM PDT 24 Jul 22 04:32:19 PM PDT 24 280676202 ps
T768 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3704827428 Jul 22 04:32:10 PM PDT 24 Jul 22 04:32:13 PM PDT 24 23575881 ps
T769 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1105942981 Jul 22 04:32:02 PM PDT 24 Jul 22 04:32:05 PM PDT 24 101239089 ps
T770 /workspace/coverage/cover_reg_top/22.gpio_intr_test.918605453 Jul 22 04:32:00 PM PDT 24 Jul 22 04:32:02 PM PDT 24 94186035 ps
T91 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1565325755 Jul 22 04:31:59 PM PDT 24 Jul 22 04:32:01 PM PDT 24 113462767 ps
T771 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1717411625 Jul 22 04:32:05 PM PDT 24 Jul 22 04:32:06 PM PDT 24 23602674 ps
T772 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.476265356 Jul 22 04:32:18 PM PDT 24 Jul 22 04:32:20 PM PDT 24 14815672 ps
T39 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1526975992 Jul 22 04:32:05 PM PDT 24 Jul 22 04:32:07 PM PDT 24 122946150 ps
T773 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.908351296 Jul 22 04:31:59 PM PDT 24 Jul 22 04:32:01 PM PDT 24 60811013 ps
T774 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1062998704 Jul 22 04:34:26 PM PDT 24 Jul 22 04:34:27 PM PDT 24 31794470 ps
T775 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1103190650 Jul 22 04:32:19 PM PDT 24 Jul 22 04:32:22 PM PDT 24 38079170 ps
T776 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.568222652 Jul 22 04:32:02 PM PDT 24 Jul 22 04:32:06 PM PDT 24 456497072 ps
T777 /workspace/coverage/cover_reg_top/40.gpio_intr_test.41295910 Jul 22 04:32:08 PM PDT 24 Jul 22 04:32:11 PM PDT 24 65880839 ps
T778 /workspace/coverage/cover_reg_top/43.gpio_intr_test.537444208 Jul 22 04:32:07 PM PDT 24 Jul 22 04:32:09 PM PDT 24 17575140 ps
T779 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3125266100 Jul 22 04:32:03 PM PDT 24 Jul 22 04:32:05 PM PDT 24 26036663 ps
T780 /workspace/coverage/cover_reg_top/12.gpio_intr_test.3196902973 Jul 22 04:32:03 PM PDT 24 Jul 22 04:32:05 PM PDT 24 11008876 ps
T781 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1051085439 Jul 22 04:32:25 PM PDT 24 Jul 22 04:32:26 PM PDT 24 48295210 ps
T782 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4110148086 Jul 22 04:32:11 PM PDT 24 Jul 22 04:32:14 PM PDT 24 39863505 ps
T783 /workspace/coverage/cover_reg_top/2.gpio_intr_test.4026875982 Jul 22 04:34:13 PM PDT 24 Jul 22 04:34:14 PM PDT 24 41126399 ps
T784 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.217519592 Jul 22 04:32:08 PM PDT 24 Jul 22 04:32:13 PM PDT 24 258064782 ps
T36 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.192384911 Jul 22 04:32:24 PM PDT 24 Jul 22 04:32:27 PM PDT 24 213662748 ps
T785 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1961485499 Jul 22 04:32:04 PM PDT 24 Jul 22 04:32:06 PM PDT 24 79379177 ps
T786 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2949692623 Jul 22 04:32:23 PM PDT 24 Jul 22 04:32:24 PM PDT 24 41665818 ps
T787 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1918726568 Jul 22 04:32:17 PM PDT 24 Jul 22 04:32:19 PM PDT 24 19603490 ps
T788 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4196301780 Jul 22 04:31:45 PM PDT 24 Jul 22 04:31:47 PM PDT 24 68266528 ps
T789 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1552165420 Jul 22 04:31:59 PM PDT 24 Jul 22 04:32:01 PM PDT 24 20176299 ps
T790 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.514606404 Jul 22 04:32:24 PM PDT 24 Jul 22 04:32:26 PM PDT 24 75654160 ps
T40 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.983532135 Jul 22 04:32:07 PM PDT 24 Jul 22 04:32:10 PM PDT 24 195426977 ps
T791 /workspace/coverage/cover_reg_top/29.gpio_intr_test.120559887 Jul 22 04:32:25 PM PDT 24 Jul 22 04:32:27 PM PDT 24 26195024 ps
T792 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3330927208 Jul 22 04:32:07 PM PDT 24 Jul 22 04:32:09 PM PDT 24 17395773 ps
T793 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1959213739 Jul 22 04:32:09 PM PDT 24 Jul 22 04:32:15 PM PDT 24 539456391 ps
T794 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.160498701 Jul 22 04:32:26 PM PDT 24 Jul 22 04:32:28 PM PDT 24 15838481 ps
T795 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2768227913 Jul 22 04:32:02 PM PDT 24 Jul 22 04:32:03 PM PDT 24 65164708 ps
T796 /workspace/coverage/cover_reg_top/42.gpio_intr_test.19337297 Jul 22 04:32:22 PM PDT 24 Jul 22 04:32:23 PM PDT 24 38056716 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3009862033 Jul 22 04:31:54 PM PDT 24 Jul 22 04:31:55 PM PDT 24 18489036 ps
T798 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2038083497 Jul 22 04:32:09 PM PDT 24 Jul 22 04:32:12 PM PDT 24 20427570 ps
T799 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3850800385 Jul 22 04:32:33 PM PDT 24 Jul 22 04:32:35 PM PDT 24 41118320 ps
T88 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2101879997 Jul 22 04:32:13 PM PDT 24 Jul 22 04:32:17 PM PDT 24 77433458 ps
T800 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3289618623 Jul 22 04:32:16 PM PDT 24 Jul 22 04:32:19 PM PDT 24 21742470 ps
T801 /workspace/coverage/cover_reg_top/38.gpio_intr_test.461368477 Jul 22 04:32:09 PM PDT 24 Jul 22 04:32:12 PM PDT 24 56731446 ps
T802 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2715265099 Jul 22 04:32:03 PM PDT 24 Jul 22 04:32:06 PM PDT 24 93397458 ps
T37 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3389744263 Jul 22 04:32:26 PM PDT 24 Jul 22 04:32:28 PM PDT 24 99116170 ps
T803 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.724974312 Jul 22 04:31:56 PM PDT 24 Jul 22 04:31:59 PM PDT 24 95959994 ps
T804 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1330511690 Jul 22 04:32:10 PM PDT 24 Jul 22 04:32:13 PM PDT 24 120966036 ps
T805 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3693311600 Jul 22 04:32:11 PM PDT 24 Jul 22 04:32:14 PM PDT 24 72394284 ps
T38 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2061207945 Jul 22 04:32:11 PM PDT 24 Jul 22 04:32:15 PM PDT 24 413836214 ps
T806 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2681730795 Jul 22 04:32:14 PM PDT 24 Jul 22 04:32:17 PM PDT 24 35245791 ps
T807 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.450225347 Jul 22 04:32:06 PM PDT 24 Jul 22 04:32:08 PM PDT 24 43031592 ps
T808 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2693143633 Jul 22 04:31:58 PM PDT 24 Jul 22 04:32:00 PM PDT 24 1150483510 ps
T809 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1523971689 Jul 22 04:32:27 PM PDT 24 Jul 22 04:32:29 PM PDT 24 59311108 ps
T115 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2460980984 Jul 22 04:34:26 PM PDT 24 Jul 22 04:34:28 PM PDT 24 602469126 ps
T810 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1510058813 Jul 22 04:32:08 PM PDT 24 Jul 22 04:32:11 PM PDT 24 14888999 ps
T811 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3258414751 Jul 22 04:32:28 PM PDT 24 Jul 22 04:32:30 PM PDT 24 63611619 ps
T812 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.28696207 Jul 22 04:34:26 PM PDT 24 Jul 22 04:34:30 PM PDT 24 275254073 ps
T813 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.277127948 Jul 22 04:32:09 PM PDT 24 Jul 22 04:32:13 PM PDT 24 17992484 ps
T814 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.738848228 Jul 22 04:31:59 PM PDT 24 Jul 22 04:32:00 PM PDT 24 208874361 ps
T815 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.238224224 Jul 22 04:32:08 PM PDT 24 Jul 22 04:32:12 PM PDT 24 226651798 ps
T816 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3693142948 Jul 22 04:32:12 PM PDT 24 Jul 22 04:32:15 PM PDT 24 151951437 ps
T817 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2926318678 Jul 22 04:32:07 PM PDT 24 Jul 22 04:32:08 PM PDT 24 23172780 ps
T41 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1095567770 Jul 22 04:31:55 PM PDT 24 Jul 22 04:31:57 PM PDT 24 308049346 ps
T818 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1094671121 Jul 22 04:32:11 PM PDT 24 Jul 22 04:32:16 PM PDT 24 1845639992 ps
T89 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3809481773 Jul 22 04:31:41 PM PDT 24 Jul 22 04:31:43 PM PDT 24 126027928 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.743970672 Jul 22 04:32:04 PM PDT 24 Jul 22 04:32:07 PM PDT 24 105061523 ps
T90 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1509066390 Jul 22 04:32:12 PM PDT 24 Jul 22 04:32:18 PM PDT 24 523202564 ps
T820 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1505154250 Jul 22 04:31:55 PM PDT 24 Jul 22 04:31:57 PM PDT 24 32563373 ps
T821 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.901637107 Jul 22 04:31:58 PM PDT 24 Jul 22 04:32:00 PM PDT 24 253201800 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3821420492 Jul 22 04:32:30 PM PDT 24 Jul 22 04:32:32 PM PDT 24 87054499 ps
T823 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.432692406 Jul 22 04:32:31 PM PDT 24 Jul 22 04:32:35 PM PDT 24 100678763 ps
T824 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2133616161 Jul 22 04:32:09 PM PDT 24 Jul 22 04:32:12 PM PDT 24 136366820 ps
T825 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3032352176 Jul 22 04:32:05 PM PDT 24 Jul 22 04:32:06 PM PDT 24 11782741 ps
T826 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.525929910 Jul 22 04:32:25 PM PDT 24 Jul 22 04:32:33 PM PDT 24 135422825 ps
T827 /workspace/coverage/cover_reg_top/21.gpio_intr_test.853292694 Jul 22 04:32:09 PM PDT 24 Jul 22 04:32:12 PM PDT 24 21805079 ps
T828 /workspace/coverage/cover_reg_top/24.gpio_intr_test.963444477 Jul 22 04:32:12 PM PDT 24 Jul 22 04:32:15 PM PDT 24 74937543 ps
T829 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3844222532 Jul 22 04:32:15 PM PDT 24 Jul 22 04:32:18 PM PDT 24 13544379 ps
T830 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1904331466 Jul 22 04:32:13 PM PDT 24 Jul 22 04:32:17 PM PDT 24 43147959 ps
T831 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1463230455 Jul 22 04:31:52 PM PDT 24 Jul 22 04:31:53 PM PDT 24 35079389 ps
T832 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1636888164 Jul 22 04:33:02 PM PDT 24 Jul 22 04:33:06 PM PDT 24 106190129 ps
T833 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1312614070 Jul 22 04:32:00 PM PDT 24 Jul 22 04:32:01 PM PDT 24 33077098 ps
T834 /workspace/coverage/cover_reg_top/26.gpio_intr_test.925337925 Jul 22 04:32:18 PM PDT 24 Jul 22 04:32:21 PM PDT 24 43156916 ps
T835 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2505008848 Jul 22 04:32:03 PM PDT 24 Jul 22 04:32:05 PM PDT 24 80828449 ps
T836 /workspace/coverage/cover_reg_top/25.gpio_intr_test.3809587261 Jul 22 04:32:10 PM PDT 24 Jul 22 04:32:13 PM PDT 24 17544472 ps
T837 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3662039339 Jul 22 04:34:26 PM PDT 24 Jul 22 04:34:27 PM PDT 24 23122697 ps
T838 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1840963548 Jul 22 04:32:15 PM PDT 24 Jul 22 04:32:18 PM PDT 24 15225313 ps
T839 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.893134948 Jul 22 04:32:08 PM PDT 24 Jul 22 04:32:10 PM PDT 24 34890187 ps
T840 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.390475985 Jul 22 04:32:17 PM PDT 24 Jul 22 04:32:20 PM PDT 24 84319170 ps
T841 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3154131955 Jul 22 04:31:57 PM PDT 24 Jul 22 04:31:58 PM PDT 24 99652315 ps
T842 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1296626802 Jul 22 04:32:01 PM PDT 24 Jul 22 04:32:04 PM PDT 24 87516893 ps
T843 /workspace/coverage/cover_reg_top/32.gpio_intr_test.4055931083 Jul 22 04:32:26 PM PDT 24 Jul 22 04:32:27 PM PDT 24 14322789 ps
T844 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2358109624 Jul 22 04:32:00 PM PDT 24 Jul 22 04:32:01 PM PDT 24 11653868 ps
T845 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4085599998 Jul 22 04:37:25 PM PDT 24 Jul 22 04:37:27 PM PDT 24 49264245 ps
T846 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.564663154 Jul 22 04:37:17 PM PDT 24 Jul 22 04:37:19 PM PDT 24 90345760 ps
T847 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3961169497 Jul 22 04:37:23 PM PDT 24 Jul 22 04:37:24 PM PDT 24 182736571 ps
T848 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.688956428 Jul 22 04:37:26 PM PDT 24 Jul 22 04:37:28 PM PDT 24 216771763 ps
T849 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.796715531 Jul 22 04:36:25 PM PDT 24 Jul 22 04:36:26 PM PDT 24 67488813 ps
T850 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.576040503 Jul 22 04:36:56 PM PDT 24 Jul 22 04:36:57 PM PDT 24 147861342 ps
T851 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1687734923 Jul 22 04:37:23 PM PDT 24 Jul 22 04:37:25 PM PDT 24 50831179 ps
T852 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4126142843 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:26 PM PDT 24 151554563 ps
T853 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2583926295 Jul 22 04:37:41 PM PDT 24 Jul 22 04:37:42 PM PDT 24 164719160 ps
T854 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.143589996 Jul 22 04:37:04 PM PDT 24 Jul 22 04:37:05 PM PDT 24 143981034 ps
T855 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.869152496 Jul 22 04:37:05 PM PDT 24 Jul 22 04:37:07 PM PDT 24 73792724 ps
T856 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.561876764 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:26 PM PDT 24 234307757 ps
T857 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037116261 Jul 22 04:37:05 PM PDT 24 Jul 22 04:37:07 PM PDT 24 393367536 ps
T858 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3010829418 Jul 22 04:36:16 PM PDT 24 Jul 22 04:36:18 PM PDT 24 85889379 ps
T859 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.868920941 Jul 22 04:36:35 PM PDT 24 Jul 22 04:36:36 PM PDT 24 37838547 ps
T860 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1792569068 Jul 22 04:36:47 PM PDT 24 Jul 22 04:36:48 PM PDT 24 151626606 ps
T861 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2578733041 Jul 22 04:36:57 PM PDT 24 Jul 22 04:36:58 PM PDT 24 40427382 ps
T862 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1587831497 Jul 22 04:36:43 PM PDT 24 Jul 22 04:36:45 PM PDT 24 40789875 ps
T863 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3720012738 Jul 22 04:37:13 PM PDT 24 Jul 22 04:37:15 PM PDT 24 161784757 ps
T864 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054858086 Jul 22 04:36:52 PM PDT 24 Jul 22 04:36:54 PM PDT 24 43412084 ps
T865 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2089648659 Jul 22 04:37:25 PM PDT 24 Jul 22 04:37:27 PM PDT 24 90635766 ps
T866 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.106227391 Jul 22 04:36:55 PM PDT 24 Jul 22 04:36:57 PM PDT 24 75567321 ps
T867 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4161985401 Jul 22 04:37:04 PM PDT 24 Jul 22 04:37:05 PM PDT 24 55500267 ps
T868 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1213139252 Jul 22 04:37:05 PM PDT 24 Jul 22 04:37:06 PM PDT 24 34689631 ps
T869 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1823289801 Jul 22 04:37:05 PM PDT 24 Jul 22 04:37:07 PM PDT 24 263254975 ps
T870 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.514479284 Jul 22 04:37:59 PM PDT 24 Jul 22 04:38:01 PM PDT 24 97680231 ps
T871 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1601636401 Jul 22 04:37:23 PM PDT 24 Jul 22 04:37:25 PM PDT 24 773424556 ps
T872 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.296950297 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:26 PM PDT 24 65029184 ps
T873 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.111240466 Jul 22 04:37:23 PM PDT 24 Jul 22 04:37:24 PM PDT 24 129895699 ps
T874 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3634194474 Jul 22 04:37:07 PM PDT 24 Jul 22 04:37:09 PM PDT 24 161338165 ps
T875 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2916121538 Jul 22 04:36:47 PM PDT 24 Jul 22 04:36:49 PM PDT 24 161522147 ps
T876 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.138689847 Jul 22 04:37:06 PM PDT 24 Jul 22 04:37:07 PM PDT 24 38401524 ps
T877 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.407711730 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:27 PM PDT 24 185883104 ps
T878 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.848618383 Jul 22 04:36:17 PM PDT 24 Jul 22 04:36:18 PM PDT 24 33302674 ps
T879 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1046931964 Jul 22 04:37:26 PM PDT 24 Jul 22 04:37:28 PM PDT 24 418347349 ps
T880 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1656804817 Jul 22 04:36:26 PM PDT 24 Jul 22 04:36:28 PM PDT 24 277966579 ps
T881 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.757383400 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:27 PM PDT 24 73237401 ps
T882 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1384399604 Jul 22 04:36:57 PM PDT 24 Jul 22 04:36:59 PM PDT 24 262766667 ps
T883 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.914054679 Jul 22 04:37:27 PM PDT 24 Jul 22 04:37:29 PM PDT 24 55582646 ps
T884 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3012923807 Jul 22 04:36:26 PM PDT 24 Jul 22 04:36:27 PM PDT 24 229766980 ps
T885 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3000891861 Jul 22 04:37:06 PM PDT 24 Jul 22 04:37:08 PM PDT 24 674262333 ps
T886 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.158284532 Jul 22 04:36:52 PM PDT 24 Jul 22 04:36:54 PM PDT 24 123420632 ps
T887 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1626632259 Jul 22 04:36:54 PM PDT 24 Jul 22 04:36:57 PM PDT 24 99447995 ps
T888 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2939760829 Jul 22 04:36:56 PM PDT 24 Jul 22 04:36:58 PM PDT 24 197055079 ps
T889 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2232432166 Jul 22 04:36:38 PM PDT 24 Jul 22 04:36:40 PM PDT 24 69339923 ps
T890 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1719850426 Jul 22 04:37:25 PM PDT 24 Jul 22 04:37:27 PM PDT 24 167858634 ps
T891 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2224548393 Jul 22 04:36:26 PM PDT 24 Jul 22 04:36:28 PM PDT 24 640166904 ps
T892 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1348949951 Jul 22 04:37:23 PM PDT 24 Jul 22 04:37:24 PM PDT 24 22106813 ps
T893 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2916977185 Jul 22 04:36:25 PM PDT 24 Jul 22 04:36:27 PM PDT 24 67059029 ps
T894 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2905008296 Jul 22 04:37:26 PM PDT 24 Jul 22 04:37:28 PM PDT 24 731823330 ps
T895 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1258234302 Jul 22 04:36:48 PM PDT 24 Jul 22 04:36:50 PM PDT 24 182461377 ps
T896 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1037776996 Jul 22 04:37:15 PM PDT 24 Jul 22 04:37:16 PM PDT 24 43266651 ps
T897 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1772505147 Jul 22 04:37:07 PM PDT 24 Jul 22 04:37:09 PM PDT 24 68218031 ps
T898 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3206185410 Jul 22 04:36:38 PM PDT 24 Jul 22 04:36:40 PM PDT 24 74981645 ps
T899 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.82748444 Jul 22 04:36:47 PM PDT 24 Jul 22 04:36:49 PM PDT 24 398482746 ps
T900 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.680445850 Jul 22 04:36:25 PM PDT 24 Jul 22 04:36:27 PM PDT 24 127847597 ps
T901 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3027610300 Jul 22 04:37:26 PM PDT 24 Jul 22 04:37:28 PM PDT 24 27943304 ps
T902 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2884433813 Jul 22 04:36:40 PM PDT 24 Jul 22 04:36:41 PM PDT 24 37145328 ps
T903 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3707485032 Jul 22 04:37:41 PM PDT 24 Jul 22 04:37:43 PM PDT 24 80398724 ps
T904 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2226602242 Jul 22 04:37:06 PM PDT 24 Jul 22 04:37:07 PM PDT 24 28892555 ps
T905 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.998254592 Jul 22 04:36:40 PM PDT 24 Jul 22 04:36:42 PM PDT 24 554197956 ps
T906 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2438868349 Jul 22 04:37:10 PM PDT 24 Jul 22 04:37:12 PM PDT 24 106200074 ps
T907 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2985686576 Jul 22 04:36:55 PM PDT 24 Jul 22 04:36:57 PM PDT 24 103845544 ps
T908 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2472833056 Jul 22 04:36:55 PM PDT 24 Jul 22 04:36:57 PM PDT 24 119257195 ps
T909 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3631124511 Jul 22 04:37:39 PM PDT 24 Jul 22 04:37:41 PM PDT 24 75739859 ps
T910 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807669255 Jul 22 04:36:55 PM PDT 24 Jul 22 04:36:57 PM PDT 24 63516663 ps
T911 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2414892339 Jul 22 04:36:47 PM PDT 24 Jul 22 04:36:49 PM PDT 24 40283506 ps
T912 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2451740038 Jul 22 04:36:56 PM PDT 24 Jul 22 04:36:57 PM PDT 24 56871554 ps
T913 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2464074632 Jul 22 04:36:17 PM PDT 24 Jul 22 04:36:18 PM PDT 24 33235640 ps
T914 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2044266236 Jul 22 04:37:15 PM PDT 24 Jul 22 04:37:17 PM PDT 24 49370300 ps
T915 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.791377630 Jul 22 04:37:06 PM PDT 24 Jul 22 04:37:08 PM PDT 24 49039762 ps
T916 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.721732260 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:27 PM PDT 24 120520696 ps
T917 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.958967863 Jul 22 04:36:39 PM PDT 24 Jul 22 04:36:41 PM PDT 24 146911640 ps
T918 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1563154855 Jul 22 04:38:23 PM PDT 24 Jul 22 04:38:24 PM PDT 24 151425841 ps
T919 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3036319073 Jul 22 04:37:41 PM PDT 24 Jul 22 04:37:42 PM PDT 24 26861902 ps
T920 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2281927578 Jul 22 04:36:47 PM PDT 24 Jul 22 04:36:49 PM PDT 24 71721812 ps
T921 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1024817628 Jul 22 04:37:15 PM PDT 24 Jul 22 04:37:17 PM PDT 24 88717535 ps
T922 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2953165873 Jul 22 04:36:55 PM PDT 24 Jul 22 04:36:57 PM PDT 24 174395763 ps
T923 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2673791317 Jul 22 04:37:05 PM PDT 24 Jul 22 04:37:07 PM PDT 24 292208956 ps
T924 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3903477474 Jul 22 04:37:03 PM PDT 24 Jul 22 04:37:05 PM PDT 24 633116222 ps
T925 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1415764017 Jul 22 04:36:54 PM PDT 24 Jul 22 04:36:56 PM PDT 24 109518704 ps
T926 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2920584391 Jul 22 04:36:39 PM PDT 24 Jul 22 04:36:41 PM PDT 24 50604971 ps
T927 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2679881353 Jul 22 04:36:43 PM PDT 24 Jul 22 04:36:45 PM PDT 24 224470384 ps
T928 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1315252617 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:27 PM PDT 24 179392385 ps
T929 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1854994210 Jul 22 04:37:15 PM PDT 24 Jul 22 04:37:17 PM PDT 24 43248529 ps
T930 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1132912824 Jul 22 04:37:03 PM PDT 24 Jul 22 04:37:05 PM PDT 24 67878985 ps
T931 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3542421272 Jul 22 04:37:40 PM PDT 24 Jul 22 04:37:42 PM PDT 24 163146797 ps
T932 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1264983847 Jul 22 04:36:43 PM PDT 24 Jul 22 04:36:44 PM PDT 24 165367406 ps
T933 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2269709892 Jul 22 04:37:06 PM PDT 24 Jul 22 04:37:08 PM PDT 24 39564377 ps
T934 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2428496743 Jul 22 04:37:33 PM PDT 24 Jul 22 04:37:35 PM PDT 24 78110414 ps
T935 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3876582972 Jul 22 04:36:26 PM PDT 24 Jul 22 04:36:27 PM PDT 24 51880777 ps
T936 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1288490061 Jul 22 04:36:56 PM PDT 24 Jul 22 04:36:58 PM PDT 24 110517229 ps
T937 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3582476900 Jul 22 04:37:15 PM PDT 24 Jul 22 04:37:17 PM PDT 24 105426611 ps
T938 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.723338387 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:26 PM PDT 24 60295492 ps
T939 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3135024050 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:25 PM PDT 24 222002675 ps
T940 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2319798957 Jul 22 04:36:55 PM PDT 24 Jul 22 04:36:57 PM PDT 24 321949074 ps
T941 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1388340367 Jul 22 04:37:06 PM PDT 24 Jul 22 04:37:08 PM PDT 24 69268907 ps
T942 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3963546373 Jul 22 04:37:41 PM PDT 24 Jul 22 04:37:42 PM PDT 24 206620600 ps
T943 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3577461132 Jul 22 04:37:24 PM PDT 24 Jul 22 04:37:26 PM PDT 24 60825605 ps
T944 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3317304437 Jul 22 04:36:52 PM PDT 24 Jul 22 04:36:54 PM PDT 24 245374184 ps

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4086984078
Short name T14
Test name
Test status
Simulation time 208283869 ps
CPU time 4.05 seconds
Started Jul 22 04:38:18 PM PDT 24
Finished Jul 22 04:38:23 PM PDT 24
Peak memory 198440 kb
Host smart-2b103f25-7306-46e4-a921-e0ad273b439e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086984078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4086984078
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2319489865
Short name T116
Test name
Test status
Simulation time 137429171 ps
CPU time 2.91 seconds
Started Jul 22 04:40:01 PM PDT 24
Finished Jul 22 04:40:05 PM PDT 24
Peak memory 198436 kb
Host smart-739f9482-357f-4cc1-b87c-7fd5c2c25d8d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319489865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2319489865
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3595503777
Short name T21
Test name
Test status
Simulation time 122583312552 ps
CPU time 1436.18 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 05:04:26 PM PDT 24
Peak memory 198704 kb
Host smart-352598ac-0ece-4933-ad52-6a6371c3eeb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3595503777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3595503777
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3626625333
Short name T78
Test name
Test status
Simulation time 80952787 ps
CPU time 0.7 seconds
Started Jul 22 04:31:46 PM PDT 24
Finished Jul 22 04:31:48 PM PDT 24
Peak memory 195612 kb
Host smart-a724577c-4fb5-43ac-aff4-d44456e7799e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626625333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3626625333
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3482342270
Short name T27
Test name
Test status
Simulation time 107985010 ps
CPU time 1.28 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:11 PM PDT 24
Peak memory 198208 kb
Host smart-62d352e4-4966-4734-9f9f-147042ae0d78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482342270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3482342270
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2402851683
Short name T3
Test name
Test status
Simulation time 568343361 ps
CPU time 3.45 seconds
Started Jul 22 04:39:42 PM PDT 24
Finished Jul 22 04:39:47 PM PDT 24
Peak memory 198372 kb
Host smart-626a959d-412a-4371-9956-ed9674916fca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402851683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2402851683
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1821183012
Short name T143
Test name
Test status
Simulation time 42496271 ps
CPU time 0.56 seconds
Started Jul 22 04:37:35 PM PDT 24
Finished Jul 22 04:37:36 PM PDT 24
Peak memory 194276 kb
Host smart-a8b139d6-0e3a-4ccb-99c8-0d7da62fb473
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821183012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1821183012
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2601137519
Short name T30
Test name
Test status
Simulation time 69722368 ps
CPU time 0.83 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:37:35 PM PDT 24
Peak memory 214252 kb
Host smart-30ea6c06-65e3-44d8-88fe-0d2ca4250a73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601137519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2601137519
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3389744263
Short name T37
Test name
Test status
Simulation time 99116170 ps
CPU time 1.3 seconds
Started Jul 22 04:32:26 PM PDT 24
Finished Jul 22 04:32:28 PM PDT 24
Peak memory 198276 kb
Host smart-d16059b7-b84e-4605-ac3e-8a11b36f63d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389744263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3389744263
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1045738140
Short name T104
Test name
Test status
Simulation time 39136024 ps
CPU time 0.67 seconds
Started Jul 22 04:31:55 PM PDT 24
Finished Jul 22 04:31:57 PM PDT 24
Peak memory 194920 kb
Host smart-48dacc4e-085f-4616-b22c-83d22af8a155
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045738140 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1045738140
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2135130376
Short name T28
Test name
Test status
Simulation time 82899220 ps
CPU time 1.18 seconds
Started Jul 22 04:32:05 PM PDT 24
Finished Jul 22 04:32:07 PM PDT 24
Peak memory 198388 kb
Host smart-4bf69e50-47a7-4dc3-8a5e-5535507f6633
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135130376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2135130376
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.28696207
Short name T812
Test name
Test status
Simulation time 275254073 ps
CPU time 3.04 seconds
Started Jul 22 04:34:26 PM PDT 24
Finished Jul 22 04:34:30 PM PDT 24
Peak memory 196888 kb
Host smart-3b53f181-da12-43e1-a2f5-fa9c5765216c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28696207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.28696207
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3809481773
Short name T89
Test name
Test status
Simulation time 126027928 ps
CPU time 0.69 seconds
Started Jul 22 04:31:41 PM PDT 24
Finished Jul 22 04:31:43 PM PDT 24
Peak memory 195372 kb
Host smart-28f5aaf7-1749-48d2-bb89-7d6baecff22c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809481773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3809481773
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1463230455
Short name T831
Test name
Test status
Simulation time 35079389 ps
CPU time 0.89 seconds
Started Jul 22 04:31:52 PM PDT 24
Finished Jul 22 04:31:53 PM PDT 24
Peak memory 198172 kb
Host smart-907774a1-685f-43df-aa9f-226f2898678b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463230455 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1463230455
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.669303677
Short name T748
Test name
Test status
Simulation time 49910622 ps
CPU time 0.63 seconds
Started Jul 22 04:31:52 PM PDT 24
Finished Jul 22 04:31:54 PM PDT 24
Peak memory 195808 kb
Host smart-29e52a45-69ce-4993-950c-9c3da2df7d98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669303677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.669303677
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2308606046
Short name T725
Test name
Test status
Simulation time 41927462 ps
CPU time 0.62 seconds
Started Jul 22 04:31:57 PM PDT 24
Finished Jul 22 04:31:59 PM PDT 24
Peak memory 193924 kb
Host smart-80de4b45-81f0-463c-b56b-3ccc6dfd7c86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308606046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2308606046
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1296626802
Short name T842
Test name
Test status
Simulation time 87516893 ps
CPU time 2.29 seconds
Started Jul 22 04:32:01 PM PDT 24
Finished Jul 22 04:32:04 PM PDT 24
Peak memory 198248 kb
Host smart-a4c21223-6b5a-4125-9675-468e4d7323e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296626802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1296626802
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.58322759
Short name T77
Test name
Test status
Simulation time 52626797 ps
CPU time 0.75 seconds
Started Jul 22 04:32:00 PM PDT 24
Finished Jul 22 04:32:01 PM PDT 24
Peak memory 196236 kb
Host smart-8f495495-8122-47b4-b2bb-0285a803e554
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58322759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
gpio_csr_aliasing.58322759
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.971281202
Short name T80
Test name
Test status
Simulation time 158070931 ps
CPU time 3.03 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:07 PM PDT 24
Peak memory 198188 kb
Host smart-26cafd68-5433-4010-9e09-01a7bc6270b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971281202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.971281202
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.450225347
Short name T807
Test name
Test status
Simulation time 43031592 ps
CPU time 0.64 seconds
Started Jul 22 04:32:06 PM PDT 24
Finished Jul 22 04:32:08 PM PDT 24
Peak memory 194960 kb
Host smart-86abd83b-08b5-40f2-95b0-d951a29dd06d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450225347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.450225347
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.386527305
Short name T744
Test name
Test status
Simulation time 24568140 ps
CPU time 0.75 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 198088 kb
Host smart-ce0d3ebe-9e4d-43f8-b888-d98bbea54c51
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386527305 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.386527305
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3396438275
Short name T86
Test name
Test status
Simulation time 13064413 ps
CPU time 0.6 seconds
Started Jul 22 04:32:15 PM PDT 24
Finished Jul 22 04:32:18 PM PDT 24
Peak memory 194980 kb
Host smart-4d256587-649a-4edd-a65d-db584a1934ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396438275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3396438275
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1006682927
Short name T721
Test name
Test status
Simulation time 46900768 ps
CPU time 0.62 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 193968 kb
Host smart-7f1a54ba-e659-48f4-aabc-1395a18a9d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006682927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1006682927
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1312614070
Short name T833
Test name
Test status
Simulation time 33077098 ps
CPU time 0.62 seconds
Started Jul 22 04:32:00 PM PDT 24
Finished Jul 22 04:32:01 PM PDT 24
Peak memory 195528 kb
Host smart-baaccdaf-ba55-45d3-9bb7-b97fa48354d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312614070 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1312614070
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1105942981
Short name T769
Test name
Test status
Simulation time 101239089 ps
CPU time 2.74 seconds
Started Jul 22 04:32:02 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 198288 kb
Host smart-4073e918-c3bb-455c-aa6c-a11581df1b1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105942981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1105942981
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.559686794
Short name T746
Test name
Test status
Simulation time 29318487 ps
CPU time 0.84 seconds
Started Jul 22 04:32:11 PM PDT 24
Finished Jul 22 04:32:14 PM PDT 24
Peak memory 198096 kb
Host smart-42bed37c-8296-4a88-acd2-5f118656069a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559686794 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.559686794
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.878617069
Short name T87
Test name
Test status
Simulation time 51281567 ps
CPU time 0.6 seconds
Started Jul 22 04:32:13 PM PDT 24
Finished Jul 22 04:32:15 PM PDT 24
Peak memory 194820 kb
Host smart-d418e0d0-f58b-48ee-9006-c0aee8920451
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878617069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.878617069
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2133616161
Short name T824
Test name
Test status
Simulation time 136366820 ps
CPU time 0.61 seconds
Started Jul 22 04:32:09 PM PDT 24
Finished Jul 22 04:32:12 PM PDT 24
Peak memory 194004 kb
Host smart-fc25681b-55e8-4617-ac9d-25456c62cfe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133616161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2133616161
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.4110148086
Short name T782
Test name
Test status
Simulation time 39863505 ps
CPU time 0.66 seconds
Started Jul 22 04:32:11 PM PDT 24
Finished Jul 22 04:32:14 PM PDT 24
Peak memory 195104 kb
Host smart-0c0d1b73-8463-4624-8931-6e7ea3927b37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110148086 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.4110148086
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.568222652
Short name T776
Test name
Test status
Simulation time 456497072 ps
CPU time 2.86 seconds
Started Jul 22 04:32:02 PM PDT 24
Finished Jul 22 04:32:06 PM PDT 24
Peak memory 198280 kb
Host smart-c8868bb5-b9f3-4288-89c5-c113c7e8cef2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568222652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.568222652
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1420081571
Short name T26
Test name
Test status
Simulation time 51111644 ps
CPU time 0.87 seconds
Started Jul 22 04:31:51 PM PDT 24
Finished Jul 22 04:31:53 PM PDT 24
Peak memory 197520 kb
Host smart-4f694be7-2b44-4812-9c6b-97edd8397d7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420081571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1420081571
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.390475985
Short name T840
Test name
Test status
Simulation time 84319170 ps
CPU time 0.75 seconds
Started Jul 22 04:32:17 PM PDT 24
Finished Jul 22 04:32:20 PM PDT 24
Peak memory 198144 kb
Host smart-c6897c4a-48f0-46b8-b024-3ec9dbc8a42f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390475985 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.390475985
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3862741817
Short name T749
Test name
Test status
Simulation time 17941169 ps
CPU time 0.55 seconds
Started Jul 22 04:32:19 PM PDT 24
Finished Jul 22 04:32:26 PM PDT 24
Peak memory 195356 kb
Host smart-ae59e19a-691d-4616-9143-daf5d6396111
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862741817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3862741817
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.970753717
Short name T760
Test name
Test status
Simulation time 67974143 ps
CPU time 0.58 seconds
Started Jul 22 04:32:11 PM PDT 24
Finished Jul 22 04:32:14 PM PDT 24
Peak memory 193896 kb
Host smart-84aef7d1-bbb4-4b8b-83c3-dcaf496db789
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970753717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.970753717
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2027141972
Short name T101
Test name
Test status
Simulation time 23752562 ps
CPU time 0.87 seconds
Started Jul 22 04:32:04 PM PDT 24
Finished Jul 22 04:32:06 PM PDT 24
Peak memory 197656 kb
Host smart-92b0f7fc-94dd-4941-b503-e22e5a8658e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027141972 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2027141972
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.525929910
Short name T826
Test name
Test status
Simulation time 135422825 ps
CPU time 2.27 seconds
Started Jul 22 04:32:25 PM PDT 24
Finished Jul 22 04:32:33 PM PDT 24
Peak memory 198284 kb
Host smart-44f4b3f1-0ff3-470d-8f10-38ff0044d1b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525929910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.525929910
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.238224224
Short name T815
Test name
Test status
Simulation time 226651798 ps
CPU time 1.4 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:12 PM PDT 24
Peak memory 198240 kb
Host smart-9236038a-ef2a-463d-bc8b-f3e4cf8dce16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238224224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.238224224
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2369476558
Short name T745
Test name
Test status
Simulation time 326113257 ps
CPU time 1.1 seconds
Started Jul 22 04:32:13 PM PDT 24
Finished Jul 22 04:32:17 PM PDT 24
Peak memory 198336 kb
Host smart-72d5f842-d7d6-4ad0-81ee-82c9bdf32655
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369476558 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2369476558
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.160498701
Short name T794
Test name
Test status
Simulation time 15838481 ps
CPU time 0.57 seconds
Started Jul 22 04:32:26 PM PDT 24
Finished Jul 22 04:32:28 PM PDT 24
Peak memory 194816 kb
Host smart-394c0f9c-5191-497b-a5c1-fbb7eb456c49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160498701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.160498701
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3196902973
Short name T780
Test name
Test status
Simulation time 11008876 ps
CPU time 0.59 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 193912 kb
Host smart-471bdfba-6055-46aa-9913-ec49fd3eca38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196902973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3196902973
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2404403377
Short name T108
Test name
Test status
Simulation time 17908509 ps
CPU time 0.72 seconds
Started Jul 22 04:32:17 PM PDT 24
Finished Jul 22 04:32:19 PM PDT 24
Peak memory 196264 kb
Host smart-b404d15a-a520-4a2b-91ac-545de4bb3876
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404403377 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2404403377
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1886495844
Short name T747
Test name
Test status
Simulation time 32106653 ps
CPU time 1.01 seconds
Started Jul 22 04:32:07 PM PDT 24
Finished Jul 22 04:32:10 PM PDT 24
Peak memory 198060 kb
Host smart-4af23eef-a30f-46c2-92ca-538c00307eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886495844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1886495844
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4175382232
Short name T728
Test name
Test status
Simulation time 65652431 ps
CPU time 1.01 seconds
Started Jul 22 04:32:20 PM PDT 24
Finished Jul 22 04:32:22 PM PDT 24
Peak memory 198168 kb
Host smart-3cab6338-6b0e-488d-9f78-37794194d015
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175382232 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4175382232
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2101879997
Short name T88
Test name
Test status
Simulation time 77433458 ps
CPU time 0.58 seconds
Started Jul 22 04:32:13 PM PDT 24
Finished Jul 22 04:32:17 PM PDT 24
Peak memory 195036 kb
Host smart-c7f0ce11-4797-4bae-885d-50c164353b69
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101879997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2101879997
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.326522815
Short name T756
Test name
Test status
Simulation time 38897719 ps
CPU time 0.61 seconds
Started Jul 22 04:32:06 PM PDT 24
Finished Jul 22 04:32:07 PM PDT 24
Peak memory 193976 kb
Host smart-30b8d74d-ebef-402a-8196-95d431000f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326522815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.326522815
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1103190650
Short name T775
Test name
Test status
Simulation time 38079170 ps
CPU time 0.85 seconds
Started Jul 22 04:32:19 PM PDT 24
Finished Jul 22 04:32:22 PM PDT 24
Peak memory 196556 kb
Host smart-9449bcc3-f3de-4753-9e6f-4d8af27da438
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103190650 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1103190650
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.432692406
Short name T823
Test name
Test status
Simulation time 100678763 ps
CPU time 2.42 seconds
Started Jul 22 04:32:31 PM PDT 24
Finished Jul 22 04:32:35 PM PDT 24
Peak memory 198332 kb
Host smart-40532fda-5601-42f2-a214-53edbf6548b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432692406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.432692406
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3693142948
Short name T816
Test name
Test status
Simulation time 151951437 ps
CPU time 1.11 seconds
Started Jul 22 04:32:12 PM PDT 24
Finished Jul 22 04:32:15 PM PDT 24
Peak memory 198252 kb
Host smart-3b20a125-b74b-4cce-ba78-115013e55796
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693142948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3693142948
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.577055844
Short name T751
Test name
Test status
Simulation time 63664180 ps
CPU time 0.67 seconds
Started Jul 22 04:34:26 PM PDT 24
Finished Jul 22 04:34:27 PM PDT 24
Peak memory 197480 kb
Host smart-47ed318c-90e8-4108-9ca6-0fbf9dc051ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577055844 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.577055844
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3850800385
Short name T799
Test name
Test status
Simulation time 41118320 ps
CPU time 0.62 seconds
Started Jul 22 04:32:33 PM PDT 24
Finished Jul 22 04:32:35 PM PDT 24
Peak memory 195332 kb
Host smart-9a776c97-3b46-4a6f-9567-08e9517dd59e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850800385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3850800385
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2038083497
Short name T798
Test name
Test status
Simulation time 20427570 ps
CPU time 0.54 seconds
Started Jul 22 04:32:09 PM PDT 24
Finished Jul 22 04:32:12 PM PDT 24
Peak memory 193928 kb
Host smart-1837051f-9ba8-4c3c-9fe8-c146f3cf9def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038083497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2038083497
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3239827658
Short name T109
Test name
Test status
Simulation time 20242740 ps
CPU time 0.84 seconds
Started Jul 22 04:32:14 PM PDT 24
Finished Jul 22 04:32:17 PM PDT 24
Peak memory 196564 kb
Host smart-5e0bd76b-35c5-4955-903c-1b9074cb3063
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239827658 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3239827658
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.669390937
Short name T758
Test name
Test status
Simulation time 176779085 ps
CPU time 1.04 seconds
Started Jul 22 04:34:51 PM PDT 24
Finished Jul 22 04:34:53 PM PDT 24
Peak memory 198004 kb
Host smart-0601b04f-40d8-4268-b6dd-bb6bb3a51338
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669390937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.669390937
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1526975992
Short name T39
Test name
Test status
Simulation time 122946150 ps
CPU time 1.47 seconds
Started Jul 22 04:32:05 PM PDT 24
Finished Jul 22 04:32:07 PM PDT 24
Peak memory 198272 kb
Host smart-d9aee47f-d4f2-409c-a44d-eb259128a534
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526975992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1526975992
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3782746591
Short name T733
Test name
Test status
Simulation time 45531188 ps
CPU time 1.11 seconds
Started Jul 22 04:32:13 PM PDT 24
Finished Jul 22 04:32:16 PM PDT 24
Peak memory 198336 kb
Host smart-99b75548-f250-4b2e-adb8-9bb6932867e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782746591 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3782746591
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.131510967
Short name T83
Test name
Test status
Simulation time 12124135 ps
CPU time 0.58 seconds
Started Jul 22 04:32:07 PM PDT 24
Finished Jul 22 04:32:09 PM PDT 24
Peak memory 193804 kb
Host smart-3fc303e0-b4c6-42aa-b822-0c70cc08ee31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131510967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.131510967
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.744657363
Short name T722
Test name
Test status
Simulation time 17190448 ps
CPU time 0.57 seconds
Started Jul 22 04:32:18 PM PDT 24
Finished Jul 22 04:32:20 PM PDT 24
Peak memory 193900 kb
Host smart-9f9f9112-b242-431c-86df-c1f3b409183c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744657363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.744657363
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3258414751
Short name T811
Test name
Test status
Simulation time 63611619 ps
CPU time 0.64 seconds
Started Jul 22 04:32:28 PM PDT 24
Finished Jul 22 04:32:30 PM PDT 24
Peak memory 195116 kb
Host smart-f7b32b97-2810-44f8-be68-bb67aedb892a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258414751 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3258414751
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.538245286
Short name T734
Test name
Test status
Simulation time 615301114 ps
CPU time 3.04 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:08 PM PDT 24
Peak memory 198272 kb
Host smart-0aca416c-0fb7-4f70-8e43-f5ec1beca50e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538245286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.538245286
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.983532135
Short name T40
Test name
Test status
Simulation time 195426977 ps
CPU time 1.4 seconds
Started Jul 22 04:32:07 PM PDT 24
Finished Jul 22 04:32:10 PM PDT 24
Peak memory 198292 kb
Host smart-7a62ca73-8ddf-4985-be58-2dbca183a863
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983532135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.983532135
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.476265356
Short name T772
Test name
Test status
Simulation time 14815672 ps
CPU time 0.69 seconds
Started Jul 22 04:32:18 PM PDT 24
Finished Jul 22 04:32:20 PM PDT 24
Peak memory 196540 kb
Host smart-ab109e1f-26e6-42a4-b144-40943d5dcde3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476265356 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.476265356
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1710999440
Short name T737
Test name
Test status
Simulation time 12627899 ps
CPU time 0.59 seconds
Started Jul 22 04:32:14 PM PDT 24
Finished Jul 22 04:32:17 PM PDT 24
Peak memory 194916 kb
Host smart-d53ab6d7-73c6-437c-8e86-e33b03d99a3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710999440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1710999440
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.2505832737
Short name T762
Test name
Test status
Simulation time 32886463 ps
CPU time 0.62 seconds
Started Jul 22 04:32:18 PM PDT 24
Finished Jul 22 04:32:20 PM PDT 24
Peak memory 193928 kb
Host smart-6271dd4e-fcf0-4b22-8fbd-c5c3cca6edf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505832737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.2505832737
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1533326124
Short name T105
Test name
Test status
Simulation time 28824981 ps
CPU time 0.64 seconds
Started Jul 22 04:32:31 PM PDT 24
Finished Jul 22 04:32:33 PM PDT 24
Peak memory 195664 kb
Host smart-e4925c67-844b-4564-96f0-173cb7176f57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533326124 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1533326124
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1636888164
Short name T832
Test name
Test status
Simulation time 106190129 ps
CPU time 2.2 seconds
Started Jul 22 04:33:02 PM PDT 24
Finished Jul 22 04:33:06 PM PDT 24
Peak memory 198196 kb
Host smart-fef6ca10-548d-4c3b-abd1-dbe9c8619082
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636888164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1636888164
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2103546004
Short name T742
Test name
Test status
Simulation time 41587584 ps
CPU time 0.81 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 197648 kb
Host smart-13e3f45c-aa45-447d-9e04-bd8888831513
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103546004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2103546004
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3821420492
Short name T822
Test name
Test status
Simulation time 87054499 ps
CPU time 0.91 seconds
Started Jul 22 04:32:30 PM PDT 24
Finished Jul 22 04:32:32 PM PDT 24
Peak memory 198148 kb
Host smart-0884f8d7-4012-43f5-bf13-dc6feb55c48b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821420492 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3821420492
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3125266100
Short name T779
Test name
Test status
Simulation time 26036663 ps
CPU time 0.65 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 195336 kb
Host smart-d4c6a98e-a52c-4620-9ecb-4f781c5b8903
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125266100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3125266100
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2350872994
Short name T757
Test name
Test status
Simulation time 13066198 ps
CPU time 0.66 seconds
Started Jul 22 04:32:20 PM PDT 24
Finished Jul 22 04:32:22 PM PDT 24
Peak memory 194088 kb
Host smart-55081e7d-40f9-41da-b3d7-64a584e7cdbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350872994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2350872994
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.2379865517
Short name T81
Test name
Test status
Simulation time 70062640 ps
CPU time 0.88 seconds
Started Jul 22 04:32:05 PM PDT 24
Finished Jul 22 04:32:07 PM PDT 24
Peak memory 197432 kb
Host smart-9330723d-3ee7-44fa-90bb-8db4f837ffaf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379865517 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.2379865517
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1094671121
Short name T818
Test name
Test status
Simulation time 1845639992 ps
CPU time 2.62 seconds
Started Jul 22 04:32:11 PM PDT 24
Finished Jul 22 04:32:16 PM PDT 24
Peak memory 198276 kb
Host smart-eb81f004-b919-43eb-afaa-041ba0fd569a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094671121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1094671121
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2061207945
Short name T38
Test name
Test status
Simulation time 413836214 ps
CPU time 1.35 seconds
Started Jul 22 04:32:11 PM PDT 24
Finished Jul 22 04:32:15 PM PDT 24
Peak memory 198248 kb
Host smart-156668ce-9971-4e67-9269-fb3de7b9bf8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061207945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2061207945
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.507918318
Short name T726
Test name
Test status
Simulation time 35780323 ps
CPU time 0.91 seconds
Started Jul 22 04:32:10 PM PDT 24
Finished Jul 22 04:32:13 PM PDT 24
Peak memory 198172 kb
Host smart-0e580001-50cf-4c46-acbf-7b7f4479782a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507918318 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.507918318
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.65942699
Short name T79
Test name
Test status
Simulation time 14712591 ps
CPU time 0.65 seconds
Started Jul 22 04:32:01 PM PDT 24
Finished Jul 22 04:32:02 PM PDT 24
Peak memory 194876 kb
Host smart-eab1684c-691e-4641-8151-f41717ac12ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65942699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_
csr_rw.65942699
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2872744464
Short name T739
Test name
Test status
Simulation time 49260592 ps
CPU time 0.63 seconds
Started Jul 22 04:33:01 PM PDT 24
Finished Jul 22 04:33:03 PM PDT 24
Peak memory 193972 kb
Host smart-a41dec74-f5ed-4f18-9120-911716e16168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872744464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2872744464
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.514606404
Short name T790
Test name
Test status
Simulation time 75654160 ps
CPU time 0.85 seconds
Started Jul 22 04:32:24 PM PDT 24
Finished Jul 22 04:32:26 PM PDT 24
Peak memory 196544 kb
Host smart-82179a54-2702-4429-b5da-8ee7ca507fe4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514606404 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.514606404
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2454091809
Short name T732
Test name
Test status
Simulation time 112372059 ps
CPU time 1 seconds
Started Jul 22 04:32:15 PM PDT 24
Finished Jul 22 04:32:18 PM PDT 24
Peak memory 198004 kb
Host smart-24380e08-a47d-4e99-a177-99374df40053
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454091809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2454091809
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.743970672
Short name T819
Test name
Test status
Simulation time 105061523 ps
CPU time 1.21 seconds
Started Jul 22 04:32:04 PM PDT 24
Finished Jul 22 04:32:07 PM PDT 24
Peak memory 198260 kb
Host smart-7d438e9b-d357-499f-bc3b-38b703bc9ab8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743970672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.743970672
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1717411625
Short name T771
Test name
Test status
Simulation time 23602674 ps
CPU time 0.73 seconds
Started Jul 22 04:32:05 PM PDT 24
Finished Jul 22 04:32:06 PM PDT 24
Peak memory 198024 kb
Host smart-64bf8398-9e8d-4c5d-b4c0-d95dfb84fbb6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717411625 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1717411625
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1523971689
Short name T809
Test name
Test status
Simulation time 59311108 ps
CPU time 0.55 seconds
Started Jul 22 04:32:27 PM PDT 24
Finished Jul 22 04:32:29 PM PDT 24
Peak memory 194180 kb
Host smart-d135858e-a9fb-4ec7-aa74-da338ed093b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523971689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1523971689
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1224757621
Short name T731
Test name
Test status
Simulation time 59265919 ps
CPU time 0.6 seconds
Started Jul 22 04:32:27 PM PDT 24
Finished Jul 22 04:32:29 PM PDT 24
Peak memory 194644 kb
Host smart-11ff9518-c81c-4518-8105-31c367dec869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224757621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1224757621
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.501508206
Short name T103
Test name
Test status
Simulation time 63815816 ps
CPU time 0.64 seconds
Started Jul 22 04:32:17 PM PDT 24
Finished Jul 22 04:32:19 PM PDT 24
Peak memory 194784 kb
Host smart-b5335fa7-f89c-4fab-8d49-555d1fcd9315
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501508206 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.501508206
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.71031141
Short name T761
Test name
Test status
Simulation time 694969551 ps
CPU time 2.79 seconds
Started Jul 22 04:32:10 PM PDT 24
Finished Jul 22 04:32:15 PM PDT 24
Peak memory 198276 kb
Host smart-881435fa-4dd3-4710-a23e-508412c803bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71031141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.71031141
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.901637107
Short name T821
Test name
Test status
Simulation time 253201800 ps
CPU time 1.37 seconds
Started Jul 22 04:31:58 PM PDT 24
Finished Jul 22 04:32:00 PM PDT 24
Peak memory 198236 kb
Host smart-7e81517f-8c14-464c-a76c-a22af0fe2a42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901637107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.901637107
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.3009862033
Short name T797
Test name
Test status
Simulation time 18489036 ps
CPU time 0.68 seconds
Started Jul 22 04:31:54 PM PDT 24
Finished Jul 22 04:31:55 PM PDT 24
Peak memory 195236 kb
Host smart-259be42d-ce5e-43c8-9d8b-737c2b8ae8ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009862033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.3009862033
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.217519592
Short name T784
Test name
Test status
Simulation time 258064782 ps
CPU time 3.21 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:13 PM PDT 24
Peak memory 198176 kb
Host smart-cc82768c-379b-47bd-a86b-d1ff73e64764
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217519592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.217519592
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1402369113
Short name T752
Test name
Test status
Simulation time 53226981 ps
CPU time 0.61 seconds
Started Jul 22 04:31:54 PM PDT 24
Finished Jul 22 04:31:56 PM PDT 24
Peak memory 194812 kb
Host smart-6b6f7d87-3a87-42e3-ae61-d662eab31d9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402369113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1402369113
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2837541283
Short name T766
Test name
Test status
Simulation time 405156814 ps
CPU time 0.83 seconds
Started Jul 22 04:32:07 PM PDT 24
Finished Jul 22 04:32:10 PM PDT 24
Peak memory 198088 kb
Host smart-d6a7cb9a-8766-46b5-97e6-b049aef1cd86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837541283 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2837541283
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1062998704
Short name T774
Test name
Test status
Simulation time 31794470 ps
CPU time 0.59 seconds
Started Jul 22 04:34:26 PM PDT 24
Finished Jul 22 04:34:27 PM PDT 24
Peak memory 195540 kb
Host smart-d3afcf70-20c1-4053-b4df-5e8946df39ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062998704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1062998704
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.4026875982
Short name T783
Test name
Test status
Simulation time 41126399 ps
CPU time 0.57 seconds
Started Jul 22 04:34:13 PM PDT 24
Finished Jul 22 04:34:14 PM PDT 24
Peak memory 193868 kb
Host smart-b4cf42ad-ade8-4b4b-a620-a25e06881438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026875982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.4026875982
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3662039339
Short name T837
Test name
Test status
Simulation time 23122697 ps
CPU time 0.64 seconds
Started Jul 22 04:34:26 PM PDT 24
Finished Jul 22 04:34:27 PM PDT 24
Peak memory 194944 kb
Host smart-38161018-2f25-4718-b6ed-6ea959798fcb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662039339 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3662039339
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.426697277
Short name T767
Test name
Test status
Simulation time 280676202 ps
CPU time 1.05 seconds
Started Jul 22 04:32:17 PM PDT 24
Finished Jul 22 04:32:19 PM PDT 24
Peak memory 198060 kb
Host smart-37c034a1-9bf3-4c06-9653-8e99ecfc54b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426697277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.426697277
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.192384911
Short name T36
Test name
Test status
Simulation time 213662748 ps
CPU time 1.38 seconds
Started Jul 22 04:32:24 PM PDT 24
Finished Jul 22 04:32:27 PM PDT 24
Peak memory 198292 kb
Host smart-dc465aea-3ff3-420d-8a39-14e774ce745f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192384911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.192384911
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2358109624
Short name T844
Test name
Test status
Simulation time 11653868 ps
CPU time 0.65 seconds
Started Jul 22 04:32:00 PM PDT 24
Finished Jul 22 04:32:01 PM PDT 24
Peak memory 193988 kb
Host smart-bde8e14a-909f-4265-9596-4108fbc4775d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358109624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2358109624
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.853292694
Short name T827
Test name
Test status
Simulation time 21805079 ps
CPU time 0.58 seconds
Started Jul 22 04:32:09 PM PDT 24
Finished Jul 22 04:32:12 PM PDT 24
Peak memory 193944 kb
Host smart-f776fb81-787b-4866-8868-4a2a52afdc51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853292694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.853292694
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.918605453
Short name T770
Test name
Test status
Simulation time 94186035 ps
CPU time 0.59 seconds
Started Jul 22 04:32:00 PM PDT 24
Finished Jul 22 04:32:02 PM PDT 24
Peak memory 194604 kb
Host smart-c1403708-e7fa-4cef-b12a-ac6bb02dcf39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918605453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.918605453
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2926318678
Short name T817
Test name
Test status
Simulation time 23172780 ps
CPU time 0.57 seconds
Started Jul 22 04:32:07 PM PDT 24
Finished Jul 22 04:32:08 PM PDT 24
Peak memory 193936 kb
Host smart-12fff8f1-c596-4b2e-96d8-96c75f9dcaf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926318678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2926318678
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.963444477
Short name T828
Test name
Test status
Simulation time 74937543 ps
CPU time 0.63 seconds
Started Jul 22 04:32:12 PM PDT 24
Finished Jul 22 04:32:15 PM PDT 24
Peak memory 194012 kb
Host smart-700c5ed9-c7c3-4802-881d-59cdcb8d2e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963444477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.963444477
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3809587261
Short name T836
Test name
Test status
Simulation time 17544472 ps
CPU time 0.57 seconds
Started Jul 22 04:32:10 PM PDT 24
Finished Jul 22 04:32:13 PM PDT 24
Peak memory 193912 kb
Host smart-fbc22250-5f13-4ffc-bf91-ca7760e81773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809587261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3809587261
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.925337925
Short name T834
Test name
Test status
Simulation time 43156916 ps
CPU time 0.63 seconds
Started Jul 22 04:32:18 PM PDT 24
Finished Jul 22 04:32:21 PM PDT 24
Peak memory 194052 kb
Host smart-8344438c-5ce5-4bc9-8962-238e877a9b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925337925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.925337925
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3542358818
Short name T736
Test name
Test status
Simulation time 15044872 ps
CPU time 0.6 seconds
Started Jul 22 04:32:06 PM PDT 24
Finished Jul 22 04:32:08 PM PDT 24
Peak memory 194664 kb
Host smart-757d284c-be84-42d2-996c-b177d21f5954
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542358818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3542358818
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3330927208
Short name T792
Test name
Test status
Simulation time 17395773 ps
CPU time 0.6 seconds
Started Jul 22 04:32:07 PM PDT 24
Finished Jul 22 04:32:09 PM PDT 24
Peak memory 194668 kb
Host smart-31e30b9d-f5a1-49b2-81ae-d8a14c9bd672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330927208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3330927208
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.120559887
Short name T791
Test name
Test status
Simulation time 26195024 ps
CPU time 0.57 seconds
Started Jul 22 04:32:25 PM PDT 24
Finished Jul 22 04:32:27 PM PDT 24
Peak memory 194004 kb
Host smart-01dc70a1-a5a5-4723-93df-96a451656a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120559887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.120559887
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1505154250
Short name T820
Test name
Test status
Simulation time 32563373 ps
CPU time 0.75 seconds
Started Jul 22 04:31:55 PM PDT 24
Finished Jul 22 04:31:57 PM PDT 24
Peak memory 195624 kb
Host smart-6cc12150-e8b8-49ac-a803-e1b89a32c532
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505154250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1505154250
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1563512508
Short name T75
Test name
Test status
Simulation time 2051267587 ps
CPU time 3.36 seconds
Started Jul 22 04:31:53 PM PDT 24
Finished Jul 22 04:31:57 PM PDT 24
Peak memory 197128 kb
Host smart-32bd33f2-157a-401d-a4fa-9d47a68261e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563512508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1563512508
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4286972328
Short name T85
Test name
Test status
Simulation time 32057024 ps
CPU time 0.65 seconds
Started Jul 22 04:32:02 PM PDT 24
Finished Jul 22 04:32:04 PM PDT 24
Peak memory 194900 kb
Host smart-ee5720f1-f362-45ff-9147-ad2e42783718
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286972328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4286972328
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4100908950
Short name T724
Test name
Test status
Simulation time 34531106 ps
CPU time 1.68 seconds
Started Jul 22 04:32:10 PM PDT 24
Finished Jul 22 04:32:14 PM PDT 24
Peak memory 198380 kb
Host smart-bfe5db56-48f1-4f8a-941d-3ad773401a9c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100908950 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4100908950
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3322758908
Short name T763
Test name
Test status
Simulation time 13167481 ps
CPU time 0.57 seconds
Started Jul 22 04:34:13 PM PDT 24
Finished Jul 22 04:34:14 PM PDT 24
Peak memory 194180 kb
Host smart-867ff844-f3f0-4f5c-b83b-ac031647dc20
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322758908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3322758908
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2207740424
Short name T719
Test name
Test status
Simulation time 33632126 ps
CPU time 0.57 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:11 PM PDT 24
Peak memory 193948 kb
Host smart-ca41e727-3ec2-43d8-b421-016899c124ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207740424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2207740424
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.416719048
Short name T106
Test name
Test status
Simulation time 109994257 ps
CPU time 0.71 seconds
Started Jul 22 04:31:52 PM PDT 24
Finished Jul 22 04:31:54 PM PDT 24
Peak memory 196396 kb
Host smart-b966ce6e-4c9a-4bea-b77e-ee64aa82fb0e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416719048 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.416719048
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.24609088
Short name T754
Test name
Test status
Simulation time 667389808 ps
CPU time 1.74 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:06 PM PDT 24
Peak memory 198236 kb
Host smart-ce249d11-b2c7-42e6-9451-203b6cd93106
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24609088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.24609088
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1874091802
Short name T25
Test name
Test status
Simulation time 61555709 ps
CPU time 0.9 seconds
Started Jul 22 04:32:20 PM PDT 24
Finished Jul 22 04:32:22 PM PDT 24
Peak memory 197124 kb
Host smart-5e9a66b8-bbf9-4c3d-97e1-5108ded40e98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874091802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1874091802
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3032352176
Short name T825
Test name
Test status
Simulation time 11782741 ps
CPU time 0.57 seconds
Started Jul 22 04:32:05 PM PDT 24
Finished Jul 22 04:32:06 PM PDT 24
Peak memory 194532 kb
Host smart-9aa8c930-ba03-4be0-b99f-ba8a4bd85161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032352176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3032352176
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2681730795
Short name T806
Test name
Test status
Simulation time 35245791 ps
CPU time 0.57 seconds
Started Jul 22 04:32:14 PM PDT 24
Finished Jul 22 04:32:17 PM PDT 24
Peak memory 193908 kb
Host smart-3db9636c-7db7-4b49-bcf8-e660d6f2962a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681730795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2681730795
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4055931083
Short name T843
Test name
Test status
Simulation time 14322789 ps
CPU time 0.58 seconds
Started Jul 22 04:32:26 PM PDT 24
Finished Jul 22 04:32:27 PM PDT 24
Peak memory 193944 kb
Host smart-194fb888-435e-4d29-ad32-9a6a755a3c9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055931083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4055931083
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2949692623
Short name T786
Test name
Test status
Simulation time 41665818 ps
CPU time 0.59 seconds
Started Jul 22 04:32:23 PM PDT 24
Finished Jul 22 04:32:24 PM PDT 24
Peak memory 194616 kb
Host smart-5f2cda06-543e-4d6f-83f4-76b76859518f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949692623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2949692623
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.168673860
Short name T764
Test name
Test status
Simulation time 31722241 ps
CPU time 0.65 seconds
Started Jul 22 04:32:26 PM PDT 24
Finished Jul 22 04:32:33 PM PDT 24
Peak memory 194704 kb
Host smart-b8a3fca7-d736-46e6-9760-be48db300382
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168673860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.168673860
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1510058813
Short name T810
Test name
Test status
Simulation time 14888999 ps
CPU time 0.6 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:11 PM PDT 24
Peak memory 193968 kb
Host smart-3ae605b5-e640-4b63-bc7f-10c5f98e264b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510058813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1510058813
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3844222532
Short name T829
Test name
Test status
Simulation time 13544379 ps
CPU time 0.57 seconds
Started Jul 22 04:32:15 PM PDT 24
Finished Jul 22 04:32:18 PM PDT 24
Peak memory 193912 kb
Host smart-f13c4cbc-320c-4b17-abdc-e7dd406186f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844222532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3844222532
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1840963548
Short name T838
Test name
Test status
Simulation time 15225313 ps
CPU time 0.58 seconds
Started Jul 22 04:32:15 PM PDT 24
Finished Jul 22 04:32:18 PM PDT 24
Peak memory 193944 kb
Host smart-8aeb92a5-7401-496a-b62e-e54a2f26c1cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840963548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1840963548
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.461368477
Short name T801
Test name
Test status
Simulation time 56731446 ps
CPU time 0.58 seconds
Started Jul 22 04:32:09 PM PDT 24
Finished Jul 22 04:32:12 PM PDT 24
Peak memory 193876 kb
Host smart-a0cb5b7a-e800-4357-906e-316e68129e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461368477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.461368477
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.403894974
Short name T765
Test name
Test status
Simulation time 40659187 ps
CPU time 0.6 seconds
Started Jul 22 04:32:06 PM PDT 24
Finished Jul 22 04:32:08 PM PDT 24
Peak memory 194548 kb
Host smart-8c8e4181-753a-4cc3-9424-8fdf36e7130c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403894974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.403894974
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1565325755
Short name T91
Test name
Test status
Simulation time 113462767 ps
CPU time 0.85 seconds
Started Jul 22 04:31:59 PM PDT 24
Finished Jul 22 04:32:01 PM PDT 24
Peak memory 196324 kb
Host smart-22184907-69f2-45e5-8e6f-b1490f7536ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565325755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1565325755
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1509066390
Short name T90
Test name
Test status
Simulation time 523202564 ps
CPU time 3.39 seconds
Started Jul 22 04:32:12 PM PDT 24
Finished Jul 22 04:32:18 PM PDT 24
Peak memory 198200 kb
Host smart-b221604d-2e93-4de6-b4b6-b7e9a694c963
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509066390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1509066390
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.277127948
Short name T813
Test name
Test status
Simulation time 17992484 ps
CPU time 0.67 seconds
Started Jul 22 04:32:09 PM PDT 24
Finished Jul 22 04:32:13 PM PDT 24
Peak memory 195040 kb
Host smart-fd62cec0-5ca2-45c7-a037-400fdf2c18a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277127948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.277127948
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2037878964
Short name T720
Test name
Test status
Simulation time 60844664 ps
CPU time 0.86 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:12 PM PDT 24
Peak memory 198160 kb
Host smart-c3d75607-515a-4833-8136-e3ecd76f563e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037878964 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2037878964
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.986062937
Short name T82
Test name
Test status
Simulation time 13202194 ps
CPU time 0.56 seconds
Started Jul 22 04:31:59 PM PDT 24
Finished Jul 22 04:32:00 PM PDT 24
Peak memory 193844 kb
Host smart-1ae4e245-dfff-4c04-9abc-879f37ad83b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986062937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.986062937
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3704827428
Short name T768
Test name
Test status
Simulation time 23575881 ps
CPU time 0.6 seconds
Started Jul 22 04:32:10 PM PDT 24
Finished Jul 22 04:32:13 PM PDT 24
Peak memory 193968 kb
Host smart-5e697dcc-5226-4d56-b1a0-630a8b3d42f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704827428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3704827428
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4159627848
Short name T107
Test name
Test status
Simulation time 106981370 ps
CPU time 0.79 seconds
Started Jul 22 04:32:09 PM PDT 24
Finished Jul 22 04:32:12 PM PDT 24
Peak memory 196220 kb
Host smart-73fbbbd8-9cfd-406f-b8f0-63a31cf548b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159627848 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4159627848
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.724974312
Short name T803
Test name
Test status
Simulation time 95959994 ps
CPU time 2.11 seconds
Started Jul 22 04:31:56 PM PDT 24
Finished Jul 22 04:31:59 PM PDT 24
Peak memory 198232 kb
Host smart-fc566223-1e71-4168-ba4b-9e20c0b6675e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724974312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.724974312
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2693143633
Short name T808
Test name
Test status
Simulation time 1150483510 ps
CPU time 1 seconds
Started Jul 22 04:31:58 PM PDT 24
Finished Jul 22 04:32:00 PM PDT 24
Peak memory 198000 kb
Host smart-0d05d537-0bd0-48b0-bc06-b7059c2be40c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693143633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2693143633
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.41295910
Short name T777
Test name
Test status
Simulation time 65880839 ps
CPU time 0.55 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:11 PM PDT 24
Peak memory 193916 kb
Host smart-b94805cd-f9d1-4b57-8b36-6acf85b65075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41295910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.41295910
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3434678314
Short name T740
Test name
Test status
Simulation time 67907603 ps
CPU time 0.6 seconds
Started Jul 22 04:32:29 PM PDT 24
Finished Jul 22 04:32:31 PM PDT 24
Peak memory 194052 kb
Host smart-3e18a6be-f58e-48ff-9d4b-8ef4c78f453c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434678314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3434678314
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.19337297
Short name T796
Test name
Test status
Simulation time 38056716 ps
CPU time 0.6 seconds
Started Jul 22 04:32:22 PM PDT 24
Finished Jul 22 04:32:23 PM PDT 24
Peak memory 194020 kb
Host smart-41c8c390-456b-4067-b38c-e0431f1a3de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19337297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.19337297
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.537444208
Short name T778
Test name
Test status
Simulation time 17575140 ps
CPU time 0.63 seconds
Started Jul 22 04:32:07 PM PDT 24
Finished Jul 22 04:32:09 PM PDT 24
Peak memory 193960 kb
Host smart-a2edca64-87f7-453b-84bf-7ebc5af01da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537444208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.537444208
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2450681059
Short name T759
Test name
Test status
Simulation time 17396808 ps
CPU time 0.65 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:11 PM PDT 24
Peak memory 193960 kb
Host smart-878375a6-8498-4d7c-a46e-4a4e2d011ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450681059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2450681059
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1051085439
Short name T781
Test name
Test status
Simulation time 48295210 ps
CPU time 0.6 seconds
Started Jul 22 04:32:25 PM PDT 24
Finished Jul 22 04:32:26 PM PDT 24
Peak memory 194056 kb
Host smart-5e156d69-be62-4bfc-b09c-e9745fef17a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051085439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1051085439
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3289618623
Short name T800
Test name
Test status
Simulation time 21742470 ps
CPU time 0.57 seconds
Started Jul 22 04:32:16 PM PDT 24
Finished Jul 22 04:32:19 PM PDT 24
Peak memory 194608 kb
Host smart-853e108a-4322-48be-b3ef-d583edae7b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289618623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3289618623
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2769327703
Short name T723
Test name
Test status
Simulation time 79366100 ps
CPU time 0.62 seconds
Started Jul 22 04:32:07 PM PDT 24
Finished Jul 22 04:32:09 PM PDT 24
Peak memory 193992 kb
Host smart-b9d7c9ba-30b8-42f3-9bc5-fde8c0723da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769327703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2769327703
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3237755330
Short name T738
Test name
Test status
Simulation time 18592392 ps
CPU time 0.66 seconds
Started Jul 22 04:32:17 PM PDT 24
Finished Jul 22 04:32:19 PM PDT 24
Peak memory 193944 kb
Host smart-7f0f33b1-a1e5-4756-90f8-e52ea8ee56f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237755330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3237755330
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.566412926
Short name T741
Test name
Test status
Simulation time 41410417 ps
CPU time 0.57 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:10 PM PDT 24
Peak memory 193952 kb
Host smart-6e4831d0-f339-436a-850c-4bef5a53f763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566412926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.566412926
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2768227913
Short name T795
Test name
Test status
Simulation time 65164708 ps
CPU time 0.81 seconds
Started Jul 22 04:32:02 PM PDT 24
Finished Jul 22 04:32:03 PM PDT 24
Peak memory 198200 kb
Host smart-194c1c23-df77-4d73-bf24-11fd2393d6b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768227913 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2768227913
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2261984234
Short name T76
Test name
Test status
Simulation time 11235133 ps
CPU time 0.59 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 194436 kb
Host smart-a4a53aea-288e-4f9c-8341-f107b46d7bbe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261984234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2261984234
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3122774762
Short name T755
Test name
Test status
Simulation time 12439446 ps
CPU time 0.61 seconds
Started Jul 22 04:32:02 PM PDT 24
Finished Jul 22 04:32:04 PM PDT 24
Peak memory 194612 kb
Host smart-7b408520-4d71-4c90-8141-ed91dc9c73a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122774762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3122774762
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.908351296
Short name T773
Test name
Test status
Simulation time 60811013 ps
CPU time 0.77 seconds
Started Jul 22 04:31:59 PM PDT 24
Finished Jul 22 04:32:01 PM PDT 24
Peak memory 196476 kb
Host smart-59110c5d-7488-4e87-974b-20c60693799d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908351296 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.908351296
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.893134948
Short name T839
Test name
Test status
Simulation time 34890187 ps
CPU time 0.88 seconds
Started Jul 22 04:32:08 PM PDT 24
Finished Jul 22 04:32:10 PM PDT 24
Peak memory 198080 kb
Host smart-ff232850-8cb0-4f26-a9d6-18c8ca75ba1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893134948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.893134948
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3445242169
Short name T29
Test name
Test status
Simulation time 73550826 ps
CPU time 1.04 seconds
Started Jul 22 04:34:12 PM PDT 24
Finished Jul 22 04:34:14 PM PDT 24
Peak memory 198192 kb
Host smart-75f488bf-01d7-4866-9e37-c1b44cb28206
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445242169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3445242169
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1918726568
Short name T787
Test name
Test status
Simulation time 19603490 ps
CPU time 1.01 seconds
Started Jul 22 04:32:17 PM PDT 24
Finished Jul 22 04:32:19 PM PDT 24
Peak memory 198076 kb
Host smart-674e763c-8f90-4d2a-aec3-481f6cb12da2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918726568 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1918726568
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2692557187
Short name T84
Test name
Test status
Simulation time 47859859 ps
CPU time 0.59 seconds
Started Jul 22 04:31:56 PM PDT 24
Finished Jul 22 04:31:57 PM PDT 24
Peak memory 194824 kb
Host smart-c82b8a45-22a4-4ec6-aad8-a96f1847f932
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692557187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2692557187
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2814452296
Short name T735
Test name
Test status
Simulation time 13446941 ps
CPU time 0.62 seconds
Started Jul 22 04:32:00 PM PDT 24
Finished Jul 22 04:32:01 PM PDT 24
Peak memory 193996 kb
Host smart-c4bfbdd6-f4b5-417c-a406-06d395142c89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814452296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2814452296
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1961485499
Short name T785
Test name
Test status
Simulation time 79379177 ps
CPU time 0.8 seconds
Started Jul 22 04:32:04 PM PDT 24
Finished Jul 22 04:32:06 PM PDT 24
Peak memory 196576 kb
Host smart-27535b85-1a35-4e61-bf86-c41700c8f0c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961485499 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1961485499
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2715265099
Short name T802
Test name
Test status
Simulation time 93397458 ps
CPU time 1.85 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:06 PM PDT 24
Peak memory 198208 kb
Host smart-6fb78bf9-9773-4550-8bec-6622aee516d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715265099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2715265099
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2460980984
Short name T115
Test name
Test status
Simulation time 602469126 ps
CPU time 1.36 seconds
Started Jul 22 04:34:26 PM PDT 24
Finished Jul 22 04:34:28 PM PDT 24
Peak memory 198236 kb
Host smart-4dea9302-8b6a-4487-9e27-44409ea22c4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460980984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2460980984
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.1330511690
Short name T804
Test name
Test status
Simulation time 120966036 ps
CPU time 0.97 seconds
Started Jul 22 04:32:10 PM PDT 24
Finished Jul 22 04:32:13 PM PDT 24
Peak memory 198148 kb
Host smart-0b393ad1-d0a4-443c-9122-f6401cf37256
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330511690 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.1330511690
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1362108209
Short name T750
Test name
Test status
Simulation time 63660728 ps
CPU time 0.61 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 195556 kb
Host smart-7297bcbe-ac68-4570-baa8-d3e6d65eab45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362108209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1362108209
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3693311600
Short name T805
Test name
Test status
Simulation time 72394284 ps
CPU time 0.59 seconds
Started Jul 22 04:32:11 PM PDT 24
Finished Jul 22 04:32:14 PM PDT 24
Peak memory 194008 kb
Host smart-3895b665-9fe3-497c-bf45-9a6a31ca1334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693311600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3693311600
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3154131955
Short name T841
Test name
Test status
Simulation time 99652315 ps
CPU time 0.67 seconds
Started Jul 22 04:31:57 PM PDT 24
Finished Jul 22 04:31:58 PM PDT 24
Peak memory 195940 kb
Host smart-25ecb149-c323-416c-bbfe-1d5bc88019d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154131955 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3154131955
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1959213739
Short name T793
Test name
Test status
Simulation time 539456391 ps
CPU time 2.84 seconds
Started Jul 22 04:32:09 PM PDT 24
Finished Jul 22 04:32:15 PM PDT 24
Peak memory 198312 kb
Host smart-38e6f415-3fc4-43b9-b342-20b83d3cc84e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959213739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1959213739
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2505008848
Short name T835
Test name
Test status
Simulation time 80828449 ps
CPU time 1.07 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 198164 kb
Host smart-a29e9e00-d14d-4f4f-ab6d-3bb54240d2b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505008848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2505008848
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.738848228
Short name T814
Test name
Test status
Simulation time 208874361 ps
CPU time 0.7 seconds
Started Jul 22 04:31:59 PM PDT 24
Finished Jul 22 04:32:00 PM PDT 24
Peak memory 198000 kb
Host smart-1b451912-6d6a-4010-992a-6b87906f6a74
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738848228 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.738848228
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.672168808
Short name T743
Test name
Test status
Simulation time 14963533 ps
CPU time 0.63 seconds
Started Jul 22 04:32:03 PM PDT 24
Finished Jul 22 04:32:05 PM PDT 24
Peak memory 193416 kb
Host smart-c551fc76-0308-4de5-89b2-0618b4514f78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672168808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.672168808
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.1495221358
Short name T753
Test name
Test status
Simulation time 22484196 ps
CPU time 0.61 seconds
Started Jul 22 04:32:22 PM PDT 24
Finished Jul 22 04:32:23 PM PDT 24
Peak memory 193972 kb
Host smart-d6e90eb0-b020-45d8-9cc7-a468278a4472
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495221358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.1495221358
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.4196301780
Short name T788
Test name
Test status
Simulation time 68266528 ps
CPU time 0.78 seconds
Started Jul 22 04:31:45 PM PDT 24
Finished Jul 22 04:31:47 PM PDT 24
Peak memory 197080 kb
Host smart-581853dd-1b94-4413-8eac-33e7dd230c1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196301780 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.4196301780
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1085572991
Short name T730
Test name
Test status
Simulation time 537686480 ps
CPU time 1.4 seconds
Started Jul 22 04:31:59 PM PDT 24
Finished Jul 22 04:32:01 PM PDT 24
Peak memory 198284 kb
Host smart-c6f5d7fd-24d7-4497-b7be-9910ebbc2e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085572991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1085572991
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1095567770
Short name T41
Test name
Test status
Simulation time 308049346 ps
CPU time 1.07 seconds
Started Jul 22 04:31:55 PM PDT 24
Finished Jul 22 04:31:57 PM PDT 24
Peak memory 198204 kb
Host smart-fed9b22e-06c2-4745-a374-f11bc4bcfb66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095567770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1095567770
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1904331466
Short name T830
Test name
Test status
Simulation time 43147959 ps
CPU time 1.05 seconds
Started Jul 22 04:32:13 PM PDT 24
Finished Jul 22 04:32:17 PM PDT 24
Peak memory 198348 kb
Host smart-e128fbf1-c0ed-4e85-b859-49bbd6304144
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904331466 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1904331466
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1552165420
Short name T789
Test name
Test status
Simulation time 20176299 ps
CPU time 0.55 seconds
Started Jul 22 04:31:59 PM PDT 24
Finished Jul 22 04:32:01 PM PDT 24
Peak memory 193524 kb
Host smart-4bdf6d5b-0fb6-41d5-9a80-8c65e02b762f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552165420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1552165420
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.702992207
Short name T729
Test name
Test status
Simulation time 37264578 ps
CPU time 0.58 seconds
Started Jul 22 04:32:28 PM PDT 24
Finished Jul 22 04:32:29 PM PDT 24
Peak memory 193952 kb
Host smart-62e1ee62-cb14-4ed9-8843-c4825fbd0a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702992207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.702992207
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2359711237
Short name T102
Test name
Test status
Simulation time 114489955 ps
CPU time 0.79 seconds
Started Jul 22 04:34:13 PM PDT 24
Finished Jul 22 04:34:14 PM PDT 24
Peak memory 197128 kb
Host smart-b2228c3f-2df7-49e5-a7a6-b3f2660a77ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359711237 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2359711237
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1205428908
Short name T727
Test name
Test status
Simulation time 375416439 ps
CPU time 1.92 seconds
Started Jul 22 04:32:02 PM PDT 24
Finished Jul 22 04:32:06 PM PDT 24
Peak memory 198252 kb
Host smart-cbe0ad07-e8e9-46fd-ade3-af5344ae01da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205428908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1205428908
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2197934197
Short name T24
Test name
Test status
Simulation time 201634626 ps
CPU time 0.92 seconds
Started Jul 22 04:32:17 PM PDT 24
Finished Jul 22 04:32:20 PM PDT 24
Peak memory 197448 kb
Host smart-0010f277-7f17-4ae8-a6c6-0029674d1d0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197934197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2197934197
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4123909491
Short name T18
Test name
Test status
Simulation time 96511281 ps
CPU time 0.81 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:37:34 PM PDT 24
Peak memory 195900 kb
Host smart-88d18dc0-6152-4a5f-9d54-68d80ba79b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123909491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4123909491
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1998734934
Short name T599
Test name
Test status
Simulation time 4785538221 ps
CPU time 23.16 seconds
Started Jul 22 04:37:35 PM PDT 24
Finished Jul 22 04:37:58 PM PDT 24
Peak memory 196964 kb
Host smart-bbf4850b-5205-41ee-b63d-8592484cf2c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998734934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1998734934
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1322440863
Short name T253
Test name
Test status
Simulation time 270143058 ps
CPU time 0.72 seconds
Started Jul 22 04:37:38 PM PDT 24
Finished Jul 22 04:37:39 PM PDT 24
Peak memory 196196 kb
Host smart-ef0f96c0-150e-4dfb-abc1-8723164b54b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322440863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1322440863
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3721664240
Short name T239
Test name
Test status
Simulation time 59572097 ps
CPU time 0.81 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:37:34 PM PDT 24
Peak memory 195664 kb
Host smart-04ebbf35-72ad-49df-8358-536ace3e867a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721664240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3721664240
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3248732994
Short name T94
Test name
Test status
Simulation time 260374220 ps
CPU time 3.05 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:37:37 PM PDT 24
Peak memory 198580 kb
Host smart-8a6a22bf-fbd2-472c-8d7c-db9383957111
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248732994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3248732994
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.2539573774
Short name T538
Test name
Test status
Simulation time 76130402 ps
CPU time 0.86 seconds
Started Jul 22 04:37:34 PM PDT 24
Finished Jul 22 04:37:35 PM PDT 24
Peak memory 195480 kb
Host smart-e043a2ef-89af-4008-a953-7e4627ce8bad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539573774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
2539573774
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4124383785
Short name T618
Test name
Test status
Simulation time 46531876 ps
CPU time 0.92 seconds
Started Jul 22 04:37:32 PM PDT 24
Finished Jul 22 04:37:34 PM PDT 24
Peak memory 196420 kb
Host smart-06e41f2a-9aeb-40b4-a1e2-cf3c56cec1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124383785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4124383785
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.288000107
Short name T667
Test name
Test status
Simulation time 281216599 ps
CPU time 0.81 seconds
Started Jul 22 04:37:35 PM PDT 24
Finished Jul 22 04:37:37 PM PDT 24
Peak memory 195764 kb
Host smart-e72dc19a-8f71-40f5-a211-6694f0baca27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288000107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.288000107
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2028132882
Short name T176
Test name
Test status
Simulation time 332784302 ps
CPU time 5.86 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:37:39 PM PDT 24
Peak memory 198192 kb
Host smart-bf261492-4476-48a6-a7f2-0b827b422662
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028132882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2028132882
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1113514313
Short name T308
Test name
Test status
Simulation time 318001671 ps
CPU time 1.42 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:37:35 PM PDT 24
Peak memory 195948 kb
Host smart-169920dc-230e-4709-b02a-33f500b3ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113514313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1113514313
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.64140960
Short name T323
Test name
Test status
Simulation time 86699159 ps
CPU time 1.19 seconds
Started Jul 22 04:37:35 PM PDT 24
Finished Jul 22 04:37:37 PM PDT 24
Peak memory 197300 kb
Host smart-29892770-cfce-4408-a8b1-9616f4e966cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64140960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.64140960
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2666662175
Short name T181
Test name
Test status
Simulation time 7557301812 ps
CPU time 204.3 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:40:58 PM PDT 24
Peak memory 198524 kb
Host smart-8a45915c-c72b-48b1-ad37-2ceae8e7456d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666662175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2666662175
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3127458067
Short name T552
Test name
Test status
Simulation time 42499126 ps
CPU time 0.59 seconds
Started Jul 22 04:37:43 PM PDT 24
Finished Jul 22 04:37:44 PM PDT 24
Peak memory 194316 kb
Host smart-d4d24264-fe89-451d-b9e6-5ace8f4c9ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127458067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3127458067
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2825300147
Short name T607
Test name
Test status
Simulation time 81202865 ps
CPU time 0.92 seconds
Started Jul 22 04:37:42 PM PDT 24
Finished Jul 22 04:37:44 PM PDT 24
Peak memory 196880 kb
Host smart-1d4644da-ba06-45df-b2c1-d2d4bfdb333a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825300147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2825300147
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.423923182
Short name T512
Test name
Test status
Simulation time 306063025 ps
CPU time 15.12 seconds
Started Jul 22 04:37:42 PM PDT 24
Finished Jul 22 04:37:58 PM PDT 24
Peak memory 197408 kb
Host smart-b56a44ef-e899-43c0-8689-fa33a29146a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423923182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.423923182
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1585520209
Short name T562
Test name
Test status
Simulation time 45932270 ps
CPU time 0.64 seconds
Started Jul 22 04:40:51 PM PDT 24
Finished Jul 22 04:40:53 PM PDT 24
Peak memory 194896 kb
Host smart-af0be8b9-7e89-4e37-87a8-00e1e74a1672
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585520209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1585520209
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.296350009
Short name T200
Test name
Test status
Simulation time 42688413 ps
CPU time 0.9 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:43 PM PDT 24
Peak memory 197936 kb
Host smart-9ad50ec7-56b1-48e1-87b0-04763c0e8ceb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296350009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.296350009
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.333064455
Short name T452
Test name
Test status
Simulation time 178837638 ps
CPU time 4.17 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:46 PM PDT 24
Peak memory 198404 kb
Host smart-cda51fa8-0ca1-45a2-8f96-50c69361de3a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333064455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.333064455
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3931513142
Short name T652
Test name
Test status
Simulation time 559857124 ps
CPU time 3.1 seconds
Started Jul 22 04:37:42 PM PDT 24
Finished Jul 22 04:37:46 PM PDT 24
Peak memory 198444 kb
Host smart-87ffd820-3868-4cfd-b71d-fa19c251bc33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931513142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3931513142
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3613959734
Short name T477
Test name
Test status
Simulation time 139274566 ps
CPU time 1.23 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:37:35 PM PDT 24
Peak memory 197496 kb
Host smart-95e66181-7589-4194-8573-777f5e2acb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613959734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3613959734
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2311947139
Short name T584
Test name
Test status
Simulation time 48949714 ps
CPU time 1.2 seconds
Started Jul 22 04:37:42 PM PDT 24
Finished Jul 22 04:37:44 PM PDT 24
Peak memory 196388 kb
Host smart-acce708c-4b9c-42e4-b2ab-258f939d814f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311947139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2311947139
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1880404052
Short name T324
Test name
Test status
Simulation time 1860084627 ps
CPU time 5.74 seconds
Started Jul 22 04:40:51 PM PDT 24
Finished Jul 22 04:40:57 PM PDT 24
Peak memory 198372 kb
Host smart-7836c1fd-4d88-4d68-af5b-cc1d6e40c886
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880404052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1880404052
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.180147531
Short name T43
Test name
Test status
Simulation time 89947925 ps
CPU time 1.01 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:43 PM PDT 24
Peak memory 215480 kb
Host smart-fc23e1ff-178a-4ad1-8de4-0b008d04a875
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180147531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.180147531
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3141277759
Short name T675
Test name
Test status
Simulation time 91023414 ps
CPU time 1.53 seconds
Started Jul 22 04:37:35 PM PDT 24
Finished Jul 22 04:37:37 PM PDT 24
Peak memory 197196 kb
Host smart-59967e9e-2cb3-4064-be93-9a6e068335f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141277759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3141277759
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1299129607
Short name T621
Test name
Test status
Simulation time 293150550 ps
CPU time 1.12 seconds
Started Jul 22 04:38:24 PM PDT 24
Finished Jul 22 04:38:25 PM PDT 24
Peak memory 195880 kb
Host smart-972eaece-254e-4303-8afc-453db500c4c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299129607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1299129607
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3458799950
Short name T464
Test name
Test status
Simulation time 16476952933 ps
CPU time 222.85 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:41:25 PM PDT 24
Peak memory 198456 kb
Host smart-e3f4ce34-f38f-4e66-8254-eeb71cbe2c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458799950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3458799950
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1529571705
Short name T660
Test name
Test status
Simulation time 13683731 ps
CPU time 0.58 seconds
Started Jul 22 04:38:56 PM PDT 24
Finished Jul 22 04:38:57 PM PDT 24
Peak memory 195024 kb
Host smart-f41baebd-3b95-47ef-b7d1-e3d5743b3046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529571705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1529571705
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2414179649
Short name T401
Test name
Test status
Simulation time 40579713 ps
CPU time 0.65 seconds
Started Jul 22 04:38:28 PM PDT 24
Finished Jul 22 04:38:29 PM PDT 24
Peak memory 195168 kb
Host smart-24e0e505-0f7a-4967-96d1-f0a783ca3fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414179649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2414179649
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2036811534
Short name T444
Test name
Test status
Simulation time 207596374 ps
CPU time 6.45 seconds
Started Jul 22 04:38:37 PM PDT 24
Finished Jul 22 04:38:44 PM PDT 24
Peak memory 198440 kb
Host smart-b0657fd2-fb22-403c-8600-03acd4339bdb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036811534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2036811534
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3312217072
Short name T69
Test name
Test status
Simulation time 54957227 ps
CPU time 0.86 seconds
Started Jul 22 04:38:38 PM PDT 24
Finished Jul 22 04:38:40 PM PDT 24
Peak memory 196400 kb
Host smart-e9544e10-edfa-48f4-baa6-8457653624c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312217072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3312217072
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2296659698
Short name T232
Test name
Test status
Simulation time 256875975 ps
CPU time 1.01 seconds
Started Jul 22 04:38:28 PM PDT 24
Finished Jul 22 04:38:30 PM PDT 24
Peak memory 196572 kb
Host smart-8f3bd5d5-e87b-40c3-8d44-98ed8cad7aac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296659698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2296659698
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.188682604
Short name T447
Test name
Test status
Simulation time 260045110 ps
CPU time 2.93 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:30 PM PDT 24
Peak memory 196912 kb
Host smart-552799c6-8a83-41bd-80ee-2e5044ebe4b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188682604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.gpio_intr_with_filter_rand_intr_event.188682604
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2703642556
Short name T228
Test name
Test status
Simulation time 35425222 ps
CPU time 1 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:29 PM PDT 24
Peak memory 195776 kb
Host smart-be5e5b52-06ad-4660-a090-c07dd8a96afc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703642556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2703642556
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.4082443958
Short name T154
Test name
Test status
Simulation time 54853631 ps
CPU time 0.82 seconds
Started Jul 22 04:38:29 PM PDT 24
Finished Jul 22 04:38:30 PM PDT 24
Peak memory 195872 kb
Host smart-c707e9d6-b0a7-4144-bce2-24aa3af8b959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082443958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.4082443958
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.294725578
Short name T131
Test name
Test status
Simulation time 26323008 ps
CPU time 1 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:29 PM PDT 24
Peak memory 197280 kb
Host smart-9279000a-6b15-47eb-a6f9-07b474fae062
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294725578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.294725578
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.977904439
Short name T340
Test name
Test status
Simulation time 1227138022 ps
CPU time 4.66 seconds
Started Jul 22 04:38:38 PM PDT 24
Finished Jul 22 04:38:43 PM PDT 24
Peak memory 198380 kb
Host smart-d31eb18e-c708-4d2e-8b4e-4edc000f07c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977904439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.977904439
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.999041765
Short name T592
Test name
Test status
Simulation time 71510041 ps
CPU time 0.85 seconds
Started Jul 22 04:38:28 PM PDT 24
Finished Jul 22 04:38:30 PM PDT 24
Peak memory 195752 kb
Host smart-0b1d1295-e5c6-4c42-b18e-f2844ec06017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999041765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.999041765
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1825536857
Short name T488
Test name
Test status
Simulation time 70400072 ps
CPU time 0.93 seconds
Started Jul 22 04:38:30 PM PDT 24
Finished Jul 22 04:38:32 PM PDT 24
Peak memory 195868 kb
Host smart-3b263712-42e3-4a9e-af9a-db26dda87951
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825536857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1825536857
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2852667978
Short name T422
Test name
Test status
Simulation time 7091950557 ps
CPU time 195.94 seconds
Started Jul 22 04:38:57 PM PDT 24
Finished Jul 22 04:42:13 PM PDT 24
Peak memory 198508 kb
Host smart-1f69e0f5-eacb-4192-bfce-6aa6f97a8200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852667978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2852667978
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.280062205
Short name T33
Test name
Test status
Simulation time 47120064 ps
CPU time 0.55 seconds
Started Jul 22 04:38:49 PM PDT 24
Finished Jul 22 04:38:50 PM PDT 24
Peak memory 194388 kb
Host smart-c95774b1-0c7f-41ac-a187-89f45e63d575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280062205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.280062205
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3067120667
Short name T110
Test name
Test status
Simulation time 78968913 ps
CPU time 0.73 seconds
Started Jul 22 04:38:37 PM PDT 24
Finished Jul 22 04:38:38 PM PDT 24
Peak memory 196328 kb
Host smart-077e697d-094a-4970-9354-7dd9eac7455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067120667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3067120667
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1313736515
Short name T12
Test name
Test status
Simulation time 535863716 ps
CPU time 18.94 seconds
Started Jul 22 04:38:38 PM PDT 24
Finished Jul 22 04:38:57 PM PDT 24
Peak memory 197152 kb
Host smart-3069721b-0f3e-4ec5-b4db-e6a5496e8e1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313736515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1313736515
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.727840480
Short name T146
Test name
Test status
Simulation time 279132099 ps
CPU time 0.71 seconds
Started Jul 22 04:38:52 PM PDT 24
Finished Jul 22 04:38:53 PM PDT 24
Peak memory 195056 kb
Host smart-95922e62-8e1d-4ff4-ad5e-21bedf2eac32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727840480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.727840480
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3898260054
Short name T114
Test name
Test status
Simulation time 72191268 ps
CPU time 0.74 seconds
Started Jul 22 04:38:36 PM PDT 24
Finished Jul 22 04:38:37 PM PDT 24
Peak memory 194680 kb
Host smart-f3897078-9994-4720-a389-aa2f0bcda70f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898260054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3898260054
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.960144510
Short name T285
Test name
Test status
Simulation time 168730014 ps
CPU time 1.9 seconds
Started Jul 22 04:38:36 PM PDT 24
Finished Jul 22 04:38:38 PM PDT 24
Peak memory 198564 kb
Host smart-7b92dd62-ca61-4846-ad8c-117d102d5c55
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960144510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.960144510
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2786532133
Short name T546
Test name
Test status
Simulation time 77324514 ps
CPU time 1.82 seconds
Started Jul 22 04:38:37 PM PDT 24
Finished Jul 22 04:38:39 PM PDT 24
Peak memory 196572 kb
Host smart-a8d8c701-9b84-4c14-accd-6f6b3c0de168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786532133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2786532133
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.3673745881
Short name T326
Test name
Test status
Simulation time 130248830 ps
CPU time 1.24 seconds
Started Jul 22 04:38:35 PM PDT 24
Finished Jul 22 04:38:37 PM PDT 24
Peak memory 196276 kb
Host smart-154b9d0c-42f3-4306-b99f-cb80d5e56044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673745881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.3673745881
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.123100535
Short name T384
Test name
Test status
Simulation time 216971641 ps
CPU time 1.31 seconds
Started Jul 22 04:38:36 PM PDT 24
Finished Jul 22 04:38:38 PM PDT 24
Peak memory 196948 kb
Host smart-d3704abc-d435-4522-b5b8-3739e26b1f5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123100535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.123100535
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.622736719
Short name T602
Test name
Test status
Simulation time 54731776 ps
CPU time 2.67 seconds
Started Jul 22 04:38:50 PM PDT 24
Finished Jul 22 04:38:53 PM PDT 24
Peak memory 198548 kb
Host smart-97589803-a0d2-4b7d-a03f-270b914d7250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622736719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.622736719
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3422544985
Short name T550
Test name
Test status
Simulation time 1178873269 ps
CPU time 1.29 seconds
Started Jul 22 04:38:36 PM PDT 24
Finished Jul 22 04:38:38 PM PDT 24
Peak memory 196116 kb
Host smart-9367b933-85db-4e64-bc4c-dabff193c3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422544985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3422544985
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.4098546846
Short name T367
Test name
Test status
Simulation time 90460509 ps
CPU time 1.14 seconds
Started Jul 22 04:38:37 PM PDT 24
Finished Jul 22 04:38:38 PM PDT 24
Peak memory 196920 kb
Host smart-b8197b3f-9607-4361-8d71-44d172dd47fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098546846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.4098546846
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1161115366
Short name T525
Test name
Test status
Simulation time 12058955940 ps
CPU time 149.09 seconds
Started Jul 22 04:38:49 PM PDT 24
Finished Jul 22 04:41:19 PM PDT 24
Peak memory 198584 kb
Host smart-5ca84671-ef9d-4c39-b517-eda7615f6c29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161115366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1161115366
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3144167206
Short name T715
Test name
Test status
Simulation time 74336705 ps
CPU time 0.57 seconds
Started Jul 22 04:38:50 PM PDT 24
Finished Jul 22 04:38:51 PM PDT 24
Peak memory 194504 kb
Host smart-a0ff1433-4efd-48d8-9b62-60ec752fc202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144167206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3144167206
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3629672057
Short name T172
Test name
Test status
Simulation time 19342543 ps
CPU time 0.68 seconds
Started Jul 22 04:38:52 PM PDT 24
Finished Jul 22 04:38:54 PM PDT 24
Peak memory 194500 kb
Host smart-8930dde6-a643-4487-b78e-cb3375f905cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629672057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3629672057
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2249857324
Short name T138
Test name
Test status
Simulation time 308875781 ps
CPU time 16.38 seconds
Started Jul 22 04:39:35 PM PDT 24
Finished Jul 22 04:39:52 PM PDT 24
Peak memory 195988 kb
Host smart-f2b9ee5e-c3c6-4931-805d-1f521ff04448
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249857324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2249857324
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2407382633
Short name T428
Test name
Test status
Simulation time 64301457 ps
CPU time 0.96 seconds
Started Jul 22 04:38:49 PM PDT 24
Finished Jul 22 04:38:51 PM PDT 24
Peak memory 197616 kb
Host smart-0bc312bc-f4bd-42da-9346-e02cf7a49487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407382633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2407382633
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2186323127
Short name T575
Test name
Test status
Simulation time 42840167 ps
CPU time 1.22 seconds
Started Jul 22 04:38:52 PM PDT 24
Finished Jul 22 04:38:53 PM PDT 24
Peak memory 197200 kb
Host smart-88e37b39-83db-4281-8193-4b7f46d25302
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186323127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2186323127
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3760330055
Short name T272
Test name
Test status
Simulation time 284804222 ps
CPU time 1.83 seconds
Started Jul 22 04:38:52 PM PDT 24
Finished Jul 22 04:38:55 PM PDT 24
Peak memory 198552 kb
Host smart-cd0d2619-694d-4302-82e0-9b4a76ae3f79
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760330055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3760330055
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1026163148
Short name T349
Test name
Test status
Simulation time 98895302 ps
CPU time 2.4 seconds
Started Jul 22 04:38:53 PM PDT 24
Finished Jul 22 04:38:55 PM PDT 24
Peak memory 197540 kb
Host smart-eac45a45-b420-4c23-bda8-741b90467cda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026163148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1026163148
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2311166206
Short name T163
Test name
Test status
Simulation time 24877230 ps
CPU time 0.73 seconds
Started Jul 22 04:38:48 PM PDT 24
Finished Jul 22 04:38:49 PM PDT 24
Peak memory 196500 kb
Host smart-f1a3f71d-9769-4cdc-9d5a-7a1a77b5fd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311166206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2311166206
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1696793708
Short name T666
Test name
Test status
Simulation time 62386393 ps
CPU time 1.27 seconds
Started Jul 22 04:39:35 PM PDT 24
Finished Jul 22 04:39:37 PM PDT 24
Peak memory 196516 kb
Host smart-b6b47376-7b28-4428-a32b-3f16f61f3fc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696793708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1696793708
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3282847030
Short name T5
Test name
Test status
Simulation time 854004199 ps
CPU time 4.79 seconds
Started Jul 22 04:38:48 PM PDT 24
Finished Jul 22 04:38:53 PM PDT 24
Peak memory 198192 kb
Host smart-522e6c8a-9275-481b-9e83-14d0e5092d3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282847030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3282847030
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.4248932849
Short name T406
Test name
Test status
Simulation time 37058579 ps
CPU time 1.23 seconds
Started Jul 22 04:38:50 PM PDT 24
Finished Jul 22 04:38:51 PM PDT 24
Peak memory 198428 kb
Host smart-90bbddca-3cc1-456c-a722-972c206da9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248932849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.4248932849
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2688248785
Short name T287
Test name
Test status
Simulation time 131705606 ps
CPU time 1.08 seconds
Started Jul 22 04:39:09 PM PDT 24
Finished Jul 22 04:39:10 PM PDT 24
Peak memory 196016 kb
Host smart-26f9a3af-4b84-4d7e-a1c5-683f750d7838
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688248785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2688248785
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1268389256
Short name T712
Test name
Test status
Simulation time 48520703226 ps
CPU time 156.26 seconds
Started Jul 22 04:38:51 PM PDT 24
Finished Jul 22 04:41:28 PM PDT 24
Peak memory 198476 kb
Host smart-052d1b54-4742-43bc-8864-6b9270df0265
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268389256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1268389256
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1697453033
Short name T480
Test name
Test status
Simulation time 142963628029 ps
CPU time 785.97 seconds
Started Jul 22 04:38:52 PM PDT 24
Finished Jul 22 04:51:59 PM PDT 24
Peak memory 198748 kb
Host smart-d48ffb1e-a789-4430-a31e-14cb811db8d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1697453033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1697453033
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1598563880
Short name T288
Test name
Test status
Simulation time 24697799 ps
CPU time 0.6 seconds
Started Jul 22 04:39:02 PM PDT 24
Finished Jul 22 04:39:03 PM PDT 24
Peak memory 194340 kb
Host smart-df31db6d-a83a-47c5-a9cd-8dc31dec4b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598563880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1598563880
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1906587821
Short name T423
Test name
Test status
Simulation time 92506509 ps
CPU time 0.92 seconds
Started Jul 22 04:38:59 PM PDT 24
Finished Jul 22 04:39:01 PM PDT 24
Peak memory 196864 kb
Host smart-a04bcb5b-8c1a-4c04-b90e-6b3bf20d3d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906587821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1906587821
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1797171901
Short name T451
Test name
Test status
Simulation time 280487165 ps
CPU time 14.34 seconds
Started Jul 22 04:39:39 PM PDT 24
Finished Jul 22 04:39:54 PM PDT 24
Peak memory 198448 kb
Host smart-306c4140-ef5f-45d3-8d06-d1edcfd4fe96
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797171901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1797171901
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3566155274
Short name T695
Test name
Test status
Simulation time 64019167 ps
CPU time 1.03 seconds
Started Jul 22 04:39:02 PM PDT 24
Finished Jul 22 04:39:03 PM PDT 24
Peak memory 198316 kb
Host smart-45237201-647a-4d94-99a1-3fc1d06abd73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566155274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3566155274
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1099112290
Short name T678
Test name
Test status
Simulation time 29466994 ps
CPU time 0.74 seconds
Started Jul 22 04:38:58 PM PDT 24
Finished Jul 22 04:39:00 PM PDT 24
Peak memory 194796 kb
Host smart-c80f4fa9-385e-4f0b-8f9d-dd230c5469dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099112290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1099112290
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3569998080
Short name T649
Test name
Test status
Simulation time 267050658 ps
CPU time 2.7 seconds
Started Jul 22 04:39:03 PM PDT 24
Finished Jul 22 04:39:06 PM PDT 24
Peak memory 198588 kb
Host smart-830f3999-a8f9-419c-88cc-c923c3cc77f9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569998080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3569998080
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2104435592
Short name T624
Test name
Test status
Simulation time 63463960 ps
CPU time 1.98 seconds
Started Jul 22 04:39:02 PM PDT 24
Finished Jul 22 04:39:05 PM PDT 24
Peak memory 197476 kb
Host smart-02169189-c180-40cf-bc18-367853c7ff57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104435592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2104435592
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1461290101
Short name T119
Test name
Test status
Simulation time 46386980 ps
CPU time 0.97 seconds
Started Jul 22 04:39:01 PM PDT 24
Finished Jul 22 04:39:02 PM PDT 24
Peak memory 197116 kb
Host smart-dc049263-0f7d-4a54-9be7-3f3901d01ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461290101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1461290101
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2148713646
Short name T48
Test name
Test status
Simulation time 256258145 ps
CPU time 1.55 seconds
Started Jul 22 04:39:01 PM PDT 24
Finished Jul 22 04:39:03 PM PDT 24
Peak memory 198448 kb
Host smart-1ccf8b44-907d-48b1-87be-2cd2825b0c6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148713646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2148713646
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2639337989
Short name T222
Test name
Test status
Simulation time 674231852 ps
CPU time 5.3 seconds
Started Jul 22 04:39:01 PM PDT 24
Finished Jul 22 04:39:07 PM PDT 24
Peak memory 198388 kb
Host smart-5b24cfa6-183d-4b56-adaf-a27d770ed848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639337989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2639337989
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1073852832
Short name T634
Test name
Test status
Simulation time 216335584 ps
CPU time 1.28 seconds
Started Jul 22 04:38:49 PM PDT 24
Finished Jul 22 04:38:50 PM PDT 24
Peak memory 196256 kb
Host smart-562b3ac6-80a5-4b22-813e-ae380a7c5985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073852832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1073852832
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.292709453
Short name T627
Test name
Test status
Simulation time 80138786 ps
CPU time 1.06 seconds
Started Jul 22 04:39:09 PM PDT 24
Finished Jul 22 04:39:10 PM PDT 24
Peak memory 196120 kb
Host smart-aa97298a-e2db-49f8-afda-f2f49a8103f7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292709453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.292709453
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1341957607
Short name T177
Test name
Test status
Simulation time 4167685253 ps
CPU time 122.41 seconds
Started Jul 22 04:38:58 PM PDT 24
Finished Jul 22 04:41:01 PM PDT 24
Peak memory 198512 kb
Host smart-3dc7e2b1-1ba8-4933-a47f-0f3da2536dcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341957607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1341957607
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.74796783
Short name T56
Test name
Test status
Simulation time 175249808711 ps
CPU time 1320.71 seconds
Started Jul 22 04:38:59 PM PDT 24
Finished Jul 22 05:01:00 PM PDT 24
Peak memory 198584 kb
Host smart-7be1a3c1-5dd3-43e5-bbde-b5b79d473f59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=74796783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.74796783
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.68394478
Short name T598
Test name
Test status
Simulation time 33711843 ps
CPU time 0.56 seconds
Started Jul 22 04:39:03 PM PDT 24
Finished Jul 22 04:39:04 PM PDT 24
Peak memory 194384 kb
Host smart-0a3ea1ca-eec3-4345-ad7f-2bb40fb2e075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68394478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.68394478
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2890165072
Short name T594
Test name
Test status
Simulation time 89181077 ps
CPU time 0.83 seconds
Started Jul 22 04:38:57 PM PDT 24
Finished Jul 22 04:38:58 PM PDT 24
Peak memory 196384 kb
Host smart-cf539875-01e1-41ae-affd-851b7d367178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890165072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2890165072
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2965399869
Short name T470
Test name
Test status
Simulation time 405107445 ps
CPU time 12.54 seconds
Started Jul 22 04:39:39 PM PDT 24
Finished Jul 22 04:39:52 PM PDT 24
Peak memory 198444 kb
Host smart-3619e07d-c801-4fc4-9f26-6a3587d936c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965399869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2965399869
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2393219966
Short name T438
Test name
Test status
Simulation time 41349351 ps
CPU time 0.73 seconds
Started Jul 22 04:43:21 PM PDT 24
Finished Jul 22 04:43:22 PM PDT 24
Peak memory 195836 kb
Host smart-88e794b3-ac7d-45a7-9404-3ae3f7e0a108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393219966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2393219966
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2571754688
Short name T145
Test name
Test status
Simulation time 135755345 ps
CPU time 0.78 seconds
Started Jul 22 04:38:57 PM PDT 24
Finished Jul 22 04:38:59 PM PDT 24
Peak memory 196472 kb
Host smart-4e95c60f-359d-4151-af41-750369530e20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571754688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2571754688
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3816084123
Short name T365
Test name
Test status
Simulation time 36077622 ps
CPU time 1.67 seconds
Started Jul 22 04:39:00 PM PDT 24
Finished Jul 22 04:39:02 PM PDT 24
Peak memory 196888 kb
Host smart-acb0563a-eb47-439d-8ae7-65ee9a00f6d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816084123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3816084123
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.466309927
Short name T283
Test name
Test status
Simulation time 1668147565 ps
CPU time 4.22 seconds
Started Jul 22 04:38:59 PM PDT 24
Finished Jul 22 04:39:04 PM PDT 24
Peak memory 196196 kb
Host smart-00184ae6-7590-4b15-a0f2-74dbd677df31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466309927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
466309927
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3809612351
Short name T60
Test name
Test status
Simulation time 29680028 ps
CPU time 0.75 seconds
Started Jul 22 04:38:59 PM PDT 24
Finished Jul 22 04:39:00 PM PDT 24
Peak memory 195744 kb
Host smart-43d06925-3235-40d3-bf68-c49a3e7a0842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809612351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3809612351
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3622763391
Short name T191
Test name
Test status
Simulation time 231750978 ps
CPU time 0.74 seconds
Started Jul 22 04:39:00 PM PDT 24
Finished Jul 22 04:39:01 PM PDT 24
Peak memory 194808 kb
Host smart-a3054495-4c10-485f-9465-004fc9ed2a44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622763391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3622763391
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1960790640
Short name T158
Test name
Test status
Simulation time 514348679 ps
CPU time 4.56 seconds
Started Jul 22 04:38:58 PM PDT 24
Finished Jul 22 04:39:03 PM PDT 24
Peak memory 198428 kb
Host smart-188d4e61-8d1c-4009-8459-12826cf1322c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960790640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1960790640
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1764461615
Short name T355
Test name
Test status
Simulation time 171502248 ps
CPU time 1.31 seconds
Started Jul 22 04:38:58 PM PDT 24
Finished Jul 22 04:39:00 PM PDT 24
Peak memory 196732 kb
Host smart-14d09381-80f8-447a-a2d3-246bde55b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764461615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1764461615
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1724181700
Short name T264
Test name
Test status
Simulation time 94352281 ps
CPU time 1.7 seconds
Started Jul 22 04:39:01 PM PDT 24
Finished Jul 22 04:39:03 PM PDT 24
Peak memory 198444 kb
Host smart-a9202cab-7151-43a7-9d6d-ef990658b079
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724181700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1724181700
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.944057042
Short name T664
Test name
Test status
Simulation time 20547882659 ps
CPU time 122.99 seconds
Started Jul 22 04:38:58 PM PDT 24
Finished Jul 22 04:41:02 PM PDT 24
Peak memory 198480 kb
Host smart-07e8a9cf-7569-4e17-b7f2-17c3ded53598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944057042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.944057042
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1944286841
Short name T53
Test name
Test status
Simulation time 63986594297 ps
CPU time 1766.7 seconds
Started Jul 22 04:38:59 PM PDT 24
Finished Jul 22 05:08:27 PM PDT 24
Peak memory 198656 kb
Host smart-8847966f-cb59-49d2-b5ec-8524adcd57fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1944286841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1944286841
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1119504473
Short name T291
Test name
Test status
Simulation time 14453649 ps
CPU time 0.59 seconds
Started Jul 22 04:39:48 PM PDT 24
Finished Jul 22 04:39:49 PM PDT 24
Peak memory 194492 kb
Host smart-4e1f957d-579a-4245-9f4c-6f9130c08800
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119504473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1119504473
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2635095531
Short name T471
Test name
Test status
Simulation time 71279665 ps
CPU time 0.76 seconds
Started Jul 22 04:38:58 PM PDT 24
Finished Jul 22 04:38:59 PM PDT 24
Peak memory 194564 kb
Host smart-fdbd8117-ec7b-49a4-a88e-ceaf5fd360c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635095531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2635095531
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2578426580
Short name T320
Test name
Test status
Simulation time 1890044447 ps
CPU time 22 seconds
Started Jul 22 04:43:21 PM PDT 24
Finished Jul 22 04:43:44 PM PDT 24
Peak memory 198372 kb
Host smart-2021b531-df60-42ff-b782-dff8e4b71cfe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578426580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2578426580
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2679968298
Short name T216
Test name
Test status
Simulation time 70242114 ps
CPU time 1.01 seconds
Started Jul 22 04:39:06 PM PDT 24
Finished Jul 22 04:39:08 PM PDT 24
Peak memory 198288 kb
Host smart-60f81bd0-1421-43ae-a30d-b2d422e4617c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679968298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2679968298
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4137110208
Short name T410
Test name
Test status
Simulation time 63990457 ps
CPU time 1.07 seconds
Started Jul 22 04:39:02 PM PDT 24
Finished Jul 22 04:39:04 PM PDT 24
Peak memory 197056 kb
Host smart-a379c099-11d1-4132-9b2c-1339f8630d3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137110208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4137110208
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2662371482
Short name T195
Test name
Test status
Simulation time 331998282 ps
CPU time 3.63 seconds
Started Jul 22 04:38:59 PM PDT 24
Finished Jul 22 04:39:03 PM PDT 24
Peak memory 198496 kb
Host smart-f58cc250-a071-4541-bf4f-5aac3de648c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662371482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2662371482
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.802974526
Short name T100
Test name
Test status
Simulation time 423094085 ps
CPU time 2.39 seconds
Started Jul 22 04:38:57 PM PDT 24
Finished Jul 22 04:39:00 PM PDT 24
Peak memory 197232 kb
Host smart-5cc1699c-b3d0-4732-8e19-a53cca7aeb82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802974526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
802974526
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3703587514
Short name T111
Test name
Test status
Simulation time 51666077 ps
CPU time 1.03 seconds
Started Jul 22 04:38:59 PM PDT 24
Finished Jul 22 04:39:00 PM PDT 24
Peak memory 197052 kb
Host smart-1ce1ece3-e92f-4ccc-aec2-445e56e89934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703587514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3703587514
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2232307858
Short name T582
Test name
Test status
Simulation time 98265368 ps
CPU time 1.11 seconds
Started Jul 22 04:38:58 PM PDT 24
Finished Jul 22 04:39:00 PM PDT 24
Peak memory 196512 kb
Host smart-ab01ffcd-d721-48ed-98f8-b01605e63da8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232307858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2232307858
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1548311838
Short name T8
Test name
Test status
Simulation time 347971536 ps
CPU time 4.1 seconds
Started Jul 22 04:39:03 PM PDT 24
Finished Jul 22 04:39:07 PM PDT 24
Peak memory 198444 kb
Host smart-215ad147-3fa4-481e-802c-1a160b576ae7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548311838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1548311838
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3259504336
Short name T298
Test name
Test status
Simulation time 342144972 ps
CPU time 1.38 seconds
Started Jul 22 04:39:01 PM PDT 24
Finished Jul 22 04:39:03 PM PDT 24
Peak memory 197144 kb
Host smart-a3abe68c-a382-4a1b-9240-061277da6864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259504336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3259504336
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1416026008
Short name T560
Test name
Test status
Simulation time 62398982 ps
CPU time 1.15 seconds
Started Jul 22 04:38:58 PM PDT 24
Finished Jul 22 04:38:59 PM PDT 24
Peak memory 195932 kb
Host smart-a0f91f53-778f-4570-a863-9bb7ab30e6b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416026008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1416026008
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1370524051
Short name T572
Test name
Test status
Simulation time 16295401209 ps
CPU time 207.12 seconds
Started Jul 22 04:44:21 PM PDT 24
Finished Jul 22 04:47:49 PM PDT 24
Peak memory 198488 kb
Host smart-fae29979-7fce-4712-96c1-890e07328667
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370524051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1370524051
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2665440489
Short name T350
Test name
Test status
Simulation time 28935105 ps
CPU time 0.54 seconds
Started Jul 22 04:39:17 PM PDT 24
Finished Jul 22 04:39:18 PM PDT 24
Peak memory 194328 kb
Host smart-be7cf2be-ef2e-48eb-8ca4-20dc0c2ea173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665440489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2665440489
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3443973383
Short name T262
Test name
Test status
Simulation time 16901808 ps
CPU time 0.65 seconds
Started Jul 22 04:39:06 PM PDT 24
Finished Jul 22 04:39:06 PM PDT 24
Peak memory 195232 kb
Host smart-c2c85d54-3973-4e23-8294-0c4cc60d7a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443973383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3443973383
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2548608226
Short name T370
Test name
Test status
Simulation time 507181523 ps
CPU time 9.94 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:30 PM PDT 24
Peak memory 197360 kb
Host smart-b2d377bc-8062-43f2-bdf6-1d81d53c0792
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548608226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2548608226
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.822350785
Short name T249
Test name
Test status
Simulation time 117734457 ps
CPU time 0.88 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 196416 kb
Host smart-889469d1-52b8-403b-bfaf-89b55b4edb5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822350785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.822350785
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.961357360
Short name T271
Test name
Test status
Simulation time 44499678 ps
CPU time 0.96 seconds
Started Jul 22 04:39:47 PM PDT 24
Finished Jul 22 04:39:48 PM PDT 24
Peak memory 196384 kb
Host smart-e72a0c46-7ab4-4aed-a900-2f175c374fb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961357360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.961357360
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3993505868
Short name T692
Test name
Test status
Simulation time 258590210 ps
CPU time 2.53 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:22 PM PDT 24
Peak memory 197776 kb
Host smart-9f2d0c5e-2b4c-452d-a014-402c445e2db0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993505868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3993505868
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.149798584
Short name T335
Test name
Test status
Simulation time 1279018631 ps
CPU time 2.83 seconds
Started Jul 22 04:39:05 PM PDT 24
Finished Jul 22 04:39:08 PM PDT 24
Peak memory 196304 kb
Host smart-f4294cd3-5b6d-4572-96c6-9afb16e8b971
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149798584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
149798584
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2247000234
Short name T386
Test name
Test status
Simulation time 32659500 ps
CPU time 1.31 seconds
Started Jul 22 04:39:07 PM PDT 24
Finished Jul 22 04:39:08 PM PDT 24
Peak memory 197540 kb
Host smart-b2eb4934-be9e-427e-ac18-6b491c8613e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247000234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2247000234
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.198490428
Short name T344
Test name
Test status
Simulation time 147264867 ps
CPU time 1.31 seconds
Started Jul 22 04:39:08 PM PDT 24
Finished Jul 22 04:39:10 PM PDT 24
Peak memory 197536 kb
Host smart-915da349-26ac-42f3-b091-948ce53480e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198490428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.198490428
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4227208542
Short name T532
Test name
Test status
Simulation time 562962950 ps
CPU time 2.3 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:22 PM PDT 24
Peak memory 197860 kb
Host smart-4a8cc579-d5bf-477c-9485-22cba32bef90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227208542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4227208542
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1091324424
Short name T398
Test name
Test status
Simulation time 40522694 ps
CPU time 1.05 seconds
Started Jul 22 04:39:47 PM PDT 24
Finished Jul 22 04:39:48 PM PDT 24
Peak memory 196288 kb
Host smart-7ba47f69-1642-48e5-9ebe-96037e253a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091324424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1091324424
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2406428357
Short name T17
Test name
Test status
Simulation time 99240983 ps
CPU time 0.94 seconds
Started Jul 22 04:39:07 PM PDT 24
Finished Jul 22 04:39:08 PM PDT 24
Peak memory 196172 kb
Host smart-07bdb6eb-b780-45d0-81fb-e2ab810a5d0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406428357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2406428357
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1767622077
Short name T540
Test name
Test status
Simulation time 9145248074 ps
CPU time 114.26 seconds
Started Jul 22 04:39:06 PM PDT 24
Finished Jul 22 04:41:01 PM PDT 24
Peak memory 198616 kb
Host smart-436a475e-2303-4d39-a647-1cbdbf6f84e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767622077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1767622077
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1679055319
Short name T469
Test name
Test status
Simulation time 31014517 ps
CPU time 0.57 seconds
Started Jul 22 04:39:15 PM PDT 24
Finished Jul 22 04:39:16 PM PDT 24
Peak memory 195032 kb
Host smart-fcffbf37-ce48-498b-ac59-697401acb228
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679055319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1679055319
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2432485179
Short name T305
Test name
Test status
Simulation time 24728175 ps
CPU time 0.74 seconds
Started Jul 22 04:39:13 PM PDT 24
Finished Jul 22 04:39:14 PM PDT 24
Peak memory 194592 kb
Host smart-9ddb2ff9-1983-4a0e-981a-897b20b52ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432485179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2432485179
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.508196756
Short name T278
Test name
Test status
Simulation time 707827231 ps
CPU time 6.37 seconds
Started Jul 22 04:39:17 PM PDT 24
Finished Jul 22 04:39:24 PM PDT 24
Peak memory 197372 kb
Host smart-9ff912fa-62cf-46fa-b1c2-cf7ffcbc1d8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508196756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.508196756
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1457502501
Short name T693
Test name
Test status
Simulation time 522983228 ps
CPU time 0.95 seconds
Started Jul 22 04:39:16 PM PDT 24
Finished Jul 22 04:39:18 PM PDT 24
Peak memory 197076 kb
Host smart-ebf257e8-5642-4676-b3ed-0b7e8dfd2b60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457502501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1457502501
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.898491539
Short name T381
Test name
Test status
Simulation time 226177043 ps
CPU time 1.16 seconds
Started Jul 22 04:39:14 PM PDT 24
Finished Jul 22 04:39:16 PM PDT 24
Peak memory 196516 kb
Host smart-84160d30-c968-40c6-8d05-e1d791a5d351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898491539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.898491539
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.4197572845
Short name T374
Test name
Test status
Simulation time 86837561 ps
CPU time 1.98 seconds
Started Jul 22 04:39:15 PM PDT 24
Finished Jul 22 04:39:18 PM PDT 24
Peak memory 198416 kb
Host smart-f6b2b650-fe97-428f-a66f-9551283fd20f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197572845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.4197572845
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.148170232
Short name T479
Test name
Test status
Simulation time 123690044 ps
CPU time 2.67 seconds
Started Jul 22 04:39:15 PM PDT 24
Finished Jul 22 04:39:18 PM PDT 24
Peak memory 197652 kb
Host smart-ff1c5c55-031a-42eb-a77a-f34a353fb567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148170232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
148170232
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.902957637
Short name T51
Test name
Test status
Simulation time 49360437 ps
CPU time 1.19 seconds
Started Jul 22 04:39:48 PM PDT 24
Finished Jul 22 04:39:50 PM PDT 24
Peak memory 196956 kb
Host smart-c5dc08af-37ae-451d-9216-89af0d66fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902957637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.902957637
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3307401448
Short name T118
Test name
Test status
Simulation time 54930963 ps
CPU time 1.27 seconds
Started Jul 22 04:39:14 PM PDT 24
Finished Jul 22 04:39:15 PM PDT 24
Peak memory 197476 kb
Host smart-eff1dd2c-0b63-4da9-9a32-29d0f82ba0d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307401448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3307401448
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3202348055
Short name T363
Test name
Test status
Simulation time 124417227 ps
CPU time 2.07 seconds
Started Jul 22 04:39:17 PM PDT 24
Finished Jul 22 04:39:20 PM PDT 24
Peak memory 198388 kb
Host smart-20eee843-c02a-47d5-86b8-c083dca883b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202348055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3202348055
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.647807514
Short name T558
Test name
Test status
Simulation time 93012824 ps
CPU time 0.86 seconds
Started Jul 22 04:39:14 PM PDT 24
Finished Jul 22 04:39:15 PM PDT 24
Peak memory 195816 kb
Host smart-f10c52f4-ae22-4c22-92e0-dede68f0bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647807514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.647807514
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1234630892
Short name T566
Test name
Test status
Simulation time 248775785 ps
CPU time 1 seconds
Started Jul 22 04:39:14 PM PDT 24
Finished Jul 22 04:39:16 PM PDT 24
Peak memory 196148 kb
Host smart-226fbe47-15c0-4df8-8345-3a6c20a901c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234630892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1234630892
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2180035273
Short name T369
Test name
Test status
Simulation time 3786296133 ps
CPU time 101.84 seconds
Started Jul 22 04:39:13 PM PDT 24
Finished Jul 22 04:40:56 PM PDT 24
Peak memory 198524 kb
Host smart-68c9b245-a4d7-4116-b8eb-c01e4a7dbc3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180035273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2180035273
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3667492759
Short name T57
Test name
Test status
Simulation time 17202299572 ps
CPU time 304 seconds
Started Jul 22 04:39:16 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 198640 kb
Host smart-1cb47c8a-d06a-483c-9c08-01e8057d95c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3667492759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3667492759
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1982433569
Short name T338
Test name
Test status
Simulation time 53716645 ps
CPU time 0.58 seconds
Started Jul 22 04:39:24 PM PDT 24
Finished Jul 22 04:39:26 PM PDT 24
Peak memory 194272 kb
Host smart-82fefc45-55d7-4528-a5a1-b1778ddaa783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982433569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1982433569
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2802005003
Short name T659
Test name
Test status
Simulation time 48084536 ps
CPU time 0.69 seconds
Started Jul 22 04:39:16 PM PDT 24
Finished Jul 22 04:39:17 PM PDT 24
Peak memory 194144 kb
Host smart-d8df60ab-98eb-46dd-b5b2-df2e6a887aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802005003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2802005003
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2819225137
Short name T697
Test name
Test status
Simulation time 362899944 ps
CPU time 12.73 seconds
Started Jul 22 04:39:25 PM PDT 24
Finished Jul 22 04:39:38 PM PDT 24
Peak memory 198440 kb
Host smart-eaa13eda-1e1e-4d14-aa15-5abd676e786d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819225137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2819225137
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1951321320
Short name T361
Test name
Test status
Simulation time 294510316 ps
CPU time 0.94 seconds
Started Jul 22 04:39:28 PM PDT 24
Finished Jul 22 04:39:30 PM PDT 24
Peak memory 196712 kb
Host smart-94bed97d-7645-4d35-b0a5-29cb445a227b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951321320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1951321320
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2051975697
Short name T680
Test name
Test status
Simulation time 155562537 ps
CPU time 0.85 seconds
Started Jul 22 04:39:16 PM PDT 24
Finished Jul 22 04:39:17 PM PDT 24
Peak memory 196620 kb
Host smart-94038a97-d91f-4f97-9e39-60738895c085
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051975697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2051975697
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.574835331
Short name T314
Test name
Test status
Simulation time 89946212 ps
CPU time 2 seconds
Started Jul 22 04:39:24 PM PDT 24
Finished Jul 22 04:39:26 PM PDT 24
Peak memory 196780 kb
Host smart-5590cabd-5e85-4bb0-b1ef-e7a365a2975d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574835331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.574835331
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3665405538
Short name T125
Test name
Test status
Simulation time 80218907 ps
CPU time 1.44 seconds
Started Jul 22 04:39:16 PM PDT 24
Finished Jul 22 04:39:18 PM PDT 24
Peak memory 197048 kb
Host smart-1c18fc1b-b504-4928-8e67-9cc25932de49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665405538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3665405538
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2204983737
Short name T227
Test name
Test status
Simulation time 49841443 ps
CPU time 0.72 seconds
Started Jul 22 04:39:39 PM PDT 24
Finished Jul 22 04:39:40 PM PDT 24
Peak memory 194616 kb
Host smart-ad6badbc-8df7-417a-9cd2-f471f60d853f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204983737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2204983737
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3323908641
Short name T371
Test name
Test status
Simulation time 36786005 ps
CPU time 0.93 seconds
Started Jul 22 04:39:15 PM PDT 24
Finished Jul 22 04:39:16 PM PDT 24
Peak memory 197168 kb
Host smart-adb73998-3a25-4c9e-8efa-31ad7cf0c07c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323908641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3323908641
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1033219889
Short name T461
Test name
Test status
Simulation time 111805057 ps
CPU time 4.57 seconds
Started Jul 22 04:39:27 PM PDT 24
Finished Jul 22 04:39:31 PM PDT 24
Peak memory 198328 kb
Host smart-f2a06b95-581f-425e-9a20-44b6bde5cf9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033219889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1033219889
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2487920844
Short name T414
Test name
Test status
Simulation time 141629254 ps
CPU time 0.8 seconds
Started Jul 22 04:39:15 PM PDT 24
Finished Jul 22 04:39:16 PM PDT 24
Peak memory 196196 kb
Host smart-942dde89-3e7a-42b4-996d-4c3383f251fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487920844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2487920844
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3807318052
Short name T641
Test name
Test status
Simulation time 52943933 ps
CPU time 1.44 seconds
Started Jul 22 04:39:17 PM PDT 24
Finished Jul 22 04:39:19 PM PDT 24
Peak memory 197276 kb
Host smart-b85e4871-bc96-433c-9036-6f0e6982ffcc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807318052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3807318052
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.138974863
Short name T368
Test name
Test status
Simulation time 7869576300 ps
CPU time 119.91 seconds
Started Jul 22 04:39:24 PM PDT 24
Finished Jul 22 04:41:25 PM PDT 24
Peak memory 198516 kb
Host smart-b63f8f83-cefc-41d0-bf97-5af1c2d20e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138974863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.138974863
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1259168244
Short name T524
Test name
Test status
Simulation time 64493908923 ps
CPU time 1423.48 seconds
Started Jul 22 04:39:31 PM PDT 24
Finished Jul 22 05:03:16 PM PDT 24
Peak memory 198564 kb
Host smart-401942d6-7c0e-4d94-aad9-c95374d5d520
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1259168244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1259168244
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1494670593
Short name T302
Test name
Test status
Simulation time 11441259 ps
CPU time 0.58 seconds
Started Jul 22 04:39:32 PM PDT 24
Finished Jul 22 04:39:33 PM PDT 24
Peak memory 194392 kb
Host smart-3a32b7f8-61e3-4c06-8916-07effe1373f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494670593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1494670593
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.2956275712
Short name T383
Test name
Test status
Simulation time 61384994 ps
CPU time 0.74 seconds
Started Jul 22 04:39:24 PM PDT 24
Finished Jul 22 04:39:25 PM PDT 24
Peak memory 195300 kb
Host smart-7877987e-d309-4790-a772-47ab9408e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956275712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.2956275712
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1961223871
Short name T187
Test name
Test status
Simulation time 1546170247 ps
CPU time 11.43 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:53 PM PDT 24
Peak memory 198356 kb
Host smart-e5b77122-1f65-44c8-8835-46ac183a1e97
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961223871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1961223871
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2061997966
Short name T19
Test name
Test status
Simulation time 72511448 ps
CPU time 1.05 seconds
Started Jul 22 04:39:25 PM PDT 24
Finished Jul 22 04:39:26 PM PDT 24
Peak memory 198136 kb
Host smart-1450f9c6-4e07-4e9f-904f-74c9877f98c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061997966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2061997966
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2122465633
Short name T297
Test name
Test status
Simulation time 86130412 ps
CPU time 1.32 seconds
Started Jul 22 04:39:31 PM PDT 24
Finished Jul 22 04:39:33 PM PDT 24
Peak memory 196484 kb
Host smart-6104d1c5-5c0e-4d23-91f6-3cecf7c2612c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122465633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2122465633
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.227089983
Short name T644
Test name
Test status
Simulation time 64961610 ps
CPU time 2.61 seconds
Started Jul 22 04:39:28 PM PDT 24
Finished Jul 22 04:39:31 PM PDT 24
Peak memory 198532 kb
Host smart-1cfacfdd-4a04-404a-903e-afd8d9e0a394
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227089983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.227089983
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1271612368
Short name T486
Test name
Test status
Simulation time 164404473 ps
CPU time 2.51 seconds
Started Jul 22 04:39:28 PM PDT 24
Finished Jul 22 04:39:31 PM PDT 24
Peak memory 197360 kb
Host smart-534f8469-5ee3-468a-987f-8a741b513873
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271612368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1271612368
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1377392079
Short name T391
Test name
Test status
Simulation time 67826785 ps
CPU time 0.86 seconds
Started Jul 22 04:39:49 PM PDT 24
Finished Jul 22 04:39:51 PM PDT 24
Peak memory 196524 kb
Host smart-a8cbb1fe-b837-479b-a247-da65d0e028de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377392079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1377392079
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.102034558
Short name T614
Test name
Test status
Simulation time 20472833 ps
CPU time 0.67 seconds
Started Jul 22 04:39:25 PM PDT 24
Finished Jul 22 04:39:26 PM PDT 24
Peak memory 194700 kb
Host smart-4701d038-0518-4b74-b11a-f3dc06c14c0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102034558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.102034558
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2501962462
Short name T7
Test name
Test status
Simulation time 926198324 ps
CPU time 3.65 seconds
Started Jul 22 04:39:24 PM PDT 24
Finished Jul 22 04:39:28 PM PDT 24
Peak memory 198304 kb
Host smart-730dc23c-c6a2-424f-b88e-315c760423d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501962462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2501962462
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.2351572304
Short name T648
Test name
Test status
Simulation time 79474330 ps
CPU time 1.2 seconds
Started Jul 22 04:39:24 PM PDT 24
Finished Jul 22 04:39:26 PM PDT 24
Peak memory 195976 kb
Host smart-7ecf070d-8c1e-4d65-9eff-33d885ccdfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351572304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.2351572304
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2188214726
Short name T270
Test name
Test status
Simulation time 31043158 ps
CPU time 0.8 seconds
Started Jul 22 04:39:25 PM PDT 24
Finished Jul 22 04:39:26 PM PDT 24
Peak memory 195740 kb
Host smart-cafb924a-3058-4431-81e2-6663a0906175
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188214726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2188214726
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.16728354
Short name T688
Test name
Test status
Simulation time 5044131553 ps
CPU time 134.83 seconds
Started Jul 22 04:39:33 PM PDT 24
Finished Jul 22 04:41:48 PM PDT 24
Peak memory 198544 kb
Host smart-d51353d4-924d-4c8e-82dc-309ed72a0c2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16728354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gp
io_stress_all.16728354
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.238973244
Short name T498
Test name
Test status
Simulation time 190546813395 ps
CPU time 1622.85 seconds
Started Jul 22 04:40:14 PM PDT 24
Finished Jul 22 05:07:17 PM PDT 24
Peak memory 198688 kb
Host smart-7ec3762c-7121-415d-8abd-094c8b04ff9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=238973244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.238973244
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4084893387
Short name T70
Test name
Test status
Simulation time 14447680 ps
CPU time 0.58 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:42 PM PDT 24
Peak memory 195024 kb
Host smart-8b41aa24-628b-4237-832f-4b858431466f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084893387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4084893387
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2223258209
Short name T201
Test name
Test status
Simulation time 98007333 ps
CPU time 0.76 seconds
Started Jul 22 04:37:43 PM PDT 24
Finished Jul 22 04:37:44 PM PDT 24
Peak memory 195728 kb
Host smart-6be2c411-4b35-4027-9719-e7c6f828430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223258209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2223258209
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3903311941
Short name T716
Test name
Test status
Simulation time 680047235 ps
CPU time 24.52 seconds
Started Jul 22 04:37:43 PM PDT 24
Finished Jul 22 04:38:08 PM PDT 24
Peak memory 197668 kb
Host smart-38feda12-3613-430b-85b0-5abeefd66e52
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903311941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3903311941
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.3292451037
Short name T359
Test name
Test status
Simulation time 273892314 ps
CPU time 0.97 seconds
Started Jul 22 04:40:51 PM PDT 24
Finished Jul 22 04:40:53 PM PDT 24
Peak memory 198204 kb
Host smart-a5201eb5-84cf-40c6-bc3f-9a28f98f2be8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292451037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.3292451037
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2296719073
Short name T633
Test name
Test status
Simulation time 69864170 ps
CPU time 0.7 seconds
Started Jul 22 04:37:42 PM PDT 24
Finished Jul 22 04:37:44 PM PDT 24
Peak memory 194828 kb
Host smart-053f9c72-a1c6-4e0a-83c7-7ff5ee78f62b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296719073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2296719073
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1598939101
Short name T435
Test name
Test status
Simulation time 137437354 ps
CPU time 2.91 seconds
Started Jul 22 04:40:51 PM PDT 24
Finished Jul 22 04:40:55 PM PDT 24
Peak memory 198540 kb
Host smart-8191463f-825b-432f-a262-95fe3943845b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598939101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1598939101
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2350363989
Short name T265
Test name
Test status
Simulation time 462544222 ps
CPU time 3.89 seconds
Started Jul 22 04:37:42 PM PDT 24
Finished Jul 22 04:37:47 PM PDT 24
Peak memory 197456 kb
Host smart-d2c05e94-5673-4fdd-803a-dd20a48c6d44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350363989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2350363989
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2225112536
Short name T276
Test name
Test status
Simulation time 36227394 ps
CPU time 1.22 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:43 PM PDT 24
Peak memory 197464 kb
Host smart-95df529d-f84c-4f61-8da5-0746d5bd8adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225112536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2225112536
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.580549760
Short name T691
Test name
Test status
Simulation time 67802441 ps
CPU time 0.65 seconds
Started Jul 22 04:37:44 PM PDT 24
Finished Jul 22 04:37:45 PM PDT 24
Peak memory 194664 kb
Host smart-ae396910-839f-4126-a254-516f1a67655c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580549760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup_
pulldown.580549760
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.4167919279
Short name T362
Test name
Test status
Simulation time 44380230 ps
CPU time 2.12 seconds
Started Jul 22 04:37:42 PM PDT 24
Finished Jul 22 04:37:45 PM PDT 24
Peak memory 198444 kb
Host smart-822c6aff-f0f4-40d2-8ae3-128e729f84af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167919279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.4167919279
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2609590197
Short name T42
Test name
Test status
Simulation time 118179141 ps
CPU time 0.86 seconds
Started Jul 22 04:37:47 PM PDT 24
Finished Jul 22 04:37:49 PM PDT 24
Peak memory 214400 kb
Host smart-17393dd7-cc0b-43e6-9095-b09694a64bac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609590197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2609590197
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1365016709
Short name T668
Test name
Test status
Simulation time 39398997 ps
CPU time 1.24 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:43 PM PDT 24
Peak memory 196912 kb
Host smart-6b5c79a6-1123-48a0-a975-c871e994fa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365016709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1365016709
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.4028193671
Short name T459
Test name
Test status
Simulation time 27612167 ps
CPU time 0.82 seconds
Started Jul 22 04:37:42 PM PDT 24
Finished Jul 22 04:37:44 PM PDT 24
Peak memory 195548 kb
Host smart-6d1eb9b4-d846-4d53-bc2b-1bdee31852cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028193671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.4028193671
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3160930249
Short name T554
Test name
Test status
Simulation time 31415661774 ps
CPU time 185.2 seconds
Started Jul 22 04:37:46 PM PDT 24
Finished Jul 22 04:40:52 PM PDT 24
Peak memory 198552 kb
Host smart-3b369b72-bcdc-4ce3-a847-585d37394f01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160930249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3160930249
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2495956851
Short name T55
Test name
Test status
Simulation time 53270486587 ps
CPU time 327.66 seconds
Started Jul 22 04:37:44 PM PDT 24
Finished Jul 22 04:43:12 PM PDT 24
Peak memory 198676 kb
Host smart-21e38283-25f8-4053-bb6e-8e494b253cba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2495956851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2495956851
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1068154209
Short name T97
Test name
Test status
Simulation time 14613276 ps
CPU time 0.59 seconds
Started Jul 22 04:39:33 PM PDT 24
Finished Jul 22 04:39:34 PM PDT 24
Peak memory 194320 kb
Host smart-c5fb7dd1-cfa1-433c-998b-7cd5bb314da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068154209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1068154209
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4028317905
Short name T45
Test name
Test status
Simulation time 38993626 ps
CPU time 0.94 seconds
Started Jul 22 04:39:32 PM PDT 24
Finished Jul 22 04:39:33 PM PDT 24
Peak memory 196936 kb
Host smart-588100b3-35b7-45e0-85d0-8332b906171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028317905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4028317905
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1159737345
Short name T682
Test name
Test status
Simulation time 3215510383 ps
CPU time 27.82 seconds
Started Jul 22 04:39:54 PM PDT 24
Finished Jul 22 04:40:22 PM PDT 24
Peak memory 197400 kb
Host smart-52445fd0-4a98-4dee-a029-15afdafb9051
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159737345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1159737345
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3832044470
Short name T689
Test name
Test status
Simulation time 91536777 ps
CPU time 0.63 seconds
Started Jul 22 04:39:33 PM PDT 24
Finished Jul 22 04:39:35 PM PDT 24
Peak memory 195156 kb
Host smart-a471917a-95fb-4e97-9497-df221efd1b80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832044470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3832044470
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.292632553
Short name T98
Test name
Test status
Simulation time 38051399 ps
CPU time 0.91 seconds
Started Jul 22 04:39:32 PM PDT 24
Finished Jul 22 04:39:34 PM PDT 24
Peak memory 196036 kb
Host smart-e23bdc3b-3701-463e-b67c-7d8d8776fa00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292632553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.292632553
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3699972094
Short name T710
Test name
Test status
Simulation time 113839367 ps
CPU time 1.16 seconds
Started Jul 22 04:39:33 PM PDT 24
Finished Jul 22 04:39:35 PM PDT 24
Peak memory 197656 kb
Host smart-bda32691-83a5-4240-9d38-27c7bfa17fbf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699972094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3699972094
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3046609501
Short name T179
Test name
Test status
Simulation time 512511332 ps
CPU time 3 seconds
Started Jul 22 04:39:33 PM PDT 24
Finished Jul 22 04:39:37 PM PDT 24
Peak memory 197504 kb
Host smart-a181fbc8-39ab-4fb2-bc7a-37d61f69369d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046609501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3046609501
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1581666414
Short name T327
Test name
Test status
Simulation time 121001106 ps
CPU time 1.1 seconds
Started Jul 22 04:39:32 PM PDT 24
Finished Jul 22 04:39:34 PM PDT 24
Peak memory 196268 kb
Host smart-d9f82fed-0b86-4eab-8f5a-bfd33a9e6beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581666414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1581666414
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3915833807
Short name T468
Test name
Test status
Simulation time 66456045 ps
CPU time 0.59 seconds
Started Jul 22 04:39:36 PM PDT 24
Finished Jul 22 04:39:37 PM PDT 24
Peak memory 195280 kb
Host smart-322b7bd6-d3fe-48e5-83e7-0d1f30348336
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915833807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3915833807
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.3001515560
Short name T699
Test name
Test status
Simulation time 740291717 ps
CPU time 5.32 seconds
Started Jul 22 04:39:34 PM PDT 24
Finished Jul 22 04:39:40 PM PDT 24
Peak memory 198388 kb
Host smart-6c536e3e-39dc-4d2f-a97c-78da2a8632a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001515560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.3001515560
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.968113790
Short name T184
Test name
Test status
Simulation time 52313900 ps
CPU time 0.87 seconds
Started Jul 22 04:39:31 PM PDT 24
Finished Jul 22 04:39:33 PM PDT 24
Peak memory 196340 kb
Host smart-34093411-3805-4b30-a35d-4702aa6d0103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968113790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.968113790
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1818226802
Short name T543
Test name
Test status
Simulation time 86761057 ps
CPU time 1.19 seconds
Started Jul 22 04:39:32 PM PDT 24
Finished Jul 22 04:39:33 PM PDT 24
Peak memory 196100 kb
Host smart-5498eab1-d4e6-47e7-990f-01f9bd0dff9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818226802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1818226802
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1862537297
Short name T67
Test name
Test status
Simulation time 4053344585 ps
CPU time 53.54 seconds
Started Jul 22 04:39:33 PM PDT 24
Finished Jul 22 04:40:28 PM PDT 24
Peak memory 198488 kb
Host smart-8d8d6cdb-3846-4e2f-9041-d6b4e437408c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862537297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1862537297
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2326404600
Short name T74
Test name
Test status
Simulation time 40460405038 ps
CPU time 1018.7 seconds
Started Jul 22 04:39:32 PM PDT 24
Finished Jul 22 04:56:31 PM PDT 24
Peak memory 198648 kb
Host smart-23b9c0d7-103e-4525-b0c8-377472e3106f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2326404600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2326404600
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3437859557
Short name T35
Test name
Test status
Simulation time 11196997 ps
CPU time 0.57 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:42 PM PDT 24
Peak memory 194336 kb
Host smart-0b1b1c8d-e5da-4988-a495-431f5b6589d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437859557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3437859557
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.607526753
Short name T134
Test name
Test status
Simulation time 19454635 ps
CPU time 0.74 seconds
Started Jul 22 04:39:44 PM PDT 24
Finished Jul 22 04:39:46 PM PDT 24
Peak memory 196288 kb
Host smart-4232f289-4316-4860-a1ca-0da818e53abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607526753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.607526753
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4047388287
Short name T466
Test name
Test status
Simulation time 2149633032 ps
CPU time 29.08 seconds
Started Jul 22 04:39:42 PM PDT 24
Finished Jul 22 04:40:13 PM PDT 24
Peak memory 198544 kb
Host smart-a1f4323f-7b2a-4e55-b456-0e2e0a34682f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047388287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4047388287
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.86139845
Short name T237
Test name
Test status
Simulation time 46982748 ps
CPU time 0.8 seconds
Started Jul 22 04:39:42 PM PDT 24
Finished Jul 22 04:39:44 PM PDT 24
Peak memory 196104 kb
Host smart-8643629d-ffe8-49ed-8e28-a0be61768d1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86139845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.86139845
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.145470449
Short name T636
Test name
Test status
Simulation time 14599811 ps
CPU time 0.62 seconds
Started Jul 22 04:39:43 PM PDT 24
Finished Jul 22 04:39:45 PM PDT 24
Peak memory 194572 kb
Host smart-c66263b1-2f4e-45f0-ab33-bc5b80f8dee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145470449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.145470449
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1255885030
Short name T465
Test name
Test status
Simulation time 240059375 ps
CPU time 2.42 seconds
Started Jul 22 04:40:09 PM PDT 24
Finished Jul 22 04:40:13 PM PDT 24
Peak memory 198364 kb
Host smart-1268a239-5a92-4206-b575-fdba3cd03864
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255885030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1255885030
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1925034331
Short name T608
Test name
Test status
Simulation time 332632987 ps
CPU time 2.53 seconds
Started Jul 22 04:39:40 PM PDT 24
Finished Jul 22 04:39:43 PM PDT 24
Peak memory 196208 kb
Host smart-aa01e01b-7943-494c-98d7-0fa76d67bb01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925034331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1925034331
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2628107732
Short name T207
Test name
Test status
Simulation time 106705924 ps
CPU time 0.86 seconds
Started Jul 22 04:39:42 PM PDT 24
Finished Jul 22 04:39:44 PM PDT 24
Peak memory 197016 kb
Host smart-f285fb34-00fe-4750-8799-33ac6c906de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628107732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2628107732
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.2694233836
Short name T670
Test name
Test status
Simulation time 27669295 ps
CPU time 0.78 seconds
Started Jul 22 04:39:40 PM PDT 24
Finished Jul 22 04:39:41 PM PDT 24
Peak memory 196476 kb
Host smart-6449a9b5-9bb0-4199-bf98-aa1998ac6032
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694233836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.2694233836
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_smoke.1502517589
Short name T342
Test name
Test status
Simulation time 254188803 ps
CPU time 1.1 seconds
Started Jul 22 04:39:51 PM PDT 24
Finished Jul 22 04:39:52 PM PDT 24
Peak memory 196368 kb
Host smart-1915373b-31c1-4b9c-a91d-2a8da42b1383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502517589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1502517589
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3664022233
Short name T389
Test name
Test status
Simulation time 42697984 ps
CPU time 1 seconds
Started Jul 22 04:39:42 PM PDT 24
Finished Jul 22 04:39:44 PM PDT 24
Peak memory 196032 kb
Host smart-eb2cec68-641c-4554-994a-1209258e79b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664022233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3664022233
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.4019098930
Short name T511
Test name
Test status
Simulation time 32126427657 ps
CPU time 186.47 seconds
Started Jul 22 04:40:08 PM PDT 24
Finished Jul 22 04:43:15 PM PDT 24
Peak memory 198540 kb
Host smart-f45fbd60-347c-470a-913f-09cee096bd20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019098930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.4019098930
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4079324748
Short name T354
Test name
Test status
Simulation time 12301791 ps
CPU time 0.64 seconds
Started Jul 22 04:39:44 PM PDT 24
Finished Jul 22 04:39:46 PM PDT 24
Peak memory 194568 kb
Host smart-333fbe88-3e1c-419b-9dbc-59dc522947c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079324748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4079324748
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.267049953
Short name T178
Test name
Test status
Simulation time 30868956 ps
CPU time 0.95 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:44 PM PDT 24
Peak memory 197720 kb
Host smart-3531a885-a2cf-4738-a77c-b96dbbd50d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267049953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.267049953
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.272492558
Short name T565
Test name
Test status
Simulation time 816127614 ps
CPU time 11.98 seconds
Started Jul 22 04:39:44 PM PDT 24
Finished Jul 22 04:39:57 PM PDT 24
Peak memory 197424 kb
Host smart-d66baca7-2dd7-49ba-9024-a961eaee4e14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272492558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.272492558
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.630247909
Short name T647
Test name
Test status
Simulation time 100832485 ps
CPU time 0.86 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:43 PM PDT 24
Peak memory 196996 kb
Host smart-09560c5e-3830-47c1-9fa5-ab6f63853c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630247909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.630247909
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1700203652
Short name T165
Test name
Test status
Simulation time 46318764 ps
CPU time 0.98 seconds
Started Jul 22 04:39:43 PM PDT 24
Finished Jul 22 04:39:45 PM PDT 24
Peak memory 195728 kb
Host smart-e904870a-2238-40e9-a1e2-19bb2f76651d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700203652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1700203652
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2069109630
Short name T348
Test name
Test status
Simulation time 338016734 ps
CPU time 3.58 seconds
Started Jul 22 04:39:43 PM PDT 24
Finished Jul 22 04:39:48 PM PDT 24
Peak memory 198580 kb
Host smart-d06fc16d-0248-4179-a9d9-7caeb1bad423
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069109630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2069109630
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3350942028
Short name T424
Test name
Test status
Simulation time 350342009 ps
CPU time 2 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:45 PM PDT 24
Peak memory 196504 kb
Host smart-d71225c9-db28-49a0-8043-0ed0c6485832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350942028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3350942028
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3418024570
Short name T241
Test name
Test status
Simulation time 557678735 ps
CPU time 0.99 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:44 PM PDT 24
Peak memory 196412 kb
Host smart-0adc450a-6a6b-4053-826d-354e79a1c1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418024570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3418024570
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.204709207
Short name T373
Test name
Test status
Simulation time 52135262 ps
CPU time 1.18 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:44 PM PDT 24
Peak memory 196516 kb
Host smart-29461cdc-018a-44f3-8673-c0dc3c4be438
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204709207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.204709207
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.838386762
Short name T440
Test name
Test status
Simulation time 1751039071 ps
CPU time 6.72 seconds
Started Jul 22 04:39:42 PM PDT 24
Finished Jul 22 04:39:50 PM PDT 24
Peak memory 198336 kb
Host smart-952115ad-e274-4a07-b45e-175f0c7209ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838386762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.838386762
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3955871113
Short name T453
Test name
Test status
Simulation time 43086722 ps
CPU time 1.17 seconds
Started Jul 22 04:39:43 PM PDT 24
Finished Jul 22 04:39:45 PM PDT 24
Peak memory 196712 kb
Host smart-f89f4c7a-a0fe-4996-aabb-1f6971f284d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955871113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3955871113
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1338009618
Short name T415
Test name
Test status
Simulation time 61536884 ps
CPU time 1.28 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:44 PM PDT 24
Peak memory 196284 kb
Host smart-fa07dd4c-7c63-45ba-b0f9-ef18f6f8cfcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338009618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1338009618
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.644642748
Short name T669
Test name
Test status
Simulation time 79259378599 ps
CPU time 180.09 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:42:41 PM PDT 24
Peak memory 198616 kb
Host smart-6645878f-0229-4ea1-9f08-69c19055144c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644642748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.644642748
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.474253462
Short name T690
Test name
Test status
Simulation time 14276211 ps
CPU time 0.57 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 194968 kb
Host smart-bc8e176f-cf57-4081-89d9-e182b0b11b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474253462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.474253462
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1547535684
Short name T282
Test name
Test status
Simulation time 28748904 ps
CPU time 0.74 seconds
Started Jul 22 04:39:51 PM PDT 24
Finished Jul 22 04:39:53 PM PDT 24
Peak memory 196352 kb
Host smart-96341a55-c194-4dea-b203-5085a4f276e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547535684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1547535684
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2839484155
Short name T450
Test name
Test status
Simulation time 3959180217 ps
CPU time 9.79 seconds
Started Jul 22 04:39:52 PM PDT 24
Finished Jul 22 04:40:02 PM PDT 24
Peak memory 197020 kb
Host smart-306eb3f1-012d-43af-b278-b60a2e35753f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839484155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2839484155
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1745667470
Short name T306
Test name
Test status
Simulation time 255785140 ps
CPU time 0.65 seconds
Started Jul 22 04:39:50 PM PDT 24
Finished Jul 22 04:39:52 PM PDT 24
Peak memory 194924 kb
Host smart-032163fa-daad-4d16-9261-47cd827bfdee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745667470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1745667470
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.101754727
Short name T510
Test name
Test status
Simulation time 69394898 ps
CPU time 1.26 seconds
Started Jul 22 04:39:51 PM PDT 24
Finished Jul 22 04:39:53 PM PDT 24
Peak memory 196568 kb
Host smart-a4bbf4f2-2d48-43bb-bb08-c492ed5697c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101754727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.101754727
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.4264220677
Short name T150
Test name
Test status
Simulation time 86774840 ps
CPU time 3.65 seconds
Started Jul 22 04:39:51 PM PDT 24
Finished Jul 22 04:39:56 PM PDT 24
Peak memory 198420 kb
Host smart-6119a067-db1e-42a8-a802-fb3c52eff2c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264220677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.4264220677
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4117603032
Short name T567
Test name
Test status
Simulation time 435460149 ps
CPU time 3.29 seconds
Started Jul 22 04:39:51 PM PDT 24
Finished Jul 22 04:39:55 PM PDT 24
Peak memory 198488 kb
Host smart-9feaee14-c959-4cb8-94a1-5789fb0a7e69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117603032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4117603032
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3659344630
Short name T358
Test name
Test status
Simulation time 213168756 ps
CPU time 1 seconds
Started Jul 22 04:39:53 PM PDT 24
Finished Jul 22 04:39:54 PM PDT 24
Peak memory 196264 kb
Host smart-b1c157d8-a60e-4e10-ae5d-5f8d9cab6ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659344630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3659344630
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.605193455
Short name T147
Test name
Test status
Simulation time 23330772 ps
CPU time 0.7 seconds
Started Jul 22 04:39:50 PM PDT 24
Finished Jul 22 04:39:52 PM PDT 24
Peak memory 194744 kb
Host smart-2edc7273-d02c-4735-8812-a8fdeae7b9fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605193455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.605193455
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3825817084
Short name T570
Test name
Test status
Simulation time 101635212 ps
CPU time 3.88 seconds
Started Jul 22 04:39:49 PM PDT 24
Finished Jul 22 04:39:53 PM PDT 24
Peak memory 198448 kb
Host smart-5df3fdeb-3595-4730-a488-6bca1e908844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825817084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3825817084
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.518974495
Short name T515
Test name
Test status
Simulation time 148112895 ps
CPU time 1.24 seconds
Started Jul 22 04:39:41 PM PDT 24
Finished Jul 22 04:39:44 PM PDT 24
Peak memory 197036 kb
Host smart-da653166-6edd-4f7d-abdd-e9624ffd7f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518974495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.518974495
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2347769221
Short name T61
Test name
Test status
Simulation time 61091156 ps
CPU time 1.29 seconds
Started Jul 22 04:39:50 PM PDT 24
Finished Jul 22 04:39:52 PM PDT 24
Peak memory 195960 kb
Host smart-2bd2329e-6eda-49ab-813c-e24a806ba20e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347769221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2347769221
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3887806870
Short name T290
Test name
Test status
Simulation time 35143422386 ps
CPU time 56.3 seconds
Started Jul 22 04:39:51 PM PDT 24
Finished Jul 22 04:40:48 PM PDT 24
Peak memory 198540 kb
Host smart-12bbaa50-ff75-42b3-9248-d7b10bb48ff7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887806870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3887806870
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3281893390
Short name T616
Test name
Test status
Simulation time 38502365899 ps
CPU time 827.81 seconds
Started Jul 22 04:39:48 PM PDT 24
Finished Jul 22 04:53:37 PM PDT 24
Peak memory 198780 kb
Host smart-81a806c8-ae5c-43e9-8646-9b50666748ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3281893390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3281893390
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2771728703
Short name T520
Test name
Test status
Simulation time 50067423 ps
CPU time 0.59 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:01 PM PDT 24
Peak memory 195184 kb
Host smart-1a639b8e-dba3-4881-a72d-78bd8276c2c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771728703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2771728703
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.668242034
Short name T149
Test name
Test status
Simulation time 23307839 ps
CPU time 0.61 seconds
Started Jul 22 04:39:50 PM PDT 24
Finished Jul 22 04:39:51 PM PDT 24
Peak memory 194312 kb
Host smart-738dfc37-9cb7-4135-a371-02cb1034c4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668242034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.668242034
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1536692882
Short name T542
Test name
Test status
Simulation time 1211316422 ps
CPU time 10.02 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:09 PM PDT 24
Peak memory 197276 kb
Host smart-c5e67ff7-da31-438e-8541-d5ce6b4343bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536692882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1536692882
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2228452182
Short name T561
Test name
Test status
Simulation time 26616502 ps
CPU time 0.71 seconds
Started Jul 22 04:40:02 PM PDT 24
Finished Jul 22 04:40:04 PM PDT 24
Peak memory 195092 kb
Host smart-e8ca9f22-d2a2-4ec6-b368-39109142eea9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228452182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2228452182
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.195313561
Short name T234
Test name
Test status
Simulation time 217689433 ps
CPU time 1.13 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:01 PM PDT 24
Peak memory 196260 kb
Host smart-efe0098e-3fca-475b-9639-ce60ec486bef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195313561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.195313561
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3796530683
Short name T553
Test name
Test status
Simulation time 235452136 ps
CPU time 2.47 seconds
Started Jul 22 04:40:01 PM PDT 24
Finished Jul 22 04:40:04 PM PDT 24
Peak memory 198308 kb
Host smart-0dfc3a90-73bb-4a75-936d-ce6a07f257c7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796530683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3796530683
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3390303858
Short name T294
Test name
Test status
Simulation time 91658927 ps
CPU time 1.02 seconds
Started Jul 22 04:40:10 PM PDT 24
Finished Jul 22 04:40:12 PM PDT 24
Peak memory 195996 kb
Host smart-11afccc3-bd96-4c1b-9761-afe7867d5692
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390303858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3390303858
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4004394978
Short name T256
Test name
Test status
Simulation time 254075290 ps
CPU time 1.29 seconds
Started Jul 22 04:39:53 PM PDT 24
Finished Jul 22 04:39:54 PM PDT 24
Peak memory 198452 kb
Host smart-76814a39-a69f-4d3f-8780-4b195a33c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004394978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4004394978
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1613035697
Short name T639
Test name
Test status
Simulation time 77866207 ps
CPU time 0.65 seconds
Started Jul 22 04:39:50 PM PDT 24
Finished Jul 22 04:39:51 PM PDT 24
Peak memory 195400 kb
Host smart-97922fe0-694a-44eb-897d-49820b034fc4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613035697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1613035697
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3756356335
Short name T279
Test name
Test status
Simulation time 1189788842 ps
CPU time 5.14 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:05 PM PDT 24
Peak memory 198280 kb
Host smart-b043c78c-8e2b-46dd-bfa6-0cd1ec1ce8ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756356335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3756356335
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3858201716
Short name T59
Test name
Test status
Simulation time 144294084 ps
CPU time 0.81 seconds
Started Jul 22 04:39:50 PM PDT 24
Finished Jul 22 04:39:51 PM PDT 24
Peak memory 195604 kb
Host smart-54c8faa5-c186-4c40-b081-cc1fca1ee58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858201716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3858201716
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3276934793
Short name T182
Test name
Test status
Simulation time 549592161 ps
CPU time 1.12 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 195812 kb
Host smart-f2aea179-ab42-4091-be50-35b71d73c123
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276934793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3276934793
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3080694058
Short name T620
Test name
Test status
Simulation time 14811203400 ps
CPU time 26.67 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:26 PM PDT 24
Peak memory 198564 kb
Host smart-6e66a942-ef4b-44d1-9233-1992bb3cf2e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080694058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3080694058
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2209063522
Short name T407
Test name
Test status
Simulation time 45343760 ps
CPU time 0.59 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:00 PM PDT 24
Peak memory 195084 kb
Host smart-89d4911f-cd9c-4681-b2de-4bf9908db3f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209063522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2209063522
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1304231849
Short name T707
Test name
Test status
Simulation time 83192529 ps
CPU time 0.85 seconds
Started Jul 22 04:40:01 PM PDT 24
Finished Jul 22 04:40:02 PM PDT 24
Peak memory 195804 kb
Host smart-8f90829b-592c-42db-b749-2e32be98128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304231849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1304231849
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.557428798
Short name T711
Test name
Test status
Simulation time 219790531 ps
CPU time 6.98 seconds
Started Jul 22 04:40:00 PM PDT 24
Finished Jul 22 04:40:08 PM PDT 24
Peak memory 197344 kb
Host smart-1b2158fd-fb82-437c-8769-18fb009b404e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557428798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.557428798
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2685525392
Short name T503
Test name
Test status
Simulation time 94739646 ps
CPU time 0.79 seconds
Started Jul 22 04:39:58 PM PDT 24
Finished Jul 22 04:39:59 PM PDT 24
Peak memory 196296 kb
Host smart-c56b3b08-a7e6-4819-8df5-c43d0c27bdd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685525392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2685525392
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2451024018
Short name T505
Test name
Test status
Simulation time 72608635 ps
CPU time 0.73 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:01 PM PDT 24
Peak memory 196476 kb
Host smart-1cb760a0-3d51-4140-b2ba-f99a6e0dcf3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451024018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2451024018
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3574671296
Short name T655
Test name
Test status
Simulation time 200399086 ps
CPU time 3.28 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:03 PM PDT 24
Peak memory 197516 kb
Host smart-70ed4ca9-3ab7-4dc8-95fb-45bffa5124bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574671296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3574671296
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2205735206
Short name T544
Test name
Test status
Simulation time 358026207 ps
CPU time 1.16 seconds
Started Jul 22 04:40:00 PM PDT 24
Finished Jul 22 04:40:01 PM PDT 24
Peak memory 196292 kb
Host smart-ddbd31c6-f8e4-454f-bb9d-e3e39e29353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205735206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2205735206
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2576796121
Short name T299
Test name
Test status
Simulation time 88308564 ps
CPU time 1.12 seconds
Started Jul 22 04:40:01 PM PDT 24
Finished Jul 22 04:40:03 PM PDT 24
Peak memory 196972 kb
Host smart-6cbec036-e81f-4060-b3d9-1b2f9a395c83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576796121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2576796121
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2454083852
Short name T613
Test name
Test status
Simulation time 1561991758 ps
CPU time 4.7 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:40:05 PM PDT 24
Peak memory 198436 kb
Host smart-b4d35907-68da-4eb0-9e35-48a2cdedc5cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454083852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2454083852
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.57129933
Short name T217
Test name
Test status
Simulation time 208990250 ps
CPU time 1.21 seconds
Started Jul 22 04:39:58 PM PDT 24
Finished Jul 22 04:40:00 PM PDT 24
Peak memory 196660 kb
Host smart-fc95f38a-a52b-4e12-82ce-bccafdad30bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57129933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.57129933
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2262053782
Short name T233
Test name
Test status
Simulation time 56063701 ps
CPU time 0.87 seconds
Started Jul 22 04:40:00 PM PDT 24
Finished Jul 22 04:40:01 PM PDT 24
Peak memory 195564 kb
Host smart-ed7475af-ccc6-4adf-a347-f71d34c0f8c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262053782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2262053782
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.74617048
Short name T653
Test name
Test status
Simulation time 9936971593 ps
CPU time 139.09 seconds
Started Jul 22 04:40:00 PM PDT 24
Finished Jul 22 04:42:20 PM PDT 24
Peak memory 198460 kb
Host smart-58a8d27f-d104-41de-baed-cf67d4396b7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74617048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gp
io_stress_all.74617048
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3196622335
Short name T489
Test name
Test status
Simulation time 27549450917 ps
CPU time 446.54 seconds
Started Jul 22 04:39:59 PM PDT 24
Finished Jul 22 04:47:27 PM PDT 24
Peak memory 198628 kb
Host smart-afd68f77-d27b-43e9-ad40-e582f0241c3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3196622335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3196622335
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1778327197
Short name T257
Test name
Test status
Simulation time 15600540 ps
CPU time 0.57 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 195100 kb
Host smart-5a637e93-cffc-4332-8f44-2d72d9454a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778327197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1778327197
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.4077586105
Short name T617
Test name
Test status
Simulation time 287301734 ps
CPU time 0.93 seconds
Started Jul 22 04:40:09 PM PDT 24
Finished Jul 22 04:40:11 PM PDT 24
Peak memory 196792 kb
Host smart-e7dd538c-e873-4dff-aa7b-e41f0426b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077586105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.4077586105
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.532491968
Short name T663
Test name
Test status
Simulation time 360714833 ps
CPU time 12.64 seconds
Started Jul 22 04:40:10 PM PDT 24
Finished Jul 22 04:40:24 PM PDT 24
Peak memory 195980 kb
Host smart-b3050881-86d1-455f-b112-6a1e40b814ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532491968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.532491968
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.116545240
Short name T483
Test name
Test status
Simulation time 71805898 ps
CPU time 0.95 seconds
Started Jul 22 04:40:30 PM PDT 24
Finished Jul 22 04:40:31 PM PDT 24
Peak memory 196480 kb
Host smart-cd9fbf2e-f8ca-4dca-946f-73442a97f1b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116545240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.116545240
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2118766364
Short name T160
Test name
Test status
Simulation time 169723082 ps
CPU time 1.02 seconds
Started Jul 22 04:40:08 PM PDT 24
Finished Jul 22 04:40:09 PM PDT 24
Peak memory 196152 kb
Host smart-39351681-cd8e-4d9b-8d39-93b091d5edb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118766364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2118766364
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2263431021
Short name T441
Test name
Test status
Simulation time 245888994 ps
CPU time 2.57 seconds
Started Jul 22 04:40:10 PM PDT 24
Finished Jul 22 04:40:13 PM PDT 24
Peak memory 198380 kb
Host smart-2e570a5f-7615-4dce-b359-c772b04b16b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263431021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2263431021
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1658833707
Short name T213
Test name
Test status
Simulation time 848551671 ps
CPU time 3.11 seconds
Started Jul 22 04:40:09 PM PDT 24
Finished Jul 22 04:40:13 PM PDT 24
Peak memory 197624 kb
Host smart-5b410958-cc2d-431d-bfa8-e78f748a55b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658833707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1658833707
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1299316524
Short name T629
Test name
Test status
Simulation time 199884980 ps
CPU time 1.15 seconds
Started Jul 22 04:40:10 PM PDT 24
Finished Jul 22 04:40:12 PM PDT 24
Peak memory 196388 kb
Host smart-2d0d34f5-0298-4193-a3e9-9fa7f732bdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299316524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1299316524
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3713718636
Short name T492
Test name
Test status
Simulation time 26185558 ps
CPU time 1.04 seconds
Started Jul 22 04:40:10 PM PDT 24
Finished Jul 22 04:40:11 PM PDT 24
Peak memory 196312 kb
Host smart-21db18af-669a-43a7-babd-550a75610adb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713718636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3713718636
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1325135861
Short name T366
Test name
Test status
Simulation time 77926083 ps
CPU time 3.02 seconds
Started Jul 22 04:41:04 PM PDT 24
Finished Jul 22 04:41:07 PM PDT 24
Peak memory 198320 kb
Host smart-f4ea33e9-9298-4543-9458-f7a765a8d73a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325135861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1325135861
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2438152182
Short name T311
Test name
Test status
Simulation time 65393412 ps
CPU time 1.36 seconds
Started Jul 22 04:40:08 PM PDT 24
Finished Jul 22 04:40:10 PM PDT 24
Peak memory 197180 kb
Host smart-596ec5ff-6a1b-429e-a6f4-0f15d369a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438152182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2438152182
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2309836130
Short name T214
Test name
Test status
Simulation time 322489806 ps
CPU time 1.53 seconds
Started Jul 22 04:40:10 PM PDT 24
Finished Jul 22 04:40:13 PM PDT 24
Peak memory 197248 kb
Host smart-be2ae584-1f16-47bd-9764-358ed8d82102
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309836130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2309836130
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3033560885
Short name T120
Test name
Test status
Simulation time 5099047167 ps
CPU time 63.61 seconds
Started Jul 22 04:40:24 PM PDT 24
Finished Jul 22 04:41:28 PM PDT 24
Peak memory 198532 kb
Host smart-bd8982a2-6d58-4556-b7ba-02c43bd05568
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033560885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3033560885
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1141618376
Short name T135
Test name
Test status
Simulation time 14088352 ps
CPU time 0.57 seconds
Started Jul 22 04:40:16 PM PDT 24
Finished Jul 22 04:40:17 PM PDT 24
Peak memory 194340 kb
Host smart-7de9a92a-947f-4b6b-bc97-c2c3f7f4d498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141618376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1141618376
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.70722642
Short name T137
Test name
Test status
Simulation time 26504854 ps
CPU time 0.85 seconds
Started Jul 22 04:40:21 PM PDT 24
Finished Jul 22 04:40:22 PM PDT 24
Peak memory 195920 kb
Host smart-85a2065a-2d0d-4d1c-8387-c9120376e7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70722642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.70722642
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1164693105
Short name T44
Test name
Test status
Simulation time 154888484 ps
CPU time 8.16 seconds
Started Jul 22 04:40:16 PM PDT 24
Finished Jul 22 04:40:24 PM PDT 24
Peak memory 197496 kb
Host smart-88652166-06da-4650-8d45-d382e4db1e50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164693105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1164693105
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2304013817
Short name T267
Test name
Test status
Simulation time 22354251 ps
CPU time 0.65 seconds
Started Jul 22 04:40:17 PM PDT 24
Finished Jul 22 04:40:19 PM PDT 24
Peak memory 194472 kb
Host smart-f5f15b70-494b-45ae-b181-4bc8f66ec183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304013817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2304013817
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3655052612
Short name T220
Test name
Test status
Simulation time 56144652 ps
CPU time 1.09 seconds
Started Jul 22 04:40:16 PM PDT 24
Finished Jul 22 04:40:18 PM PDT 24
Peak memory 197096 kb
Host smart-21575dc1-bf51-4d52-afa9-8b36c12875c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655052612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3655052612
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.36405588
Short name T231
Test name
Test status
Simulation time 51575132 ps
CPU time 2.09 seconds
Started Jul 22 04:40:32 PM PDT 24
Finished Jul 22 04:40:34 PM PDT 24
Peak memory 198484 kb
Host smart-2f8ef812-b98c-467b-ad9d-5afbdce8e84e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36405588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.gpio_intr_with_filter_rand_intr_event.36405588
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3927104111
Short name T467
Test name
Test status
Simulation time 56214707 ps
CPU time 1.34 seconds
Started Jul 22 04:40:19 PM PDT 24
Finished Jul 22 04:40:20 PM PDT 24
Peak memory 197264 kb
Host smart-0d961203-93ae-4d11-8de9-b2540faa44b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927104111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3927104111
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2126941909
Short name T152
Test name
Test status
Simulation time 16716287 ps
CPU time 0.73 seconds
Started Jul 22 04:40:17 PM PDT 24
Finished Jul 22 04:40:18 PM PDT 24
Peak memory 194676 kb
Host smart-bbb4eb51-0540-4688-a5d0-8926472f3eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126941909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2126941909
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.244027686
Short name T343
Test name
Test status
Simulation time 91432361 ps
CPU time 1.05 seconds
Started Jul 22 04:40:21 PM PDT 24
Finished Jul 22 04:40:23 PM PDT 24
Peak memory 196368 kb
Host smart-9db4c9af-d73b-477f-8f35-cc88d3c26250
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244027686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.244027686
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2078282881
Short name T351
Test name
Test status
Simulation time 266249159 ps
CPU time 2.56 seconds
Started Jul 22 04:40:16 PM PDT 24
Finished Jul 22 04:40:18 PM PDT 24
Peak memory 198388 kb
Host smart-5f45d708-fa8f-4cfc-9e6b-4dea33cc92c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078282881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2078282881
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2992065505
Short name T136
Test name
Test status
Simulation time 32371005 ps
CPU time 0.9 seconds
Started Jul 22 04:40:21 PM PDT 24
Finished Jul 22 04:40:22 PM PDT 24
Peak memory 197732 kb
Host smart-872c14f2-6bff-4765-bb39-c45b5f3b1633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992065505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2992065505
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3570488980
Short name T268
Test name
Test status
Simulation time 47055060 ps
CPU time 1.34 seconds
Started Jul 22 04:40:22 PM PDT 24
Finished Jul 22 04:40:24 PM PDT 24
Peak memory 197008 kb
Host smart-58c5c763-75c4-41bb-a680-d5f77193aa65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570488980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3570488980
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1228851629
Short name T197
Test name
Test status
Simulation time 11227707016 ps
CPU time 74.29 seconds
Started Jul 22 04:40:17 PM PDT 24
Finished Jul 22 04:41:31 PM PDT 24
Peak memory 198512 kb
Host smart-08e5a93f-a81d-44ef-909b-13b809e13547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228851629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1228851629
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1957093628
Short name T482
Test name
Test status
Simulation time 15461005 ps
CPU time 0.59 seconds
Started Jul 22 04:40:26 PM PDT 24
Finished Jul 22 04:40:28 PM PDT 24
Peak memory 195192 kb
Host smart-04950abe-b727-427c-a525-fd4dbe13e01a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957093628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1957093628
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1892260275
Short name T196
Test name
Test status
Simulation time 34403370 ps
CPU time 0.88 seconds
Started Jul 22 04:40:21 PM PDT 24
Finished Jul 22 04:40:23 PM PDT 24
Peak memory 197044 kb
Host smart-3e34eef0-06ef-4f97-8c9b-9b1132d8c558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892260275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1892260275
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3609138705
Short name T96
Test name
Test status
Simulation time 2111423128 ps
CPU time 25.81 seconds
Started Jul 22 04:40:21 PM PDT 24
Finished Jul 22 04:40:48 PM PDT 24
Peak memory 196680 kb
Host smart-fe416668-f7c2-4c12-afd4-f03990ee02b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609138705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3609138705
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.254816289
Short name T142
Test name
Test status
Simulation time 289460935 ps
CPU time 0.89 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:40:26 PM PDT 24
Peak memory 196396 kb
Host smart-fb1e96e0-5081-46d7-aca4-3225e2028cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254816289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.254816289
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.366379424
Short name T574
Test name
Test status
Simulation time 174653001 ps
CPU time 0.86 seconds
Started Jul 22 04:40:18 PM PDT 24
Finished Jul 22 04:40:19 PM PDT 24
Peak memory 197080 kb
Host smart-e4b3a20a-6210-40c9-b37d-fed68ca6259b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366379424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.366379424
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1447004833
Short name T595
Test name
Test status
Simulation time 979151275 ps
CPU time 3.52 seconds
Started Jul 22 04:40:18 PM PDT 24
Finished Jul 22 04:40:22 PM PDT 24
Peak memory 198420 kb
Host smart-cc0da6ac-c1f1-494d-84cc-348188b59126
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447004833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1447004833
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4165603661
Short name T164
Test name
Test status
Simulation time 276045251 ps
CPU time 1.42 seconds
Started Jul 22 04:40:24 PM PDT 24
Finished Jul 22 04:40:25 PM PDT 24
Peak memory 196152 kb
Host smart-1510dcbc-9fb8-492e-afc2-5d5a0948e837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165603661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4165603661
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1643611238
Short name T113
Test name
Test status
Simulation time 25305946 ps
CPU time 0.75 seconds
Started Jul 22 04:40:16 PM PDT 24
Finished Jul 22 04:40:17 PM PDT 24
Peak memory 195624 kb
Host smart-49bd407c-1078-412d-a545-4bc804f6149e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643611238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1643611238
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2598509863
Short name T412
Test name
Test status
Simulation time 19088717 ps
CPU time 0.77 seconds
Started Jul 22 04:44:19 PM PDT 24
Finished Jul 22 04:44:21 PM PDT 24
Peak memory 196400 kb
Host smart-bc831c99-2de7-44e7-94fc-18257f6c1cac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598509863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2598509863
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1675096899
Short name T432
Test name
Test status
Simulation time 685183157 ps
CPU time 2.51 seconds
Started Jul 22 04:40:26 PM PDT 24
Finished Jul 22 04:40:30 PM PDT 24
Peak memory 198352 kb
Host smart-db570f10-014b-4579-83e4-671b00ae5675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675096899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1675096899
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.293246658
Short name T248
Test name
Test status
Simulation time 169907285 ps
CPU time 1.03 seconds
Started Jul 22 04:40:16 PM PDT 24
Finished Jul 22 04:40:17 PM PDT 24
Peak memory 197388 kb
Host smart-4cb8ae82-cc22-452a-b69c-e4e81df1694a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293246658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.293246658
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3281852879
Short name T587
Test name
Test status
Simulation time 60997880 ps
CPU time 1.1 seconds
Started Jul 22 04:40:20 PM PDT 24
Finished Jul 22 04:40:22 PM PDT 24
Peak memory 196020 kb
Host smart-c3c380c7-7129-4ffd-99bc-1e62c1b27f1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281852879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3281852879
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2457204402
Short name T430
Test name
Test status
Simulation time 37624913757 ps
CPU time 82.64 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:41:49 PM PDT 24
Peak memory 198524 kb
Host smart-b99b69c5-4da7-4ab6-a29b-b30b51a7a309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457204402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2457204402
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3666529972
Short name T49
Test name
Test status
Simulation time 75187875024 ps
CPU time 1029.41 seconds
Started Jul 22 04:40:26 PM PDT 24
Finished Jul 22 04:57:36 PM PDT 24
Peak memory 198624 kb
Host smart-6dbfd685-8c30-44f6-ab85-b1308c24e422
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3666529972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3666529972
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.904922097
Short name T704
Test name
Test status
Simulation time 11793685 ps
CPU time 0.61 seconds
Started Jul 22 04:40:27 PM PDT 24
Finished Jul 22 04:40:28 PM PDT 24
Peak memory 195316 kb
Host smart-d26103f2-991e-4384-9984-8d12d5bba681
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904922097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.904922097
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3936282097
Short name T545
Test name
Test status
Simulation time 20817060 ps
CPU time 0.66 seconds
Started Jul 22 04:40:26 PM PDT 24
Finished Jul 22 04:40:27 PM PDT 24
Peak memory 195232 kb
Host smart-594f7f65-36b3-439b-b386-5a098ca2b1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936282097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3936282097
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4239556967
Short name T226
Test name
Test status
Simulation time 1587946088 ps
CPU time 20.83 seconds
Started Jul 22 04:40:26 PM PDT 24
Finished Jul 22 04:40:47 PM PDT 24
Peak memory 198456 kb
Host smart-47b65d1b-bb8b-402a-9e5d-93a1406933d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239556967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4239556967
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1339935107
Short name T519
Test name
Test status
Simulation time 310862477 ps
CPU time 1.09 seconds
Started Jul 22 04:40:26 PM PDT 24
Finished Jul 22 04:40:28 PM PDT 24
Peak memory 197096 kb
Host smart-82f7d3e3-318c-4dee-b2e5-27cfaf5857e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339935107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1339935107
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3082553547
Short name T497
Test name
Test status
Simulation time 252431202 ps
CPU time 0.75 seconds
Started Jul 22 04:40:27 PM PDT 24
Finished Jul 22 04:40:28 PM PDT 24
Peak memory 195840 kb
Host smart-5eeadcd0-84b6-4cdf-90e7-f65b987e539f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082553547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3082553547
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4272443165
Short name T523
Test name
Test status
Simulation time 76491013 ps
CPU time 2.94 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:40:29 PM PDT 24
Peak memory 198476 kb
Host smart-42e7283e-691e-45f1-9a3d-e1bf0b2b7023
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272443165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4272443165
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3955805470
Short name T596
Test name
Test status
Simulation time 152987293 ps
CPU time 2.67 seconds
Started Jul 22 04:40:27 PM PDT 24
Finished Jul 22 04:40:31 PM PDT 24
Peak memory 197644 kb
Host smart-31e691aa-b67b-48ad-896d-86d91ff84d10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955805470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3955805470
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3942955285
Short name T457
Test name
Test status
Simulation time 86354566 ps
CPU time 0.69 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:40:27 PM PDT 24
Peak memory 195440 kb
Host smart-9c52d89c-655f-40b3-9ee2-d71685e2083f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942955285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3942955285
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2164567802
Short name T289
Test name
Test status
Simulation time 94900791 ps
CPU time 1.04 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:40:27 PM PDT 24
Peak memory 196400 kb
Host smart-54e6696b-3734-4004-87f0-0878d1d51cb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164567802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2164567802
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.921452180
Short name T313
Test name
Test status
Simulation time 207624483 ps
CPU time 2.49 seconds
Started Jul 22 04:40:24 PM PDT 24
Finished Jul 22 04:40:27 PM PDT 24
Peak memory 198396 kb
Host smart-63de1b1e-ca71-4e11-b3ad-d34a128f2b18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921452180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.921452180
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3941421894
Short name T224
Test name
Test status
Simulation time 34472189 ps
CPU time 1.09 seconds
Started Jul 22 04:40:24 PM PDT 24
Finished Jul 22 04:40:26 PM PDT 24
Peak memory 195964 kb
Host smart-b2f1aedb-db5f-4d6b-bb8a-2c62ebe28452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941421894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3941421894
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.657127067
Short name T281
Test name
Test status
Simulation time 154216061 ps
CPU time 0.89 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:40:26 PM PDT 24
Peak memory 196884 kb
Host smart-712ced38-62ae-4b35-8f44-f69438bab6d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657127067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.657127067
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.4049919338
Short name T702
Test name
Test status
Simulation time 15791592743 ps
CPU time 133.67 seconds
Started Jul 22 04:40:26 PM PDT 24
Finished Jul 22 04:42:40 PM PDT 24
Peak memory 198564 kb
Host smart-cdf933df-6f1f-4744-8e01-a86a2e94b2b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049919338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.4049919338
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.53581713
Short name T708
Test name
Test status
Simulation time 712067005550 ps
CPU time 1578.51 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 05:06:44 PM PDT 24
Peak memory 198708 kb
Host smart-c8816d14-8d24-410f-94bc-71347dffc6fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=53581713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.53581713
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.4189821526
Short name T529
Test name
Test status
Simulation time 15298349 ps
CPU time 0.59 seconds
Started Jul 22 04:37:51 PM PDT 24
Finished Jul 22 04:37:52 PM PDT 24
Peak memory 194344 kb
Host smart-346618b5-3cf3-44ef-9c8c-cacd994d280b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189821526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4189821526
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1899344741
Short name T170
Test name
Test status
Simulation time 308368946 ps
CPU time 0.72 seconds
Started Jul 22 04:40:52 PM PDT 24
Finished Jul 22 04:40:53 PM PDT 24
Peak memory 195364 kb
Host smart-598adb34-9d1a-4745-b4ad-bd4135f3b0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899344741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1899344741
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2090755550
Short name T144
Test name
Test status
Simulation time 354611310 ps
CPU time 18.77 seconds
Started Jul 22 04:37:52 PM PDT 24
Finished Jul 22 04:38:11 PM PDT 24
Peak memory 197352 kb
Host smart-4668ecc6-3460-4901-be66-25fb817acd5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090755550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2090755550
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3433255892
Short name T161
Test name
Test status
Simulation time 68776951 ps
CPU time 0.74 seconds
Started Jul 22 04:37:53 PM PDT 24
Finished Jul 22 04:37:55 PM PDT 24
Peak memory 195012 kb
Host smart-2651157e-3ecd-4bdb-a585-d11f45b2b778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433255892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3433255892
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3007396122
Short name T122
Test name
Test status
Simulation time 233729404 ps
CPU time 0.78 seconds
Started Jul 22 04:37:52 PM PDT 24
Finished Jul 22 04:37:54 PM PDT 24
Peak memory 195820 kb
Host smart-2ae1da65-fbb4-47d0-a9a7-96c4247bb4c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007396122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3007396122
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2982507596
Short name T261
Test name
Test status
Simulation time 82692592 ps
CPU time 1.65 seconds
Started Jul 22 04:37:57 PM PDT 24
Finished Jul 22 04:37:59 PM PDT 24
Peak memory 197348 kb
Host smart-47b82da8-d6c6-4b8f-9d4b-461d88f357ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982507596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2982507596
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1743049108
Short name T193
Test name
Test status
Simulation time 486779512 ps
CPU time 3.24 seconds
Started Jul 22 04:37:53 PM PDT 24
Finished Jul 22 04:37:57 PM PDT 24
Peak memory 198500 kb
Host smart-4061cc99-b92c-4f5f-888a-60d6b4a85d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743049108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1743049108
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3615565940
Short name T632
Test name
Test status
Simulation time 43095549 ps
CPU time 0.93 seconds
Started Jul 22 04:37:46 PM PDT 24
Finished Jul 22 04:37:48 PM PDT 24
Peak memory 196280 kb
Host smart-2f29d6a8-c974-4d7e-8ec5-697ee93289ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615565940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3615565940
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.736157591
Short name T405
Test name
Test status
Simulation time 68970401 ps
CPU time 0.71 seconds
Started Jul 22 04:37:44 PM PDT 24
Finished Jul 22 04:37:45 PM PDT 24
Peak memory 195844 kb
Host smart-7be76828-deaa-4adc-830f-5b70fd729cef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736157591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.736157591
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4152052045
Short name T206
Test name
Test status
Simulation time 84343834 ps
CPU time 1.06 seconds
Started Jul 22 04:37:52 PM PDT 24
Finished Jul 22 04:37:53 PM PDT 24
Peak memory 196580 kb
Host smart-0e8a08e6-440c-4af2-92fd-8759bd7f721c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152052045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4152052045
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1974301104
Short name T31
Test name
Test status
Simulation time 38015446 ps
CPU time 0.79 seconds
Started Jul 22 04:38:50 PM PDT 24
Finished Jul 22 04:38:52 PM PDT 24
Peak memory 214260 kb
Host smart-030b5ba0-5de8-473d-b474-e4fb44fe729c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974301104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1974301104
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.967597840
Short name T460
Test name
Test status
Simulation time 76406521 ps
CPU time 1.16 seconds
Started Jul 22 04:40:51 PM PDT 24
Finished Jul 22 04:40:53 PM PDT 24
Peak memory 196220 kb
Host smart-e47d654b-6f6a-4d34-adcf-95060f2907fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967597840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.967597840
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.518504279
Short name T526
Test name
Test status
Simulation time 166304180 ps
CPU time 1.35 seconds
Started Jul 22 04:37:47 PM PDT 24
Finished Jul 22 04:37:49 PM PDT 24
Peak memory 197272 kb
Host smart-2d804dcc-558b-48f0-ab19-ec809e4d4174
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518504279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.518504279
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.944107014
Short name T10
Test name
Test status
Simulation time 31001227325 ps
CPU time 87.45 seconds
Started Jul 22 04:37:57 PM PDT 24
Finished Jul 22 04:39:25 PM PDT 24
Peak memory 198604 kb
Host smart-5800cfd7-42d1-49a1-a0b5-6abe03de770f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944107014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.944107014
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1967181300
Short name T713
Test name
Test status
Simulation time 88066607816 ps
CPU time 2028.17 seconds
Started Jul 22 04:37:50 PM PDT 24
Finished Jul 22 05:11:39 PM PDT 24
Peak memory 198660 kb
Host smart-c7d6a3a8-5715-4d09-a0e4-b1eff235b7ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1967181300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1967181300
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2710608496
Short name T153
Test name
Test status
Simulation time 63463661 ps
CPU time 0.62 seconds
Started Jul 22 04:40:36 PM PDT 24
Finished Jul 22 04:40:37 PM PDT 24
Peak memory 194648 kb
Host smart-7708f098-827e-493a-a99e-582a8c75e2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710608496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2710608496
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.4087445275
Short name T68
Test name
Test status
Simulation time 24951606 ps
CPU time 0.78 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:40:27 PM PDT 24
Peak memory 195604 kb
Host smart-897755d9-3a46-4d75-a330-2062a4b092db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087445275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.4087445275
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.586711224
Short name T346
Test name
Test status
Simulation time 1487052307 ps
CPU time 18.18 seconds
Started Jul 22 04:40:34 PM PDT 24
Finished Jul 22 04:40:52 PM PDT 24
Peak memory 197268 kb
Host smart-306fff4a-55bc-4239-a5da-54d935d88436
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586711224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.586711224
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.752830466
Short name T284
Test name
Test status
Simulation time 270498721 ps
CPU time 1.01 seconds
Started Jul 22 04:40:35 PM PDT 24
Finished Jul 22 04:40:36 PM PDT 24
Peak memory 198312 kb
Host smart-81b436b6-05d4-41f9-883e-7206c04bd67a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752830466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.752830466
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2959715419
Short name T199
Test name
Test status
Simulation time 160197949 ps
CPU time 1.29 seconds
Started Jul 22 04:40:42 PM PDT 24
Finished Jul 22 04:40:44 PM PDT 24
Peak memory 196464 kb
Host smart-8906b656-a322-4378-bce7-2490368ce344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959715419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2959715419
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2674053311
Short name T705
Test name
Test status
Simulation time 131940578 ps
CPU time 2.86 seconds
Started Jul 22 04:40:38 PM PDT 24
Finished Jul 22 04:40:41 PM PDT 24
Peak memory 198472 kb
Host smart-24209d8b-e1d1-4478-95ea-548b6311cf75
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674053311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2674053311
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1077680469
Short name T307
Test name
Test status
Simulation time 115997058 ps
CPU time 3.44 seconds
Started Jul 22 04:40:38 PM PDT 24
Finished Jul 22 04:40:41 PM PDT 24
Peak memory 198540 kb
Host smart-e50b6a30-c727-4cbd-9fa0-f77cb43043a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077680469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1077680469
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3945666392
Short name T377
Test name
Test status
Simulation time 91840119 ps
CPU time 1.03 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:40:27 PM PDT 24
Peak memory 196244 kb
Host smart-7c4b6a96-f5ce-4734-9e24-81aaf70d2266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945666392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3945666392
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.38141222
Short name T571
Test name
Test status
Simulation time 55507135 ps
CPU time 1.26 seconds
Started Jul 22 04:40:26 PM PDT 24
Finished Jul 22 04:40:28 PM PDT 24
Peak memory 196996 kb
Host smart-e307781f-1e82-4de3-9b93-9df1380e1774
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38141222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup_
pulldown.38141222
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3361572346
Short name T557
Test name
Test status
Simulation time 693746022 ps
CPU time 5.45 seconds
Started Jul 22 04:40:34 PM PDT 24
Finished Jul 22 04:40:40 PM PDT 24
Peak memory 198464 kb
Host smart-8e667b36-e6e4-4a10-a172-5084e7850942
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361572346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3361572346
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.4040985246
Short name T491
Test name
Test status
Simulation time 40900218 ps
CPU time 1.16 seconds
Started Jul 22 04:40:27 PM PDT 24
Finished Jul 22 04:40:29 PM PDT 24
Peak memory 198440 kb
Host smart-4daf3b3d-c16d-4d00-851e-dfaebeceb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040985246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.4040985246
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3520058447
Short name T530
Test name
Test status
Simulation time 876504334 ps
CPU time 1.35 seconds
Started Jul 22 04:40:25 PM PDT 24
Finished Jul 22 04:40:27 PM PDT 24
Peak memory 196816 kb
Host smart-7b7e98d5-0f83-4425-a2fd-83da6a05015e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520058447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3520058447
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1772852128
Short name T328
Test name
Test status
Simulation time 23921367703 ps
CPU time 147.07 seconds
Started Jul 22 04:40:35 PM PDT 24
Finished Jul 22 04:43:03 PM PDT 24
Peak memory 198528 kb
Host smart-19a5598a-2389-4b21-b3a2-bd75f663bf45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772852128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1772852128
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.553879917
Short name T516
Test name
Test status
Simulation time 48484027 ps
CPU time 0.61 seconds
Started Jul 22 04:40:33 PM PDT 24
Finished Jul 22 04:40:33 PM PDT 24
Peak memory 194288 kb
Host smart-d06f0a14-a7c9-4fa5-b8f0-0e588fff406c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553879917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.553879917
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2029029878
Short name T701
Test name
Test status
Simulation time 21010230 ps
CPU time 0.71 seconds
Started Jul 22 04:40:33 PM PDT 24
Finished Jul 22 04:40:34 PM PDT 24
Peak memory 194544 kb
Host smart-33aaa195-3455-4a9f-a79f-2ccf7d131e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029029878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2029029878
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3214840064
Short name T252
Test name
Test status
Simulation time 383722097 ps
CPU time 17.34 seconds
Started Jul 22 04:40:36 PM PDT 24
Finished Jul 22 04:40:53 PM PDT 24
Peak memory 197652 kb
Host smart-6c72951a-944f-403f-b1bb-367d08e80969
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214840064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3214840064
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2449756062
Short name T658
Test name
Test status
Simulation time 251283651 ps
CPU time 0.88 seconds
Started Jul 22 04:40:38 PM PDT 24
Finished Jul 22 04:40:39 PM PDT 24
Peak memory 196932 kb
Host smart-bd9e427c-4148-4d9a-93a3-7302109a1fe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449756062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2449756062
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4001413787
Short name T717
Test name
Test status
Simulation time 143709433 ps
CPU time 0.86 seconds
Started Jul 22 04:40:34 PM PDT 24
Finished Jul 22 04:40:36 PM PDT 24
Peak memory 196560 kb
Host smart-d84cd147-1743-43f4-8f8e-eb7f12dc56a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001413787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4001413787
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.240321494
Short name T676
Test name
Test status
Simulation time 128499342 ps
CPU time 2.6 seconds
Started Jul 22 04:40:36 PM PDT 24
Finished Jul 22 04:40:40 PM PDT 24
Peak memory 198412 kb
Host smart-c1c96220-82e6-4b0d-81cd-f8b106e4f378
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240321494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.240321494
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1726901432
Short name T578
Test name
Test status
Simulation time 431023485 ps
CPU time 2.64 seconds
Started Jul 22 04:40:38 PM PDT 24
Finished Jul 22 04:40:41 PM PDT 24
Peak memory 197900 kb
Host smart-41b8224b-640c-4ddc-9d23-3e0321b398a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726901432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1726901432
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3663789656
Short name T475
Test name
Test status
Simulation time 249797448 ps
CPU time 1.38 seconds
Started Jul 22 04:40:32 PM PDT 24
Finished Jul 22 04:40:34 PM PDT 24
Peak memory 198436 kb
Host smart-5654dba5-bbac-421d-a662-5a6eac3248a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663789656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3663789656
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4287649895
Short name T352
Test name
Test status
Simulation time 34454744 ps
CPU time 0.89 seconds
Started Jul 22 04:40:34 PM PDT 24
Finished Jul 22 04:40:36 PM PDT 24
Peak memory 197792 kb
Host smart-0c0e5bbe-dd07-40f7-bc75-aeb35d265865
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287649895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4287649895
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2204104011
Short name T4
Test name
Test status
Simulation time 420491632 ps
CPU time 5.4 seconds
Started Jul 22 04:40:35 PM PDT 24
Finished Jul 22 04:40:41 PM PDT 24
Peak memory 198420 kb
Host smart-768c18b2-853b-4d8b-8044-93926dd1be13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204104011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2204104011
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2321379345
Short name T518
Test name
Test status
Simulation time 282526302 ps
CPU time 1.45 seconds
Started Jul 22 04:41:08 PM PDT 24
Finished Jul 22 04:41:10 PM PDT 24
Peak memory 196760 kb
Host smart-76572723-3d66-4b0a-b70d-cd81f5a1f52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321379345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2321379345
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.451922891
Short name T380
Test name
Test status
Simulation time 154943438 ps
CPU time 0.99 seconds
Started Jul 22 04:40:36 PM PDT 24
Finished Jul 22 04:40:38 PM PDT 24
Peak memory 196784 kb
Host smart-f466c65f-b166-4efa-8702-4bf64562b00c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451922891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.451922891
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.14318813
Short name T243
Test name
Test status
Simulation time 15879774406 ps
CPU time 104.06 seconds
Started Jul 22 04:40:33 PM PDT 24
Finished Jul 22 04:42:18 PM PDT 24
Peak memory 198528 kb
Host smart-ea06910a-d224-4e12-a515-60fd3366fc2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14318813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gp
io_stress_all.14318813
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2590652033
Short name T192
Test name
Test status
Simulation time 14334525 ps
CPU time 0.59 seconds
Started Jul 22 04:40:43 PM PDT 24
Finished Jul 22 04:40:44 PM PDT 24
Peak memory 194616 kb
Host smart-8527a1c2-deff-43e7-8b89-530b0bfa0067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590652033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2590652033
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2802897265
Short name T173
Test name
Test status
Simulation time 53601891 ps
CPU time 0.64 seconds
Started Jul 22 04:40:34 PM PDT 24
Finished Jul 22 04:40:35 PM PDT 24
Peak memory 195124 kb
Host smart-9695bfc5-5ad6-4596-846f-1c8bf73b3496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802897265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2802897265
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2867160490
Short name T490
Test name
Test status
Simulation time 806764867 ps
CPU time 21.51 seconds
Started Jul 22 04:40:46 PM PDT 24
Finished Jul 22 04:41:07 PM PDT 24
Peak memory 197036 kb
Host smart-f12afa9c-78a2-40af-a3e9-2025a6f9f820
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867160490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2867160490
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3963288145
Short name T703
Test name
Test status
Simulation time 482045235 ps
CPU time 0.77 seconds
Started Jul 22 04:40:43 PM PDT 24
Finished Jul 22 04:40:44 PM PDT 24
Peak memory 196192 kb
Host smart-0af2958f-addf-46fb-a6c9-d653f7cad5cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963288145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3963288145
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1078937065
Short name T612
Test name
Test status
Simulation time 71740009 ps
CPU time 1.21 seconds
Started Jul 22 04:40:38 PM PDT 24
Finished Jul 22 04:40:39 PM PDT 24
Peak memory 196500 kb
Host smart-64591013-241a-44d2-a718-d4b34f951fae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078937065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1078937065
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3297068756
Short name T506
Test name
Test status
Simulation time 31851098 ps
CPU time 1.26 seconds
Started Jul 22 04:40:47 PM PDT 24
Finished Jul 22 04:40:49 PM PDT 24
Peak memory 198528 kb
Host smart-b8721ace-62f9-4bfa-b1dd-3cdc7500102d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297068756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3297068756
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.350957052
Short name T230
Test name
Test status
Simulation time 244067673 ps
CPU time 2.9 seconds
Started Jul 22 04:40:36 PM PDT 24
Finished Jul 22 04:40:39 PM PDT 24
Peak memory 196328 kb
Host smart-708fb529-5521-4217-809f-b7b8866c5a80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350957052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
350957052
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2778779576
Short name T236
Test name
Test status
Simulation time 24656161 ps
CPU time 0.83 seconds
Started Jul 22 04:40:32 PM PDT 24
Finished Jul 22 04:40:33 PM PDT 24
Peak memory 197772 kb
Host smart-ae2194e7-9565-4ee2-8888-0c052738e3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778779576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2778779576
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2082932648
Short name T204
Test name
Test status
Simulation time 56984032 ps
CPU time 1.2 seconds
Started Jul 22 04:40:33 PM PDT 24
Finished Jul 22 04:40:35 PM PDT 24
Peak memory 197392 kb
Host smart-e0e0824f-6ebd-4d65-9648-e85eba337dc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082932648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2082932648
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3270212305
Short name T436
Test name
Test status
Simulation time 469650395 ps
CPU time 4.17 seconds
Started Jul 22 04:40:42 PM PDT 24
Finished Jul 22 04:40:47 PM PDT 24
Peak memory 198412 kb
Host smart-19749c86-17aa-4177-999d-78da4dfda8a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270212305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3270212305
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1527047624
Short name T223
Test name
Test status
Simulation time 75935792 ps
CPU time 1.21 seconds
Started Jul 22 04:40:36 PM PDT 24
Finished Jul 22 04:40:38 PM PDT 24
Peak memory 197104 kb
Host smart-9c87eec0-0b98-4fb7-87f1-d3579fe4381b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527047624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1527047624
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3983535993
Short name T318
Test name
Test status
Simulation time 171214702 ps
CPU time 1.48 seconds
Started Jul 22 04:40:33 PM PDT 24
Finished Jul 22 04:40:35 PM PDT 24
Peak memory 195980 kb
Host smart-c45d3140-fea2-4e0f-bd42-2f62eba1f6d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983535993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3983535993
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4229145150
Short name T151
Test name
Test status
Simulation time 7948989651 ps
CPU time 58.51 seconds
Started Jul 22 04:40:44 PM PDT 24
Finished Jul 22 04:41:43 PM PDT 24
Peak memory 198540 kb
Host smart-0a828bad-440b-4bc2-a0e2-bd5da66cc53e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229145150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4229145150
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.790251536
Short name T64
Test name
Test status
Simulation time 219564014883 ps
CPU time 1363.4 seconds
Started Jul 22 04:40:45 PM PDT 24
Finished Jul 22 05:03:29 PM PDT 24
Peak memory 198692 kb
Host smart-052582dd-16b3-4804-8713-e487561aeca1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=790251536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.790251536
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3134504068
Short name T66
Test name
Test status
Simulation time 40987896 ps
CPU time 0.51 seconds
Started Jul 22 04:42:15 PM PDT 24
Finished Jul 22 04:42:16 PM PDT 24
Peak memory 194220 kb
Host smart-40040703-6627-40ce-b5e4-e27ea4680516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134504068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3134504068
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.442599664
Short name T353
Test name
Test status
Simulation time 50427040 ps
CPU time 0.76 seconds
Started Jul 22 04:40:42 PM PDT 24
Finished Jul 22 04:40:43 PM PDT 24
Peak memory 195632 kb
Host smart-a76fa61b-b3fc-4fd7-8edd-fe0c8909f51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442599664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.442599664
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3666793222
Short name T20
Test name
Test status
Simulation time 1462656465 ps
CPU time 20.48 seconds
Started Jul 22 04:40:42 PM PDT 24
Finished Jul 22 04:41:03 PM PDT 24
Peak memory 197320 kb
Host smart-7a52a6e9-3b49-4772-9b84-e11dcade0094
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666793222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3666793222
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1024997152
Short name T563
Test name
Test status
Simulation time 55638326 ps
CPU time 0.72 seconds
Started Jul 22 04:40:47 PM PDT 24
Finished Jul 22 04:40:49 PM PDT 24
Peak memory 196272 kb
Host smart-426da3bd-eac4-433e-afa4-6c8d4361b1a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024997152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1024997152
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2305780956
Short name T275
Test name
Test status
Simulation time 139685584 ps
CPU time 0.92 seconds
Started Jul 22 04:40:42 PM PDT 24
Finished Jul 22 04:40:44 PM PDT 24
Peak memory 197108 kb
Host smart-8df81dc7-35f9-455d-83c2-a52746261bc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305780956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2305780956
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.32399833
Short name T449
Test name
Test status
Simulation time 106891579 ps
CPU time 1.17 seconds
Started Jul 22 04:40:45 PM PDT 24
Finished Jul 22 04:40:47 PM PDT 24
Peak memory 198228 kb
Host smart-850d3a74-39a4-425d-989a-7281915b0da4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32399833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.gpio_intr_with_filter_rand_intr_event.32399833
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3361695300
Short name T500
Test name
Test status
Simulation time 150427991 ps
CPU time 2.07 seconds
Started Jul 22 04:42:15 PM PDT 24
Finished Jul 22 04:42:17 PM PDT 24
Peak memory 197180 kb
Host smart-1a2abff8-cefe-4dfe-b728-97609794272c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361695300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3361695300
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1733123612
Short name T244
Test name
Test status
Simulation time 19875629 ps
CPU time 0.75 seconds
Started Jul 22 04:40:44 PM PDT 24
Finished Jul 22 04:40:46 PM PDT 24
Peak memory 195416 kb
Host smart-a04e43e1-9bb8-40af-992f-ebb2846126a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733123612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1733123612
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3650651186
Short name T251
Test name
Test status
Simulation time 34979876 ps
CPU time 1.11 seconds
Started Jul 22 04:40:42 PM PDT 24
Finished Jul 22 04:40:43 PM PDT 24
Peak memory 196216 kb
Host smart-10031fe5-7883-4d4a-bb3a-67fae274bd82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650651186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3650651186
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2222307071
Short name T579
Test name
Test status
Simulation time 546647719 ps
CPU time 1.43 seconds
Started Jul 22 04:40:42 PM PDT 24
Finished Jul 22 04:40:44 PM PDT 24
Peak memory 198392 kb
Host smart-df2aef74-2048-4500-9250-ca87efef7821
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222307071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2222307071
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.88873026
Short name T673
Test name
Test status
Simulation time 166315868 ps
CPU time 1 seconds
Started Jul 22 04:40:47 PM PDT 24
Finished Jul 22 04:40:49 PM PDT 24
Peak memory 196952 kb
Host smart-427c83af-2718-49c2-9446-d2041a5df875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88873026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.88873026
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3793985690
Short name T429
Test name
Test status
Simulation time 107451097 ps
CPU time 1.16 seconds
Started Jul 22 04:40:43 PM PDT 24
Finished Jul 22 04:40:45 PM PDT 24
Peak memory 197032 kb
Host smart-742df507-969a-4e57-bef8-fc9d4ab800fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793985690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3793985690
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3434264267
Short name T671
Test name
Test status
Simulation time 49455787121 ps
CPU time 174.58 seconds
Started Jul 22 04:40:42 PM PDT 24
Finished Jul 22 04:43:38 PM PDT 24
Peak memory 198552 kb
Host smart-206786e8-feb7-43b1-be7c-097d1e83941c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434264267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3434264267
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1338455835
Short name T169
Test name
Test status
Simulation time 40635889 ps
CPU time 0.56 seconds
Started Jul 22 04:40:55 PM PDT 24
Finished Jul 22 04:40:56 PM PDT 24
Peak memory 194972 kb
Host smart-8a43e6b0-d710-4a4a-b620-91c65ccf1ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338455835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1338455835
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.153352478
Short name T250
Test name
Test status
Simulation time 29117733 ps
CPU time 0.72 seconds
Started Jul 22 04:40:58 PM PDT 24
Finished Jul 22 04:41:00 PM PDT 24
Peak memory 194552 kb
Host smart-9d7b6893-a791-4753-99ec-f7c203b96764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153352478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.153352478
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2035982936
Short name T615
Test name
Test status
Simulation time 497126216 ps
CPU time 17.05 seconds
Started Jul 22 04:40:55 PM PDT 24
Finished Jul 22 04:41:13 PM PDT 24
Peak memory 198400 kb
Host smart-223c2ee3-f51d-4347-a9c3-3fef24d35c1a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035982936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2035982936
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1807456758
Short name T286
Test name
Test status
Simulation time 210558327 ps
CPU time 1.03 seconds
Started Jul 22 04:40:56 PM PDT 24
Finished Jul 22 04:40:58 PM PDT 24
Peak memory 197072 kb
Host smart-c69be608-f65b-408d-aece-bf1288fec9c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807456758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1807456758
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3893998174
Short name T62
Test name
Test status
Simulation time 67631963 ps
CPU time 0.87 seconds
Started Jul 22 04:40:55 PM PDT 24
Finished Jul 22 04:40:57 PM PDT 24
Peak memory 196112 kb
Host smart-21868ba9-739e-4f08-96e8-6db60608d415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893998174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3893998174
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2122090886
Short name T623
Test name
Test status
Simulation time 355342631 ps
CPU time 3.87 seconds
Started Jul 22 04:40:56 PM PDT 24
Finished Jul 22 04:41:01 PM PDT 24
Peak memory 198544 kb
Host smart-ce368b3d-5808-4e24-9183-cb321f7eb9ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122090886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2122090886
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.653847938
Short name T15
Test name
Test status
Simulation time 117481627 ps
CPU time 1.05 seconds
Started Jul 22 04:41:03 PM PDT 24
Finished Jul 22 04:41:04 PM PDT 24
Peak memory 195920 kb
Host smart-7470ab81-02c7-48a3-8b03-90715f4c0458
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653847938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
653847938
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3149821688
Short name T533
Test name
Test status
Simulation time 159258408 ps
CPU time 1.08 seconds
Started Jul 22 04:40:56 PM PDT 24
Finished Jul 22 04:40:58 PM PDT 24
Peak memory 196248 kb
Host smart-5189c8bf-0e7f-4a4c-9637-6f5355ce72f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149821688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3149821688
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3799891
Short name T638
Test name
Test status
Simulation time 191321721 ps
CPU time 1.18 seconds
Started Jul 22 04:40:55 PM PDT 24
Finished Jul 22 04:40:57 PM PDT 24
Peak memory 196432 kb
Host smart-f6caeb8c-f1d4-448f-a795-228cbc11c0bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup_p
ulldown.3799891
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1933643885
Short name T95
Test name
Test status
Simulation time 1396490868 ps
CPU time 5.14 seconds
Started Jul 22 04:41:01 PM PDT 24
Finished Jul 22 04:41:07 PM PDT 24
Peak memory 198352 kb
Host smart-134133e7-e7c7-490b-afd1-a9b534b44db4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933643885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1933643885
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3108052341
Short name T390
Test name
Test status
Simulation time 50285738 ps
CPU time 1.08 seconds
Started Jul 22 04:40:47 PM PDT 24
Finished Jul 22 04:40:49 PM PDT 24
Peak memory 196732 kb
Host smart-4a9b0fee-5809-4245-a2c6-bfd84a1ceaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108052341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3108052341
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2305019359
Short name T439
Test name
Test status
Simulation time 145362609 ps
CPU time 0.82 seconds
Started Jul 22 04:40:56 PM PDT 24
Finished Jul 22 04:40:58 PM PDT 24
Peak memory 196492 kb
Host smart-ad2344be-776b-49d6-b7db-42c55f7219ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305019359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2305019359
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.4163934123
Short name T274
Test name
Test status
Simulation time 60132257872 ps
CPU time 81.39 seconds
Started Jul 22 04:40:56 PM PDT 24
Finished Jul 22 04:42:18 PM PDT 24
Peak memory 198440 kb
Host smart-26364d85-6106-488c-9ea4-17a7749ac7d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163934123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.4163934123
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.445334415
Short name T504
Test name
Test status
Simulation time 71658004 ps
CPU time 0.59 seconds
Started Jul 22 04:42:02 PM PDT 24
Finished Jul 22 04:42:04 PM PDT 24
Peak memory 194056 kb
Host smart-3a755846-0e1d-410d-8d62-4270cdf0a2e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445334415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.445334415
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1847008456
Short name T413
Test name
Test status
Simulation time 39576251 ps
CPU time 0.9 seconds
Started Jul 22 04:40:55 PM PDT 24
Finished Jul 22 04:40:56 PM PDT 24
Peak memory 197652 kb
Host smart-8aca4bf4-3fb1-4e35-8fc0-4af36cc7dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847008456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1847008456
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3988251000
Short name T93
Test name
Test status
Simulation time 1902544287 ps
CPU time 23.64 seconds
Started Jul 22 04:42:12 PM PDT 24
Finished Jul 22 04:42:36 PM PDT 24
Peak memory 198440 kb
Host smart-8ed2f105-13e6-4ce9-8a01-39cff4eaf700
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988251000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3988251000
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3237310443
Short name T221
Test name
Test status
Simulation time 225173294 ps
CPU time 0.78 seconds
Started Jul 22 04:42:07 PM PDT 24
Finished Jul 22 04:42:09 PM PDT 24
Peak memory 196908 kb
Host smart-0154b17b-6a9e-429a-b9d5-3484c299d20d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237310443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3237310443
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2057267731
Short name T501
Test name
Test status
Simulation time 47415588 ps
CPU time 1.24 seconds
Started Jul 22 04:41:06 PM PDT 24
Finished Jul 22 04:41:08 PM PDT 24
Peak memory 197484 kb
Host smart-4fcacc81-883e-45b2-af2c-f059b9ff662e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057267731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2057267731
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3244355078
Short name T63
Test name
Test status
Simulation time 106295939 ps
CPU time 2.4 seconds
Started Jul 22 04:41:05 PM PDT 24
Finished Jul 22 04:41:08 PM PDT 24
Peak memory 196932 kb
Host smart-10d35068-d317-42a1-b34b-c20036a81c36
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244355078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3244355078
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.4045822167
Short name T245
Test name
Test status
Simulation time 418976100 ps
CPU time 2.14 seconds
Started Jul 22 04:41:17 PM PDT 24
Finished Jul 22 04:41:20 PM PDT 24
Peak memory 196936 kb
Host smart-80788aec-9088-4dd7-ae72-57d4aa0fd0fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045822167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.4045822167
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3005009827
Short name T180
Test name
Test status
Simulation time 26683892 ps
CPU time 0.87 seconds
Started Jul 22 04:40:55 PM PDT 24
Finished Jul 22 04:40:57 PM PDT 24
Peak memory 196584 kb
Host smart-5d705674-5b9e-471c-9155-202140b97eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005009827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3005009827
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4099058649
Short name T462
Test name
Test status
Simulation time 182536295 ps
CPU time 1.08 seconds
Started Jul 22 04:41:46 PM PDT 24
Finished Jul 22 04:41:47 PM PDT 24
Peak memory 196296 kb
Host smart-8d449b43-f966-47c8-9cf7-6b189522a4a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099058649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4099058649
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3353761919
Short name T586
Test name
Test status
Simulation time 454397636 ps
CPU time 5.36 seconds
Started Jul 22 04:41:04 PM PDT 24
Finished Jul 22 04:41:10 PM PDT 24
Peak memory 198096 kb
Host smart-5b28f498-d56f-4d23-b889-cfb11e84a084
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353761919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3353761919
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.583050054
Short name T478
Test name
Test status
Simulation time 32871091 ps
CPU time 0.98 seconds
Started Jul 22 04:40:56 PM PDT 24
Finished Jul 22 04:40:58 PM PDT 24
Peak memory 196184 kb
Host smart-c810a9ed-2266-4d7e-b9dd-f7c0d2681d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583050054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.583050054
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2487497293
Short name T580
Test name
Test status
Simulation time 112596759 ps
CPU time 1.23 seconds
Started Jul 22 04:40:55 PM PDT 24
Finished Jul 22 04:40:57 PM PDT 24
Peak memory 196264 kb
Host smart-37f9b460-9967-4a25-a824-4f2bf99718f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487497293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2487497293
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4278595772
Short name T16
Test name
Test status
Simulation time 11384802108 ps
CPU time 152.15 seconds
Started Jul 22 04:41:06 PM PDT 24
Finished Jul 22 04:43:39 PM PDT 24
Peak memory 198568 kb
Host smart-a7ce31d6-f677-47a6-9b99-5df3066bafc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278595772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4278595772
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.2215924130
Short name T310
Test name
Test status
Simulation time 129563329134 ps
CPU time 667.72 seconds
Started Jul 22 04:41:05 PM PDT 24
Finished Jul 22 04:52:13 PM PDT 24
Peak memory 198680 kb
Host smart-f658e3e4-1f92-4c00-b367-63571e1ed3d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2215924130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.2215924130
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2068848796
Short name T124
Test name
Test status
Simulation time 12586566 ps
CPU time 0.58 seconds
Started Jul 22 04:41:07 PM PDT 24
Finished Jul 22 04:41:08 PM PDT 24
Peak memory 195012 kb
Host smart-cb5038de-b71c-4ec5-be80-c479803434ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068848796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2068848796
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.480427849
Short name T437
Test name
Test status
Simulation time 41510555 ps
CPU time 0.74 seconds
Started Jul 22 04:41:05 PM PDT 24
Finished Jul 22 04:41:06 PM PDT 24
Peak memory 196520 kb
Host smart-8d8c2123-f3ae-40d2-ab9e-bc16a74f7330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480427849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.480427849
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2501712674
Short name T448
Test name
Test status
Simulation time 341693022 ps
CPU time 6.5 seconds
Started Jul 22 04:41:05 PM PDT 24
Finished Jul 22 04:41:12 PM PDT 24
Peak memory 197352 kb
Host smart-d19f3806-1bd1-4b95-aaa7-d5a7dacaa700
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501712674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2501712674
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3380977653
Short name T443
Test name
Test status
Simulation time 187759913 ps
CPU time 0.83 seconds
Started Jul 22 04:41:06 PM PDT 24
Finished Jul 22 04:41:08 PM PDT 24
Peak memory 196440 kb
Host smart-26be6a26-ddee-402c-92b9-c3d1e8cd9f11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380977653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3380977653
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.680946294
Short name T246
Test name
Test status
Simulation time 263455271 ps
CPU time 1.12 seconds
Started Jul 22 04:41:05 PM PDT 24
Finished Jul 22 04:41:07 PM PDT 24
Peak memory 196172 kb
Host smart-c435c607-9b0c-4658-ac93-0a6231f66ee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680946294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.680946294
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.250450392
Short name T609
Test name
Test status
Simulation time 222870597 ps
CPU time 2.47 seconds
Started Jul 22 04:41:08 PM PDT 24
Finished Jul 22 04:41:11 PM PDT 24
Peak memory 198588 kb
Host smart-b9ceeb18-6949-46c6-ac37-43ce17449713
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250450392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.250450392
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3185733137
Short name T317
Test name
Test status
Simulation time 229061385 ps
CPU time 3.22 seconds
Started Jul 22 04:41:08 PM PDT 24
Finished Jul 22 04:41:12 PM PDT 24
Peak memory 197292 kb
Host smart-fcd91e87-9486-48a4-a38a-c28e42e2b8bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185733137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3185733137
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2361662120
Short name T549
Test name
Test status
Simulation time 273753291 ps
CPU time 1.05 seconds
Started Jul 22 04:41:12 PM PDT 24
Finished Jul 22 04:41:13 PM PDT 24
Peak memory 196540 kb
Host smart-46f83d9e-d3fb-42df-8b05-611e77302be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361662120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2361662120
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3547358353
Short name T128
Test name
Test status
Simulation time 39950586 ps
CPU time 1.05 seconds
Started Jul 22 04:41:06 PM PDT 24
Finished Jul 22 04:41:08 PM PDT 24
Peak memory 196428 kb
Host smart-1d9a22b4-6889-48d4-9577-e72fc301672d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547358353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3547358353
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.493425485
Short name T628
Test name
Test status
Simulation time 466408746 ps
CPU time 4.43 seconds
Started Jul 22 04:42:13 PM PDT 24
Finished Jul 22 04:42:18 PM PDT 24
Peak memory 198340 kb
Host smart-88bbe42a-4522-45ca-ac9b-1f0f4e399ffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493425485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.493425485
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2532140078
Short name T654
Test name
Test status
Simulation time 45471399 ps
CPU time 1.24 seconds
Started Jul 22 04:41:06 PM PDT 24
Finished Jul 22 04:41:08 PM PDT 24
Peak memory 196876 kb
Host smart-8b78f364-611a-421f-b9a9-c3da712aa827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532140078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2532140078
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1712419310
Short name T315
Test name
Test status
Simulation time 76231836 ps
CPU time 0.88 seconds
Started Jul 22 04:41:08 PM PDT 24
Finished Jul 22 04:41:09 PM PDT 24
Peak memory 196648 kb
Host smart-2967fbb3-f4ae-4390-a8b7-a603f08482ed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712419310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1712419310
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2621076979
Short name T718
Test name
Test status
Simulation time 106469897178 ps
CPU time 102.09 seconds
Started Jul 22 04:41:55 PM PDT 24
Finished Jul 22 04:43:38 PM PDT 24
Peak memory 198592 kb
Host smart-af50f0e2-4f58-43ff-ba19-514be9b4f00d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621076979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2621076979
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.4099007710
Short name T376
Test name
Test status
Simulation time 99650341 ps
CPU time 0.55 seconds
Started Jul 22 04:41:18 PM PDT 24
Finished Jul 22 04:41:19 PM PDT 24
Peak memory 195020 kb
Host smart-7e30bd11-ed0d-4dcd-9673-68dd06009fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099007710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.4099007710
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1313463103
Short name T619
Test name
Test status
Simulation time 339854263 ps
CPU time 0.81 seconds
Started Jul 22 04:41:06 PM PDT 24
Finished Jul 22 04:41:07 PM PDT 24
Peak memory 196480 kb
Host smart-d59287eb-f57c-48e5-98fc-cbbe44ae3530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313463103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1313463103
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1784496490
Short name T527
Test name
Test status
Simulation time 363843096 ps
CPU time 20.11 seconds
Started Jul 22 04:41:07 PM PDT 24
Finished Jul 22 04:41:28 PM PDT 24
Peak memory 198408 kb
Host smart-33fe1260-1422-4a37-b7e3-f5051892cdc2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784496490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1784496490
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.2329072633
Short name T564
Test name
Test status
Simulation time 190191954 ps
CPU time 0.91 seconds
Started Jul 22 04:42:56 PM PDT 24
Finished Jul 22 04:42:57 PM PDT 24
Peak memory 197344 kb
Host smart-a18c4fbc-5b1f-455b-97f3-d8d06c487832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329072633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.2329072633
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1549261659
Short name T665
Test name
Test status
Simulation time 54453080 ps
CPU time 0.63 seconds
Started Jul 22 04:41:17 PM PDT 24
Finished Jul 22 04:41:19 PM PDT 24
Peak memory 195372 kb
Host smart-c20a9060-1639-4cf4-a9b5-844a1054b125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549261659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1549261659
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3031970299
Short name T601
Test name
Test status
Simulation time 188461332 ps
CPU time 3.54 seconds
Started Jul 22 04:41:12 PM PDT 24
Finished Jul 22 04:41:16 PM PDT 24
Peak memory 198612 kb
Host smart-01fb1403-d5a6-4d68-aa0b-67e4eabe5abd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031970299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3031970299
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3718170802
Short name T674
Test name
Test status
Simulation time 81838526 ps
CPU time 1.04 seconds
Started Jul 22 04:41:12 PM PDT 24
Finished Jul 22 04:41:13 PM PDT 24
Peak memory 196104 kb
Host smart-d41c2915-8edc-4fb2-ba52-26932e7dccad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718170802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3718170802
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2581418159
Short name T502
Test name
Test status
Simulation time 120140851 ps
CPU time 1.23 seconds
Started Jul 22 04:41:06 PM PDT 24
Finished Jul 22 04:41:08 PM PDT 24
Peak memory 196568 kb
Host smart-9f585aed-80fc-45cf-b980-f5c5b2678e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581418159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2581418159
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1779632916
Short name T139
Test name
Test status
Simulation time 75869897 ps
CPU time 0.99 seconds
Started Jul 22 04:41:13 PM PDT 24
Finished Jul 22 04:41:15 PM PDT 24
Peak memory 197044 kb
Host smart-b45f4b6f-1117-48fb-808e-c9a5749315ec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779632916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1779632916
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.4276002132
Short name T403
Test name
Test status
Simulation time 55597672 ps
CPU time 1.14 seconds
Started Jul 22 04:41:08 PM PDT 24
Finished Jul 22 04:41:10 PM PDT 24
Peak memory 198456 kb
Host smart-c8fd00d8-f36b-4bfa-9f65-4b24f3d300d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276002132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.4276002132
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2383750882
Short name T258
Test name
Test status
Simulation time 72848922 ps
CPU time 1.25 seconds
Started Jul 22 04:41:12 PM PDT 24
Finished Jul 22 04:41:14 PM PDT 24
Peak memory 197328 kb
Host smart-379e4463-a86e-4232-8ae2-be1a5d0a6bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383750882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2383750882
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1755636730
Short name T65
Test name
Test status
Simulation time 54985289 ps
CPU time 1.03 seconds
Started Jul 22 04:41:06 PM PDT 24
Finished Jul 22 04:41:08 PM PDT 24
Peak memory 197344 kb
Host smart-d6867dbb-424e-4177-9ab9-9839d0627558
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755636730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1755636730
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1856817367
Short name T474
Test name
Test status
Simulation time 4434192808 ps
CPU time 29.23 seconds
Started Jul 22 04:41:17 PM PDT 24
Finished Jul 22 04:41:47 PM PDT 24
Peak memory 198496 kb
Host smart-f046e39c-f563-4188-af16-ccf8de4d0fd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856817367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1856817367
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1793045403
Short name T23
Test name
Test status
Simulation time 137254272872 ps
CPU time 1158.76 seconds
Started Jul 22 04:41:14 PM PDT 24
Finished Jul 22 05:00:34 PM PDT 24
Peak memory 198628 kb
Host smart-3939c40a-02ec-49cb-99a3-68eb404f6bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1793045403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1793045403
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1475666857
Short name T576
Test name
Test status
Simulation time 14886240 ps
CPU time 0.59 seconds
Started Jul 22 04:41:15 PM PDT 24
Finished Jul 22 04:41:17 PM PDT 24
Peak memory 195408 kb
Host smart-325cb8ef-4ed7-4827-a132-9e7f4ddd8368
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475666857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1475666857
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.753165935
Short name T345
Test name
Test status
Simulation time 55249382 ps
CPU time 0.97 seconds
Started Jul 22 04:41:14 PM PDT 24
Finished Jul 22 04:41:15 PM PDT 24
Peak memory 196316 kb
Host smart-fe759534-9d4f-4673-a92e-0ed4e02efc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753165935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.753165935
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.906907157
Short name T700
Test name
Test status
Simulation time 694538220 ps
CPU time 18.11 seconds
Started Jul 22 04:41:16 PM PDT 24
Finished Jul 22 04:41:34 PM PDT 24
Peak memory 197228 kb
Host smart-36a29555-4c40-4b1b-842b-a2b391dbde15
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906907157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stres
s.906907157
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1739369901
Short name T458
Test name
Test status
Simulation time 220718478 ps
CPU time 0.94 seconds
Started Jul 22 04:41:51 PM PDT 24
Finished Jul 22 04:41:52 PM PDT 24
Peak memory 198304 kb
Host smart-ad347617-413e-40cc-b324-42b59a4d3eca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739369901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1739369901
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2206633683
Short name T681
Test name
Test status
Simulation time 196241007 ps
CPU time 0.83 seconds
Started Jul 22 04:41:52 PM PDT 24
Finished Jul 22 04:41:53 PM PDT 24
Peak memory 195964 kb
Host smart-115a5e81-f287-44e6-86e5-8e5c498a89bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206633683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2206633683
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3817605209
Short name T375
Test name
Test status
Simulation time 67853221 ps
CPU time 1.12 seconds
Started Jul 22 04:42:44 PM PDT 24
Finished Jul 22 04:42:45 PM PDT 24
Peak memory 197380 kb
Host smart-c7ccbb8a-09e1-4d1e-a833-7465bed1d05d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817605209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3817605209
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2442525242
Short name T194
Test name
Test status
Simulation time 311946833 ps
CPU time 1.74 seconds
Started Jul 22 04:41:13 PM PDT 24
Finished Jul 22 04:41:16 PM PDT 24
Peak memory 196424 kb
Host smart-45a0b789-3110-457f-ba13-6fa7afd6b92e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442525242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2442525242
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1593157062
Short name T219
Test name
Test status
Simulation time 94488076 ps
CPU time 0.8 seconds
Started Jul 22 04:41:40 PM PDT 24
Finished Jul 22 04:41:41 PM PDT 24
Peak memory 195896 kb
Host smart-aefe6595-8b81-4096-8661-574fbd4cd93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593157062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1593157062
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3323789430
Short name T547
Test name
Test status
Simulation time 38631220 ps
CPU time 1 seconds
Started Jul 22 04:41:16 PM PDT 24
Finished Jul 22 04:41:18 PM PDT 24
Peak memory 196376 kb
Host smart-9c81eec1-8357-4090-8c81-03db1d2bad9e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323789430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3323789430
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3036284150
Short name T203
Test name
Test status
Simulation time 84700896 ps
CPU time 2.09 seconds
Started Jul 22 04:41:14 PM PDT 24
Finished Jul 22 04:41:16 PM PDT 24
Peak memory 198344 kb
Host smart-6a8cdecb-5c0e-4635-b708-6eab8c7e7ff6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036284150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3036284150
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3815836328
Short name T188
Test name
Test status
Simulation time 38937012 ps
CPU time 0.68 seconds
Started Jul 22 04:41:16 PM PDT 24
Finished Jul 22 04:41:17 PM PDT 24
Peak memory 195188 kb
Host smart-81128a88-375a-46de-8b72-e2159fe57b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815836328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3815836328
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1965482614
Short name T269
Test name
Test status
Simulation time 62593004 ps
CPU time 1.08 seconds
Started Jul 22 04:41:14 PM PDT 24
Finished Jul 22 04:41:16 PM PDT 24
Peak memory 196884 kb
Host smart-f86de62e-ce41-4ad5-abf0-89805ab04a69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965482614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1965482614
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.2918646935
Short name T631
Test name
Test status
Simulation time 14711718498 ps
CPU time 165.86 seconds
Started Jul 22 04:41:15 PM PDT 24
Finished Jul 22 04:44:01 PM PDT 24
Peak memory 198480 kb
Host smart-19a93d3d-3533-4848-bc91-43c5418aac72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918646935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.2918646935
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1911297074
Short name T304
Test name
Test status
Simulation time 37878611 ps
CPU time 0.57 seconds
Started Jul 22 04:41:16 PM PDT 24
Finished Jul 22 04:41:18 PM PDT 24
Peak memory 194324 kb
Host smart-842f86df-4f6c-4344-a5de-6a92ccd9c3f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911297074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1911297074
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3687365268
Short name T606
Test name
Test status
Simulation time 25446571 ps
CPU time 0.79 seconds
Started Jul 22 04:42:56 PM PDT 24
Finished Jul 22 04:42:57 PM PDT 24
Peak memory 194344 kb
Host smart-cbc61b08-7903-4b14-82d2-848cf3ddc7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687365268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3687365268
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3651506220
Short name T329
Test name
Test status
Simulation time 5161626931 ps
CPU time 23.51 seconds
Started Jul 22 04:41:13 PM PDT 24
Finished Jul 22 04:41:36 PM PDT 24
Peak memory 198596 kb
Host smart-54dec789-ab6f-4f0c-9d2b-b6de08b0ab35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651506220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3651506220
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3144539210
Short name T130
Test name
Test status
Simulation time 72413895 ps
CPU time 0.76 seconds
Started Jul 22 04:41:16 PM PDT 24
Finished Jul 22 04:41:18 PM PDT 24
Peak memory 195192 kb
Host smart-577e70eb-422e-41d6-90dc-9bc8c2093b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144539210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3144539210
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.126237546
Short name T242
Test name
Test status
Simulation time 103493737 ps
CPU time 1.52 seconds
Started Jul 22 04:41:17 PM PDT 24
Finished Jul 22 04:41:19 PM PDT 24
Peak memory 197448 kb
Host smart-375b9fa9-c5e4-463f-99bb-f4332a5634e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126237546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.126237546
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2358414706
Short name T640
Test name
Test status
Simulation time 181939595 ps
CPU time 1.75 seconds
Started Jul 22 04:41:16 PM PDT 24
Finished Jul 22 04:41:18 PM PDT 24
Peak memory 197128 kb
Host smart-12c7ac61-78a2-4a0c-823d-c2c0fa6b8411
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358414706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2358414706
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.289983688
Short name T417
Test name
Test status
Simulation time 350164432 ps
CPU time 2.81 seconds
Started Jul 22 04:41:13 PM PDT 24
Finished Jul 22 04:41:17 PM PDT 24
Peak memory 198444 kb
Host smart-acc14597-2427-4a35-9e75-6c6ef3f20f2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289983688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
289983688
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.563040165
Short name T336
Test name
Test status
Simulation time 22483913 ps
CPU time 0.92 seconds
Started Jul 22 04:41:14 PM PDT 24
Finished Jul 22 04:41:16 PM PDT 24
Peak memory 196412 kb
Host smart-321a4c5c-469e-4283-96a6-f8083fd87f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563040165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.563040165
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3659372762
Short name T388
Test name
Test status
Simulation time 69412486 ps
CPU time 0.96 seconds
Started Jul 22 04:41:14 PM PDT 24
Finished Jul 22 04:41:16 PM PDT 24
Peak memory 197116 kb
Host smart-6932ec11-9327-44e1-b898-e36217ee4632
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659372762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3659372762
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2950978668
Short name T651
Test name
Test status
Simulation time 81914441 ps
CPU time 3.74 seconds
Started Jul 22 04:41:15 PM PDT 24
Finished Jul 22 04:41:19 PM PDT 24
Peak memory 198392 kb
Host smart-c3e3fd7a-74bd-48dc-ba38-3474bfe5054f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950978668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2950978668
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3571392109
Short name T141
Test name
Test status
Simulation time 77567262 ps
CPU time 1.14 seconds
Started Jul 22 04:42:56 PM PDT 24
Finished Jul 22 04:42:58 PM PDT 24
Peak memory 196668 kb
Host smart-9cffb9f4-9578-48a3-af56-8b1e80953043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571392109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3571392109
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.4091969248
Short name T148
Test name
Test status
Simulation time 104548748 ps
CPU time 1.26 seconds
Started Jul 22 04:41:17 PM PDT 24
Finished Jul 22 04:41:19 PM PDT 24
Peak memory 196656 kb
Host smart-1a768e3c-86ea-4896-9e6e-d59e7c45547d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091969248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.4091969248
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.666212866
Short name T425
Test name
Test status
Simulation time 2661025828 ps
CPU time 37.77 seconds
Started Jul 22 04:41:16 PM PDT 24
Finished Jul 22 04:41:55 PM PDT 24
Peak memory 198572 kb
Host smart-f1ea7e09-21ef-494e-837f-7dc987e8949a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666212866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.666212866
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.986583543
Short name T714
Test name
Test status
Simulation time 117066517 ps
CPU time 0.6 seconds
Started Jul 22 04:38:02 PM PDT 24
Finished Jul 22 04:38:03 PM PDT 24
Peak memory 194340 kb
Host smart-9358c941-58fd-4db6-8f74-0efd88b260c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986583543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.986583543
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3506540971
Short name T534
Test name
Test status
Simulation time 54265801 ps
CPU time 1.01 seconds
Started Jul 22 04:38:02 PM PDT 24
Finished Jul 22 04:38:03 PM PDT 24
Peak memory 196500 kb
Host smart-701a675a-61be-4c6d-8023-f4907b499f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506540971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3506540971
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.654121432
Short name T434
Test name
Test status
Simulation time 445221960 ps
CPU time 3.45 seconds
Started Jul 22 04:38:04 PM PDT 24
Finished Jul 22 04:38:08 PM PDT 24
Peak memory 196344 kb
Host smart-43d2c81c-3b09-4d3e-9fb4-43505b8fc64b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654121432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.654121432
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.608658198
Short name T71
Test name
Test status
Simulation time 249256450 ps
CPU time 0.76 seconds
Started Jul 22 04:38:03 PM PDT 24
Finished Jul 22 04:38:04 PM PDT 24
Peak memory 195864 kb
Host smart-de1d6cb0-4694-4fd1-afb3-616175ca1d43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608658198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.608658198
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3808427858
Short name T309
Test name
Test status
Simulation time 648731969 ps
CPU time 0.9 seconds
Started Jul 22 04:38:00 PM PDT 24
Finished Jul 22 04:38:02 PM PDT 24
Peak memory 196432 kb
Host smart-5670932a-efcf-4d32-a525-5046794c7918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808427858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3808427858
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2441410197
Short name T341
Test name
Test status
Simulation time 92424638 ps
CPU time 3.81 seconds
Started Jul 22 04:38:01 PM PDT 24
Finished Jul 22 04:38:05 PM PDT 24
Peak memory 198428 kb
Host smart-2ba93899-5277-432e-9617-0bac123f939f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441410197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2441410197
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2505376933
Short name T13
Test name
Test status
Simulation time 73928668 ps
CPU time 1.76 seconds
Started Jul 22 04:38:01 PM PDT 24
Finished Jul 22 04:38:04 PM PDT 24
Peak memory 196192 kb
Host smart-721665f2-63b8-4394-bbb9-10256efc7e31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505376933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2505376933
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3140735775
Short name T463
Test name
Test status
Simulation time 39951310 ps
CPU time 1.04 seconds
Started Jul 22 04:37:50 PM PDT 24
Finished Jul 22 04:37:52 PM PDT 24
Peak memory 196236 kb
Host smart-73d46bdf-45c2-4e2e-8ac9-7b44db72a9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140735775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3140735775
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.328530707
Short name T127
Test name
Test status
Simulation time 56703014 ps
CPU time 1.13 seconds
Started Jul 22 04:37:52 PM PDT 24
Finished Jul 22 04:37:53 PM PDT 24
Peak memory 196316 kb
Host smart-2bf7dfcb-ae6a-439d-ba09-0b765775f748
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328530707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.328530707
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3278123350
Short name T255
Test name
Test status
Simulation time 96265436 ps
CPU time 4.38 seconds
Started Jul 22 04:38:01 PM PDT 24
Finished Jul 22 04:38:06 PM PDT 24
Peak memory 198368 kb
Host smart-70d83982-f912-4383-b17f-6f867189731f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278123350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3278123350
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3178650572
Short name T32
Test name
Test status
Simulation time 482285822 ps
CPU time 1 seconds
Started Jul 22 04:38:01 PM PDT 24
Finished Jul 22 04:38:02 PM PDT 24
Peak memory 215476 kb
Host smart-9cb9ccf5-b4d7-44f5-adad-d6c4f8e1adfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178650572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3178650572
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3739333306
Short name T155
Test name
Test status
Simulation time 82672150 ps
CPU time 1.47 seconds
Started Jul 22 04:37:51 PM PDT 24
Finished Jul 22 04:37:53 PM PDT 24
Peak memory 195940 kb
Host smart-43fccb8f-864d-4fd8-9432-afe3b56a1b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739333306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3739333306
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3829354233
Short name T325
Test name
Test status
Simulation time 61073037 ps
CPU time 0.94 seconds
Started Jul 22 04:37:52 PM PDT 24
Finished Jul 22 04:37:54 PM PDT 24
Peak memory 195948 kb
Host smart-642b7232-b1aa-48fb-a763-b7c91830b9eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829354233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3829354233
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3117232833
Short name T442
Test name
Test status
Simulation time 13164466062 ps
CPU time 95.24 seconds
Started Jul 22 04:38:00 PM PDT 24
Finished Jul 22 04:39:36 PM PDT 24
Peak memory 198424 kb
Host smart-0a0fad11-531c-45e6-918d-4fe096bd2d5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117232833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3117232833
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.4245465001
Short name T528
Test name
Test status
Simulation time 45322817 ps
CPU time 0.56 seconds
Started Jul 22 04:42:45 PM PDT 24
Finished Jul 22 04:42:46 PM PDT 24
Peak memory 194348 kb
Host smart-7171aa7e-d54e-47eb-a1d0-34138537fc29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245465001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.4245465001
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1101453401
Short name T52
Test name
Test status
Simulation time 57024152 ps
CPU time 0.72 seconds
Started Jul 22 04:41:13 PM PDT 24
Finished Jul 22 04:41:14 PM PDT 24
Peak memory 195248 kb
Host smart-c3189438-a9d9-43af-910c-c980ce42da14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101453401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1101453401
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3322754779
Short name T476
Test name
Test status
Simulation time 1050065744 ps
CPU time 27.87 seconds
Started Jul 22 04:41:28 PM PDT 24
Finished Jul 22 04:41:57 PM PDT 24
Peak memory 197428 kb
Host smart-e470029c-aeb8-4573-9f08-a7f7128305d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322754779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3322754779
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.377505042
Short name T123
Test name
Test status
Simulation time 214198604 ps
CPU time 0.8 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:41:26 PM PDT 24
Peak memory 196364 kb
Host smart-ffcb6ef8-b547-4cc0-b0f5-61858534649a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377505042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.377505042
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.4149033393
Short name T694
Test name
Test status
Simulation time 36601387 ps
CPU time 1.04 seconds
Started Jul 22 04:41:23 PM PDT 24
Finished Jul 22 04:41:25 PM PDT 24
Peak memory 196552 kb
Host smart-111ef96a-dc82-4170-8014-79837282fcea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149033393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.4149033393
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.1924700327
Short name T209
Test name
Test status
Simulation time 117081679 ps
CPU time 2.27 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:41:27 PM PDT 24
Peak memory 198384 kb
Host smart-72f6c05b-a8bf-43fa-aba2-1cae2e1fba4b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924700327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.1924700327
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1877085067
Short name T225
Test name
Test status
Simulation time 89801524 ps
CPU time 1.71 seconds
Started Jul 22 04:41:23 PM PDT 24
Finished Jul 22 04:41:26 PM PDT 24
Peak memory 196272 kb
Host smart-585ca114-5ac1-4088-84f8-68b8619dd5b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877085067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1877085067
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3865555019
Short name T559
Test name
Test status
Simulation time 45980821 ps
CPU time 0.68 seconds
Started Jul 22 04:41:16 PM PDT 24
Finished Jul 22 04:41:17 PM PDT 24
Peak memory 195336 kb
Host smart-d2d8b443-e4ba-43bc-978e-063e0788a5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865555019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3865555019
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3750287032
Short name T347
Test name
Test status
Simulation time 37991873 ps
CPU time 0.94 seconds
Started Jul 22 04:41:23 PM PDT 24
Finished Jul 22 04:41:25 PM PDT 24
Peak memory 197024 kb
Host smart-bcb96d7c-e169-48ff-84fc-5b6849c6ba21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750287032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3750287032
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.672233146
Short name T189
Test name
Test status
Simulation time 200421315 ps
CPU time 1.79 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:41:27 PM PDT 24
Peak memory 198240 kb
Host smart-02f6cd72-56ee-409a-bc16-bf5965ab024c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672233146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.672233146
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2982439685
Short name T493
Test name
Test status
Simulation time 29643533 ps
CPU time 0.81 seconds
Started Jul 22 04:42:56 PM PDT 24
Finished Jul 22 04:42:57 PM PDT 24
Peak memory 195536 kb
Host smart-7c325b81-1b4b-47d8-9934-bac84b2426b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982439685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2982439685
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3584698867
Short name T685
Test name
Test status
Simulation time 208039687 ps
CPU time 1.2 seconds
Started Jul 22 04:41:13 PM PDT 24
Finished Jul 22 04:41:15 PM PDT 24
Peak memory 196916 kb
Host smart-d8166171-14a0-4db3-96b9-8254e388bb96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584698867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3584698867
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1294606728
Short name T494
Test name
Test status
Simulation time 13736927385 ps
CPU time 91.93 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:42:57 PM PDT 24
Peak memory 198536 kb
Host smart-3363378f-fb8e-410b-b296-e5b4540ec656
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294606728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1294606728
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3675893023
Short name T392
Test name
Test status
Simulation time 46662894996 ps
CPU time 745.52 seconds
Started Jul 22 04:41:23 PM PDT 24
Finished Jul 22 04:53:49 PM PDT 24
Peak memory 198772 kb
Host smart-1972d81b-1baa-4fe0-ae66-765e66dbacd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3675893023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3675893023
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3240665681
Short name T273
Test name
Test status
Simulation time 76303164 ps
CPU time 0.56 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:41:25 PM PDT 24
Peak memory 194332 kb
Host smart-a0006c6f-d6db-4f00-a3a0-2a2623b75bc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240665681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3240665681
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2758368071
Short name T591
Test name
Test status
Simulation time 20203412 ps
CPU time 0.71 seconds
Started Jul 22 04:41:23 PM PDT 24
Finished Jul 22 04:41:25 PM PDT 24
Peak memory 194660 kb
Host smart-52acb8a1-e9c2-4683-9c17-41d8249d70ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758368071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2758368071
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.129914691
Short name T496
Test name
Test status
Simulation time 84944514 ps
CPU time 4.13 seconds
Started Jul 22 04:41:23 PM PDT 24
Finished Jul 22 04:41:28 PM PDT 24
Peak memory 196264 kb
Host smart-e0ce8f29-689d-4268-9eac-ddf591d6beed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129914691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.129914691
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.886111323
Short name T551
Test name
Test status
Simulation time 36392449 ps
CPU time 0.68 seconds
Started Jul 22 04:42:44 PM PDT 24
Finished Jul 22 04:42:45 PM PDT 24
Peak memory 195008 kb
Host smart-6d583219-ad9a-4d40-a7e8-2bee8ebf70bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886111323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.886111323
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.4148626377
Short name T646
Test name
Test status
Simulation time 164212783 ps
CPU time 1.41 seconds
Started Jul 22 04:42:45 PM PDT 24
Finished Jul 22 04:42:47 PM PDT 24
Peak memory 197548 kb
Host smart-42532f19-b18e-4c42-b648-9cc74724620e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148626377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.4148626377
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2604594675
Short name T416
Test name
Test status
Simulation time 24570347 ps
CPU time 1.05 seconds
Started Jul 22 04:41:22 PM PDT 24
Finished Jul 22 04:41:24 PM PDT 24
Peak memory 196472 kb
Host smart-cb1ac27a-42d7-4f6d-a556-42ba537479ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604594675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2604594675
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2621581559
Short name T481
Test name
Test status
Simulation time 124840806 ps
CPU time 2.89 seconds
Started Jul 22 04:41:23 PM PDT 24
Finished Jul 22 04:41:27 PM PDT 24
Peak memory 197724 kb
Host smart-d908fd89-80c1-4968-baba-08a6a348799f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621581559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2621581559
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.75204323
Short name T706
Test name
Test status
Simulation time 31194340 ps
CPU time 0.77 seconds
Started Jul 22 04:41:26 PM PDT 24
Finished Jul 22 04:41:27 PM PDT 24
Peak memory 197064 kb
Host smart-e540d717-e018-4930-9fde-39d421aa06b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75204323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.75204323
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.721852363
Short name T395
Test name
Test status
Simulation time 572241035 ps
CPU time 1.25 seconds
Started Jul 22 04:42:14 PM PDT 24
Finished Jul 22 04:42:16 PM PDT 24
Peak memory 197328 kb
Host smart-cf7471ce-0df8-4e1b-b900-92835f93ecfe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721852363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.721852363
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3763637156
Short name T603
Test name
Test status
Simulation time 1157738653 ps
CPU time 4.42 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:41:29 PM PDT 24
Peak memory 198388 kb
Host smart-959a2dd1-2053-4d4e-a080-8b609c173a12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763637156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3763637156
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1432454092
Short name T522
Test name
Test status
Simulation time 59186137 ps
CPU time 1.11 seconds
Started Jul 22 04:41:22 PM PDT 24
Finished Jul 22 04:41:23 PM PDT 24
Peak memory 197392 kb
Host smart-115e9187-6d97-4eb0-874e-28529a07ae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432454092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1432454092
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2464294068
Short name T126
Test name
Test status
Simulation time 110261118 ps
CPU time 1.29 seconds
Started Jul 22 04:41:22 PM PDT 24
Finished Jul 22 04:41:23 PM PDT 24
Peak memory 197272 kb
Host smart-98d7ba5c-3f77-4691-8203-e0190ff24a26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464294068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2464294068
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.4189509371
Short name T9
Test name
Test status
Simulation time 71300983184 ps
CPU time 234.77 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:45:20 PM PDT 24
Peak memory 198508 kb
Host smart-ee54f0e8-f65d-467d-b9fe-7a4f2ee2caf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189509371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.4189509371
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3359416017
Short name T387
Test name
Test status
Simulation time 117132477618 ps
CPU time 1011.46 seconds
Started Jul 22 04:42:28 PM PDT 24
Finished Jul 22 04:59:20 PM PDT 24
Peak memory 198604 kb
Host smart-dd240509-dd2b-447a-b00e-0eec3490833c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3359416017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3359416017
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2162819120
Short name T382
Test name
Test status
Simulation time 58268333 ps
CPU time 0.64 seconds
Started Jul 22 04:41:32 PM PDT 24
Finished Jul 22 04:41:33 PM PDT 24
Peak memory 194548 kb
Host smart-38491542-4d2d-4424-979a-f1dc2b3eec3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162819120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2162819120
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.686019218
Short name T356
Test name
Test status
Simulation time 53549911 ps
CPU time 0.65 seconds
Started Jul 22 04:41:32 PM PDT 24
Finished Jul 22 04:41:33 PM PDT 24
Peak memory 195164 kb
Host smart-f9b2277b-0f72-4d99-9805-1b708363f40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686019218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.686019218
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2436070106
Short name T642
Test name
Test status
Simulation time 4071609819 ps
CPU time 22.87 seconds
Started Jul 22 04:41:34 PM PDT 24
Finished Jul 22 04:41:57 PM PDT 24
Peak memory 198436 kb
Host smart-29dc3ae2-97fc-4f36-b877-685ea7ad0f7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436070106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2436070106
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3412324218
Short name T484
Test name
Test status
Simulation time 169865579 ps
CPU time 0.82 seconds
Started Jul 22 04:41:34 PM PDT 24
Finished Jul 22 04:41:35 PM PDT 24
Peak memory 196956 kb
Host smart-7822847e-27ec-4485-8132-474228f0ae24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412324218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3412324218
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1462124345
Short name T577
Test name
Test status
Simulation time 72214103 ps
CPU time 0.79 seconds
Started Jul 22 04:41:37 PM PDT 24
Finished Jul 22 04:41:38 PM PDT 24
Peak memory 195948 kb
Host smart-98ffc48a-52e5-46b7-b9ac-d65066c8d5fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462124345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1462124345
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.1200270722
Short name T331
Test name
Test status
Simulation time 358404006 ps
CPU time 4 seconds
Started Jul 22 04:41:31 PM PDT 24
Finished Jul 22 04:41:36 PM PDT 24
Peak memory 198340 kb
Host smart-bafadc85-b83a-477b-af0a-4802a5fa82b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200270722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.1200270722
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.454847879
Short name T339
Test name
Test status
Simulation time 207516110 ps
CPU time 1.32 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:24 PM PDT 24
Peak memory 196364 kb
Host smart-5fbde5c5-cc10-4bac-831a-2e5bf8b03247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454847879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
454847879
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3913299752
Short name T210
Test name
Test status
Simulation time 62630247 ps
CPU time 1.15 seconds
Started Jul 22 04:41:22 PM PDT 24
Finished Jul 22 04:41:24 PM PDT 24
Peak memory 196924 kb
Host smart-2345750a-d9b1-42a1-9cbb-b4787d3b4df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913299752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3913299752
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1252815415
Short name T238
Test name
Test status
Simulation time 289808890 ps
CPU time 1.17 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:41:26 PM PDT 24
Peak memory 196244 kb
Host smart-a855bc38-3df5-4666-bb86-87dfcb9b5356
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252815415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1252815415
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.4097104520
Short name T1
Test name
Test status
Simulation time 1929427502 ps
CPU time 5.82 seconds
Started Jul 22 04:41:36 PM PDT 24
Finished Jul 22 04:41:42 PM PDT 24
Peak memory 198368 kb
Host smart-d01b9311-fa05-434e-b66a-b48f186e26d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097104520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.4097104520
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1500125699
Short name T72
Test name
Test status
Simulation time 203893974 ps
CPU time 1.19 seconds
Started Jul 22 04:41:29 PM PDT 24
Finished Jul 22 04:41:31 PM PDT 24
Peak memory 196984 kb
Host smart-8ca22a9b-24d1-4eed-ab00-498e306f309c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500125699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1500125699
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3399296900
Short name T472
Test name
Test status
Simulation time 90997798 ps
CPU time 0.73 seconds
Started Jul 22 04:41:24 PM PDT 24
Finished Jul 22 04:41:25 PM PDT 24
Peak memory 195324 kb
Host smart-cbf520de-f1ac-4550-b885-e9a0e2fc80c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399296900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3399296900
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.280643922
Short name T99
Test name
Test status
Simulation time 28468640291 ps
CPU time 79.94 seconds
Started Jul 22 04:41:33 PM PDT 24
Finished Jul 22 04:42:54 PM PDT 24
Peak memory 198512 kb
Host smart-00d31813-3e50-4ece-ab27-514b24657c92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280643922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.280643922
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2071750031
Short name T583
Test name
Test status
Simulation time 43370338 ps
CPU time 0.61 seconds
Started Jul 22 04:41:41 PM PDT 24
Finished Jul 22 04:41:42 PM PDT 24
Peak memory 195304 kb
Host smart-9bbaaf76-69c0-4bb3-9b74-2a458c486a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071750031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2071750031
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3752152535
Short name T259
Test name
Test status
Simulation time 24706743 ps
CPU time 0.83 seconds
Started Jul 22 04:41:37 PM PDT 24
Finished Jul 22 04:41:38 PM PDT 24
Peak memory 196516 kb
Host smart-a918fe8d-5500-4313-a38b-69e95f74b05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752152535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3752152535
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2413564688
Short name T589
Test name
Test status
Simulation time 2010109617 ps
CPU time 25.02 seconds
Started Jul 22 04:42:13 PM PDT 24
Finished Jul 22 04:42:39 PM PDT 24
Peak memory 197304 kb
Host smart-e2c1299b-f4f3-435d-80db-1bcd8e03f557
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413564688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2413564688
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3802980334
Short name T174
Test name
Test status
Simulation time 65853051 ps
CPU time 0.85 seconds
Started Jul 22 04:41:46 PM PDT 24
Finished Jul 22 04:41:47 PM PDT 24
Peak memory 197396 kb
Host smart-7fdeb5a7-81bf-4e7d-8040-e3cf1f11c98e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802980334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3802980334
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.110329001
Short name T46
Test name
Test status
Simulation time 187850205 ps
CPU time 0.88 seconds
Started Jul 22 04:41:33 PM PDT 24
Finished Jul 22 04:41:35 PM PDT 24
Peak memory 195944 kb
Host smart-2667bc2f-3216-4b27-a4d2-177c3b4bc270
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110329001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.110329001
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2030445024
Short name T215
Test name
Test status
Simulation time 222381340 ps
CPU time 1.23 seconds
Started Jul 22 04:41:32 PM PDT 24
Finished Jul 22 04:41:33 PM PDT 24
Peak memory 197120 kb
Host smart-5eac6e70-a67e-46bb-b9ab-c46aeed76f3b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030445024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2030445024
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3616468465
Short name T433
Test name
Test status
Simulation time 98915837 ps
CPU time 1.8 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:25 PM PDT 24
Peak memory 195640 kb
Host smart-69621a6a-0f8c-44e8-9c64-6db1a27b39ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616468465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3616468465
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2296709451
Short name T446
Test name
Test status
Simulation time 97702372 ps
CPU time 0.69 seconds
Started Jul 22 04:41:34 PM PDT 24
Finished Jul 22 04:41:35 PM PDT 24
Peak memory 196540 kb
Host smart-5d339f20-5c96-495f-b918-5fc0f6af640e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296709451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2296709451
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3032587281
Short name T445
Test name
Test status
Simulation time 33467772 ps
CPU time 1.19 seconds
Started Jul 22 04:41:37 PM PDT 24
Finished Jul 22 04:41:38 PM PDT 24
Peak memory 197536 kb
Host smart-a4f2d002-41c4-4654-9448-7f0e2bb8a5db
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032587281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3032587281
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1944108711
Short name T166
Test name
Test status
Simulation time 1902322201 ps
CPU time 2.8 seconds
Started Jul 22 04:41:35 PM PDT 24
Finished Jul 22 04:41:38 PM PDT 24
Peak memory 198396 kb
Host smart-03272e03-a06c-4e3b-b673-51c7f742483d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944108711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1944108711
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.417825928
Short name T698
Test name
Test status
Simulation time 463801637 ps
CPU time 0.77 seconds
Started Jul 22 04:41:32 PM PDT 24
Finished Jul 22 04:41:33 PM PDT 24
Peak memory 195308 kb
Host smart-9c343f3e-c0bb-42e2-8d4d-0847e285a300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417825928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.417825928
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1743938736
Short name T597
Test name
Test status
Simulation time 38562287 ps
CPU time 1.13 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:24 PM PDT 24
Peak memory 195960 kb
Host smart-6fcbd4d3-37f9-417c-8f96-75a8cbeaf212
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743938736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1743938736
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.601570725
Short name T385
Test name
Test status
Simulation time 11808313744 ps
CPU time 87.38 seconds
Started Jul 22 04:41:46 PM PDT 24
Finished Jul 22 04:43:14 PM PDT 24
Peak memory 198596 kb
Host smart-3efd1fca-f261-47eb-9179-b58b098870e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601570725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.601570725
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.496716171
Short name T635
Test name
Test status
Simulation time 53002852 ps
CPU time 0.56 seconds
Started Jul 22 04:41:41 PM PDT 24
Finished Jul 22 04:41:42 PM PDT 24
Peak memory 194572 kb
Host smart-0dad395c-eb68-46df-88fe-957e0767b4b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496716171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.496716171
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1933724883
Short name T129
Test name
Test status
Simulation time 19088558 ps
CPU time 0.64 seconds
Started Jul 22 04:41:47 PM PDT 24
Finished Jul 22 04:41:49 PM PDT 24
Peak memory 195076 kb
Host smart-e644c8ed-6465-486b-8a34-3ee83baab744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933724883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1933724883
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2765137461
Short name T229
Test name
Test status
Simulation time 464685790 ps
CPU time 3.58 seconds
Started Jul 22 04:41:42 PM PDT 24
Finished Jul 22 04:41:46 PM PDT 24
Peak memory 195988 kb
Host smart-1666980c-0c5a-40a4-9b94-108a905acc90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765137461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2765137461
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4023654901
Short name T514
Test name
Test status
Simulation time 271078094 ps
CPU time 0.93 seconds
Started Jul 22 04:41:40 PM PDT 24
Finished Jul 22 04:41:42 PM PDT 24
Peak memory 197512 kb
Host smart-fe593808-dec9-4c24-9985-0d5cd7349486
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023654901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4023654901
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1404643410
Short name T581
Test name
Test status
Simulation time 403155972 ps
CPU time 1.14 seconds
Started Jul 22 04:41:46 PM PDT 24
Finished Jul 22 04:41:48 PM PDT 24
Peak memory 196612 kb
Host smart-d1514029-ef4b-4ec7-909c-1dc17e15cae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404643410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1404643410
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2890396182
Short name T333
Test name
Test status
Simulation time 53297557 ps
CPU time 1.17 seconds
Started Jul 22 04:41:42 PM PDT 24
Finished Jul 22 04:41:44 PM PDT 24
Peak memory 198236 kb
Host smart-45b5ca41-09f3-4588-9498-665630279309
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890396182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2890396182
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.3551813044
Short name T672
Test name
Test status
Simulation time 141369766 ps
CPU time 3.16 seconds
Started Jul 22 04:41:39 PM PDT 24
Finished Jul 22 04:41:43 PM PDT 24
Peak memory 198448 kb
Host smart-c5c51595-0487-438c-8f9e-05743ea947fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551813044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.3551813044
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1746214836
Short name T537
Test name
Test status
Simulation time 29080981 ps
CPU time 1.02 seconds
Started Jul 22 04:41:41 PM PDT 24
Finished Jul 22 04:41:43 PM PDT 24
Peak memory 197180 kb
Host smart-122f07ef-7005-4b62-9aa9-ccf243c2442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746214836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1746214836
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1256917815
Short name T186
Test name
Test status
Simulation time 55390227 ps
CPU time 1.08 seconds
Started Jul 22 04:41:46 PM PDT 24
Finished Jul 22 04:41:48 PM PDT 24
Peak memory 196436 kb
Host smart-02ac93b9-24a0-4f5b-afbd-1f2acd765589
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256917815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1256917815
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1884138339
Short name T656
Test name
Test status
Simulation time 540985697 ps
CPU time 2.81 seconds
Started Jul 22 04:41:41 PM PDT 24
Finished Jul 22 04:41:44 PM PDT 24
Peak memory 198440 kb
Host smart-81624236-c4e6-43b4-892a-7685aac0aca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884138339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1884138339
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.67958831
Short name T630
Test name
Test status
Simulation time 29912659 ps
CPU time 0.94 seconds
Started Jul 22 04:41:42 PM PDT 24
Finished Jul 22 04:41:43 PM PDT 24
Peak memory 196680 kb
Host smart-ddfa9899-8314-45af-8eec-8c5dc16a0f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67958831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.67958831
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3125283766
Short name T211
Test name
Test status
Simulation time 506355676 ps
CPU time 1.48 seconds
Started Jul 22 04:41:41 PM PDT 24
Finished Jul 22 04:41:43 PM PDT 24
Peak memory 197056 kb
Host smart-f414f407-2a6e-443b-be8e-e055186fa95d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125283766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3125283766
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1302589986
Short name T6
Test name
Test status
Simulation time 13898624891 ps
CPU time 165.41 seconds
Started Jul 22 04:41:40 PM PDT 24
Finished Jul 22 04:44:26 PM PDT 24
Peak memory 198548 kb
Host smart-991547e9-098a-4bc2-bd1d-514eeb089b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302589986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1302589986
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.4216817695
Short name T54
Test name
Test status
Simulation time 257542951023 ps
CPU time 1076.79 seconds
Started Jul 22 04:41:41 PM PDT 24
Finished Jul 22 04:59:39 PM PDT 24
Peak memory 198676 kb
Host smart-43a8cffa-85ae-42ac-81f1-fe58bd1fc575
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4216817695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.4216817695
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1759323017
Short name T411
Test name
Test status
Simulation time 66674911 ps
CPU time 0.56 seconds
Started Jul 22 04:41:51 PM PDT 24
Finished Jul 22 04:41:52 PM PDT 24
Peak memory 194384 kb
Host smart-b3070a8c-f7e4-4f52-861a-c18a5e13f35f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759323017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1759323017
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.872522655
Short name T495
Test name
Test status
Simulation time 64067581 ps
CPU time 0.68 seconds
Started Jul 22 04:41:41 PM PDT 24
Finished Jul 22 04:41:43 PM PDT 24
Peak memory 194564 kb
Host smart-9fc5a78b-9f2b-458c-9329-68e17937e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872522655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.872522655
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2740447491
Short name T168
Test name
Test status
Simulation time 612689490 ps
CPU time 6.54 seconds
Started Jul 22 04:41:51 PM PDT 24
Finished Jul 22 04:41:58 PM PDT 24
Peak memory 197456 kb
Host smart-38267943-387e-4a25-a5a1-1d4586ef1d9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740447491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2740447491
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2443886765
Short name T610
Test name
Test status
Simulation time 42337935 ps
CPU time 0.78 seconds
Started Jul 22 04:41:48 PM PDT 24
Finished Jul 22 04:41:50 PM PDT 24
Peak memory 196240 kb
Host smart-4f2b7b88-ed1f-4c9f-af04-d2458fd8a250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443886765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2443886765
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4125354339
Short name T162
Test name
Test status
Simulation time 472668438 ps
CPU time 1.26 seconds
Started Jul 22 04:41:49 PM PDT 24
Finished Jul 22 04:41:51 PM PDT 24
Peak memory 197496 kb
Host smart-8343f9b3-fd2b-44ab-88d0-1ceec7900bc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125354339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4125354339
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1487051458
Short name T569
Test name
Test status
Simulation time 318138827 ps
CPU time 3.31 seconds
Started Jul 22 04:41:50 PM PDT 24
Finished Jul 22 04:41:54 PM PDT 24
Peak memory 198412 kb
Host smart-879802ec-2dc8-443b-8b5e-9055ae85f0b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487051458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1487051458
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3118594129
Short name T240
Test name
Test status
Simulation time 550112912 ps
CPU time 3.51 seconds
Started Jul 22 04:41:49 PM PDT 24
Finished Jul 22 04:41:53 PM PDT 24
Peak memory 198528 kb
Host smart-8e7493b5-756b-4904-94d2-c1d796d18267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118594129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3118594129
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3991802593
Short name T293
Test name
Test status
Simulation time 553118799 ps
CPU time 1.35 seconds
Started Jul 22 04:41:41 PM PDT 24
Finished Jul 22 04:41:44 PM PDT 24
Peak memory 197320 kb
Host smart-86cab25e-9ab9-4f92-b283-048e5543093b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991802593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3991802593
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2957501584
Short name T517
Test name
Test status
Simulation time 42391079 ps
CPU time 0.93 seconds
Started Jul 22 04:41:40 PM PDT 24
Finished Jul 22 04:41:42 PM PDT 24
Peak memory 197596 kb
Host smart-d4bdf87d-396e-4515-ad6c-670655de8a97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957501584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2957501584
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3110009460
Short name T140
Test name
Test status
Simulation time 299067991 ps
CPU time 2.56 seconds
Started Jul 22 04:41:47 PM PDT 24
Finished Jul 22 04:41:50 PM PDT 24
Peak memory 198344 kb
Host smart-0eaf2274-f30f-4c04-a4f5-94e74448d983
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110009460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3110009460
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3126525552
Short name T683
Test name
Test status
Simulation time 45236853 ps
CPU time 0.86 seconds
Started Jul 22 04:41:46 PM PDT 24
Finished Jul 22 04:41:48 PM PDT 24
Peak memory 195688 kb
Host smart-9acf1122-1d8d-4c71-a938-61b16ad47f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126525552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3126525552
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2658755723
Short name T330
Test name
Test status
Simulation time 29025542 ps
CPU time 1.05 seconds
Started Jul 22 04:41:39 PM PDT 24
Finished Jul 22 04:41:41 PM PDT 24
Peak memory 196144 kb
Host smart-026be1fc-7e0f-4d5d-be71-45663bdce091
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658755723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2658755723
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.105818966
Short name T292
Test name
Test status
Simulation time 2580082451 ps
CPU time 37.12 seconds
Started Jul 22 04:41:50 PM PDT 24
Finished Jul 22 04:42:28 PM PDT 24
Peak memory 198512 kb
Host smart-f36e9804-8a51-42c4-9a02-7ff239827a60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105818966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.105818966
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.691797975
Short name T34
Test name
Test status
Simulation time 37366162 ps
CPU time 0.56 seconds
Started Jul 22 04:41:48 PM PDT 24
Finished Jul 22 04:41:50 PM PDT 24
Peak memory 194300 kb
Host smart-0b8b6456-439c-4f77-b814-1f6729822fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691797975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.691797975
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3423447376
Short name T536
Test name
Test status
Simulation time 42341668 ps
CPU time 0.8 seconds
Started Jul 22 04:41:48 PM PDT 24
Finished Jul 22 04:41:50 PM PDT 24
Peak memory 195708 kb
Host smart-47a356f4-526d-47cd-a4a0-3c9bb84fdbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423447376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3423447376
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.79044994
Short name T431
Test name
Test status
Simulation time 523458929 ps
CPU time 27.48 seconds
Started Jul 22 04:41:51 PM PDT 24
Finished Jul 22 04:42:19 PM PDT 24
Peak memory 197416 kb
Host smart-25747a6d-36be-42ae-9978-071317229dc3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79044994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stress
.79044994
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3443159682
Short name T185
Test name
Test status
Simulation time 36713171 ps
CPU time 0.78 seconds
Started Jul 22 04:41:47 PM PDT 24
Finished Jul 22 04:41:48 PM PDT 24
Peak memory 196288 kb
Host smart-7dfc217c-a9cc-471c-98e4-0fc8d01074ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443159682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3443159682
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.463979408
Short name T133
Test name
Test status
Simulation time 35535640 ps
CPU time 1.06 seconds
Started Jul 22 04:41:51 PM PDT 24
Finished Jul 22 04:41:52 PM PDT 24
Peak memory 196444 kb
Host smart-6f1b0134-3d5d-4166-8bd4-dc7a9b5ba65a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463979408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.463979408
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.22214183
Short name T426
Test name
Test status
Simulation time 68409823 ps
CPU time 1.06 seconds
Started Jul 22 04:41:48 PM PDT 24
Finished Jul 22 04:41:50 PM PDT 24
Peak memory 197548 kb
Host smart-13c91049-8d5c-4d93-93c4-9f462d9517d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22214183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 46.gpio_intr_with_filter_rand_intr_event.22214183
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3781471067
Short name T183
Test name
Test status
Simulation time 43218588 ps
CPU time 1.18 seconds
Started Jul 22 04:41:49 PM PDT 24
Finished Jul 22 04:41:51 PM PDT 24
Peak memory 196180 kb
Host smart-d1b9ab8f-103b-449a-addb-3c6b4d118f51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781471067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3781471067
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.656877441
Short name T661
Test name
Test status
Simulation time 21453514 ps
CPU time 0.93 seconds
Started Jul 22 04:41:49 PM PDT 24
Finished Jul 22 04:41:51 PM PDT 24
Peak memory 196500 kb
Host smart-8349d0cb-6319-4ed5-a6fc-b4deb47083e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656877441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.656877441
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.657661647
Short name T247
Test name
Test status
Simulation time 41734768 ps
CPU time 0.94 seconds
Started Jul 22 04:41:47 PM PDT 24
Finished Jul 22 04:41:48 PM PDT 24
Peak memory 196404 kb
Host smart-1e9238dd-6912-42f0-bead-864f258386ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657661647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.657661647
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1218033336
Short name T280
Test name
Test status
Simulation time 407701861 ps
CPU time 5.83 seconds
Started Jul 22 04:42:53 PM PDT 24
Finished Jul 22 04:42:59 PM PDT 24
Peak memory 198440 kb
Host smart-8d11d7ca-423c-4c5a-8008-a61d875119e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218033336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1218033336
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2499466095
Short name T11
Test name
Test status
Simulation time 106828528 ps
CPU time 0.81 seconds
Started Jul 22 04:43:16 PM PDT 24
Finished Jul 22 04:43:18 PM PDT 24
Peak memory 196352 kb
Host smart-65d2009b-0b57-46f9-934d-094338ab0c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499466095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2499466095
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.824018424
Short name T521
Test name
Test status
Simulation time 69678757 ps
CPU time 1.06 seconds
Started Jul 22 04:41:49 PM PDT 24
Finished Jul 22 04:41:51 PM PDT 24
Peak memory 196668 kb
Host smart-eff581e4-0546-48de-926e-acc3828ce14e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824018424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.824018424
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1175767800
Short name T404
Test name
Test status
Simulation time 22037121771 ps
CPU time 41.37 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:45:04 PM PDT 24
Peak memory 198508 kb
Host smart-10c7fc85-aeaa-4569-a1c8-657788e07704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175767800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1175767800
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.232080762
Short name T548
Test name
Test status
Simulation time 33939650 ps
CPU time 0.57 seconds
Started Jul 22 04:41:57 PM PDT 24
Finished Jul 22 04:41:58 PM PDT 24
Peak memory 195196 kb
Host smart-355cc605-378b-4dad-a954-23afaa281652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232080762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.232080762
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.635791758
Short name T696
Test name
Test status
Simulation time 33602937 ps
CPU time 0.77 seconds
Started Jul 22 04:42:00 PM PDT 24
Finished Jul 22 04:42:01 PM PDT 24
Peak memory 195756 kb
Host smart-d941ef8b-e50f-41d8-a4ec-c3b761a841ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635791758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.635791758
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3717289457
Short name T198
Test name
Test status
Simulation time 1494117069 ps
CPU time 15.44 seconds
Started Jul 22 04:41:58 PM PDT 24
Finished Jul 22 04:42:14 PM PDT 24
Peak memory 197168 kb
Host smart-59d479b6-cefe-4dfa-be60-59575a56e471
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717289457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3717289457
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.260525665
Short name T260
Test name
Test status
Simulation time 23970315 ps
CPU time 0.72 seconds
Started Jul 22 04:42:01 PM PDT 24
Finished Jul 22 04:42:02 PM PDT 24
Peak memory 194980 kb
Host smart-da0d0944-76ce-4b4c-b337-6f176e244372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260525665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.260525665
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1692212895
Short name T590
Test name
Test status
Simulation time 213889076 ps
CPU time 0.74 seconds
Started Jul 22 04:42:02 PM PDT 24
Finished Jul 22 04:42:04 PM PDT 24
Peak memory 194852 kb
Host smart-3f5e6888-e939-4651-a98c-27b5c394d6aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692212895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1692212895
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1872228431
Short name T399
Test name
Test status
Simulation time 96838684 ps
CPU time 1.06 seconds
Started Jul 22 04:41:58 PM PDT 24
Finished Jul 22 04:41:59 PM PDT 24
Peak memory 196752 kb
Host smart-6a02ad43-3355-4d62-961c-d03da8b0eee0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872228431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1872228431
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1958557029
Short name T321
Test name
Test status
Simulation time 782879332 ps
CPU time 1.42 seconds
Started Jul 22 04:41:57 PM PDT 24
Finished Jul 22 04:41:59 PM PDT 24
Peak memory 197196 kb
Host smart-669b8f61-eccf-44ab-aa7e-d9ec044018fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958557029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1958557029
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3974246532
Short name T585
Test name
Test status
Simulation time 25586944 ps
CPU time 0.78 seconds
Started Jul 22 04:42:01 PM PDT 24
Finished Jul 22 04:42:03 PM PDT 24
Peak memory 195840 kb
Host smart-2a5f0650-8343-46a0-81f1-5c161c2884ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974246532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3974246532
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2627502837
Short name T50
Test name
Test status
Simulation time 178077461 ps
CPU time 1.04 seconds
Started Jul 22 04:42:02 PM PDT 24
Finished Jul 22 04:42:04 PM PDT 24
Peak memory 196232 kb
Host smart-420df831-f002-4372-8d64-bf419e08b195
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627502837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2627502837
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3190265018
Short name T92
Test name
Test status
Simulation time 175759021 ps
CPU time 2.45 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:25 PM PDT 24
Peak memory 197392 kb
Host smart-b021adf7-3cf2-4024-b33e-a462ca708cc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190265018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3190265018
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4195643126
Short name T175
Test name
Test status
Simulation time 26274485 ps
CPU time 0.73 seconds
Started Jul 22 04:41:49 PM PDT 24
Finished Jul 22 04:41:50 PM PDT 24
Peak memory 194512 kb
Host smart-27e61682-1472-4d5b-bce8-2cfb7f5b5639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195643126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4195643126
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2879658512
Short name T487
Test name
Test status
Simulation time 288826903 ps
CPU time 1.16 seconds
Started Jul 22 04:41:49 PM PDT 24
Finished Jul 22 04:41:51 PM PDT 24
Peak memory 198456 kb
Host smart-4b2a072a-542a-46a9-a5f5-c90ce7b91e76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879658512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2879658512
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1032179545
Short name T686
Test name
Test status
Simulation time 5957293368 ps
CPU time 39.89 seconds
Started Jul 22 04:42:01 PM PDT 24
Finished Jul 22 04:42:42 PM PDT 24
Peak memory 198444 kb
Host smart-dc49e650-40ac-4172-89dd-3f5eb6da4cd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032179545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1032179545
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3643234615
Short name T645
Test name
Test status
Simulation time 87270806 ps
CPU time 0.58 seconds
Started Jul 22 04:41:58 PM PDT 24
Finished Jul 22 04:41:59 PM PDT 24
Peak memory 194292 kb
Host smart-e9a9434e-2c6c-408e-b726-9f2e038be6b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643234615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3643234615
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.742573929
Short name T485
Test name
Test status
Simulation time 19708333 ps
CPU time 0.71 seconds
Started Jul 22 04:42:01 PM PDT 24
Finished Jul 22 04:42:02 PM PDT 24
Peak memory 194532 kb
Host smart-61667bbe-cc04-44b4-8976-97ec11d0d874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742573929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.742573929
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1782438506
Short name T337
Test name
Test status
Simulation time 219635161 ps
CPU time 5.48 seconds
Started Jul 22 04:42:03 PM PDT 24
Finished Jul 22 04:42:09 PM PDT 24
Peak memory 197412 kb
Host smart-273b49a2-71cb-4d7e-a58a-3f94a1ba52c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782438506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1782438506
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1600117732
Short name T332
Test name
Test status
Simulation time 37887578 ps
CPU time 0.77 seconds
Started Jul 22 04:42:03 PM PDT 24
Finished Jul 22 04:42:04 PM PDT 24
Peak memory 195156 kb
Host smart-40a10a9a-8cab-42ea-8491-4ae2629d51a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600117732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1600117732
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1954047834
Short name T402
Test name
Test status
Simulation time 84247487 ps
CPU time 1.44 seconds
Started Jul 22 04:41:59 PM PDT 24
Finished Jul 22 04:42:01 PM PDT 24
Peak memory 196160 kb
Host smart-6effb19f-8247-49ca-81fd-cdaa8e3ffac6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954047834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1954047834
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1605267805
Short name T509
Test name
Test status
Simulation time 59718248 ps
CPU time 2.4 seconds
Started Jul 22 04:42:03 PM PDT 24
Finished Jul 22 04:42:07 PM PDT 24
Peak memory 198384 kb
Host smart-3c3b0716-8b53-46d9-a7f3-59d6b4644b12
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605267805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1605267805
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1783269953
Short name T295
Test name
Test status
Simulation time 245213518 ps
CPU time 1.48 seconds
Started Jul 22 04:44:22 PM PDT 24
Finished Jul 22 04:44:24 PM PDT 24
Peak memory 196588 kb
Host smart-47f76b17-a4ea-43e1-badd-1caa7e79aa9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783269953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1783269953
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.17334955
Short name T541
Test name
Test status
Simulation time 153371145 ps
CPU time 1.27 seconds
Started Jul 22 04:42:01 PM PDT 24
Finished Jul 22 04:42:03 PM PDT 24
Peak memory 196932 kb
Host smart-0d9162ff-3fb3-4c3d-bc4d-58a24f600fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17334955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.17334955
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3124133499
Short name T400
Test name
Test status
Simulation time 175076427 ps
CPU time 0.82 seconds
Started Jul 22 04:42:03 PM PDT 24
Finished Jul 22 04:42:05 PM PDT 24
Peak memory 196908 kb
Host smart-103cd24e-b875-49fa-8c4e-76e6841db5f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124133499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3124133499
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2866969766
Short name T2
Test name
Test status
Simulation time 232832114 ps
CPU time 3.15 seconds
Started Jul 22 04:41:59 PM PDT 24
Finished Jul 22 04:42:03 PM PDT 24
Peak memory 198340 kb
Host smart-d19686d9-efb5-4a21-a6bf-8935dcd38ca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866969766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2866969766
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.4163543439
Short name T455
Test name
Test status
Simulation time 86896280 ps
CPU time 0.82 seconds
Started Jul 22 04:42:01 PM PDT 24
Finished Jul 22 04:42:02 PM PDT 24
Peak memory 195600 kb
Host smart-7dd03c71-effc-4af9-916f-18a136574618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163543439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4163543439
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3702802747
Short name T394
Test name
Test status
Simulation time 61512837 ps
CPU time 1.05 seconds
Started Jul 22 04:41:57 PM PDT 24
Finished Jul 22 04:41:58 PM PDT 24
Peak memory 196148 kb
Host smart-7dcb2476-1215-4799-8cdb-b9f182c67e39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702802747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3702802747
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.3835934187
Short name T357
Test name
Test status
Simulation time 7262931006 ps
CPU time 94.79 seconds
Started Jul 22 04:42:06 PM PDT 24
Finished Jul 22 04:43:41 PM PDT 24
Peak memory 198456 kb
Host smart-474e56c2-6198-409f-bec2-6cc619f69ab0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835934187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.3835934187
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3076949208
Short name T622
Test name
Test status
Simulation time 67051363250 ps
CPU time 1607.51 seconds
Started Jul 22 04:41:57 PM PDT 24
Finished Jul 22 05:08:45 PM PDT 24
Peak memory 198676 kb
Host smart-da7eea94-e515-406a-b85d-8274a35492e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3076949208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3076949208
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.4025510643
Short name T456
Test name
Test status
Simulation time 10856906 ps
CPU time 0.55 seconds
Started Jul 22 04:42:07 PM PDT 24
Finished Jul 22 04:42:08 PM PDT 24
Peak memory 193140 kb
Host smart-92e16e7b-4966-4edf-822d-965fd8e22e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025510643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.4025510643
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2742418680
Short name T677
Test name
Test status
Simulation time 80713024 ps
CPU time 0.66 seconds
Started Jul 22 04:41:57 PM PDT 24
Finished Jul 22 04:41:58 PM PDT 24
Peak memory 194496 kb
Host smart-4f1ee5d5-acb8-49ab-bdeb-df3990fd00fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742418680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2742418680
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2224329124
Short name T157
Test name
Test status
Simulation time 1792666728 ps
CPU time 22.94 seconds
Started Jul 22 04:42:06 PM PDT 24
Finished Jul 22 04:42:30 PM PDT 24
Peak memory 198404 kb
Host smart-7c02bb43-da65-495e-b099-41681d11af34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224329124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2224329124
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2217696970
Short name T605
Test name
Test status
Simulation time 216994300 ps
CPU time 0.6 seconds
Started Jul 22 04:42:13 PM PDT 24
Finished Jul 22 04:42:14 PM PDT 24
Peak memory 195604 kb
Host smart-159b65dc-5f07-42ba-9090-2dcf8ab12bd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217696970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2217696970
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.386256040
Short name T408
Test name
Test status
Simulation time 62738162 ps
CPU time 0.87 seconds
Started Jul 22 04:42:01 PM PDT 24
Finished Jul 22 04:42:02 PM PDT 24
Peak memory 195868 kb
Host smart-02da801d-1c92-44a9-9a4c-263696fe3156
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386256040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.386256040
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2754890832
Short name T112
Test name
Test status
Simulation time 905079178 ps
CPU time 2.36 seconds
Started Jul 22 04:42:03 PM PDT 24
Finished Jul 22 04:42:06 PM PDT 24
Peak memory 198464 kb
Host smart-b665f7e4-faab-4f4f-b0f9-0766b2647f31
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754890832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2754890832
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.828174703
Short name T643
Test name
Test status
Simulation time 267980040 ps
CPU time 1.99 seconds
Started Jul 22 04:41:54 PM PDT 24
Finished Jul 22 04:41:57 PM PDT 24
Peak memory 197240 kb
Host smart-13b6e3d2-ee54-4e3c-8bb6-1637d0b606e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828174703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
828174703
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1811645045
Short name T132
Test name
Test status
Simulation time 32342579 ps
CPU time 0.96 seconds
Started Jul 22 04:41:58 PM PDT 24
Finished Jul 22 04:42:00 PM PDT 24
Peak memory 196420 kb
Host smart-0c7245da-ead8-45b7-958d-a7cb2a8d8ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811645045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1811645045
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.4161274562
Short name T301
Test name
Test status
Simulation time 187681522 ps
CPU time 1.26 seconds
Started Jul 22 04:42:03 PM PDT 24
Finished Jul 22 04:42:05 PM PDT 24
Peak memory 198412 kb
Host smart-66ffdee5-f304-40c4-afe3-f3b098d547da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161274562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.4161274562
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2501000429
Short name T539
Test name
Test status
Simulation time 292119351 ps
CPU time 4.71 seconds
Started Jul 22 04:42:07 PM PDT 24
Finished Jul 22 04:42:12 PM PDT 24
Peak memory 198432 kb
Host smart-08a572c3-780c-4bd9-ba22-031af2b30f5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501000429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2501000429
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1440971857
Short name T397
Test name
Test status
Simulation time 121900269 ps
CPU time 1.27 seconds
Started Jul 22 04:42:02 PM PDT 24
Finished Jul 22 04:42:04 PM PDT 24
Peak memory 196172 kb
Host smart-343acd5a-be1c-4da2-9c8a-9453499ca7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440971857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1440971857
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1100037526
Short name T208
Test name
Test status
Simulation time 190086602 ps
CPU time 1.36 seconds
Started Jul 22 04:42:01 PM PDT 24
Finished Jul 22 04:42:02 PM PDT 24
Peak memory 195972 kb
Host smart-f930083c-cd92-4b45-b63b-446cb338463b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100037526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1100037526
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2403534017
Short name T190
Test name
Test status
Simulation time 864286500 ps
CPU time 20.51 seconds
Started Jul 22 04:43:18 PM PDT 24
Finished Jul 22 04:43:40 PM PDT 24
Peak memory 198556 kb
Host smart-667ecb2f-8d19-4184-9b08-ca4dce42faef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403534017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2403534017
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3856283245
Short name T58
Test name
Test status
Simulation time 307063391544 ps
CPU time 814.08 seconds
Started Jul 22 04:42:08 PM PDT 24
Finished Jul 22 04:55:43 PM PDT 24
Peak memory 206856 kb
Host smart-855d640f-1c6c-4c5e-af5f-33d2d87ceab6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3856283245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3856283245
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2391038022
Short name T266
Test name
Test status
Simulation time 23524100 ps
CPU time 0.58 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:11 PM PDT 24
Peak memory 194324 kb
Host smart-9f499ca6-a8c0-4de8-9731-50f96d22baa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391038022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2391038022
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1934744195
Short name T535
Test name
Test status
Simulation time 65186156 ps
CPU time 0.71 seconds
Started Jul 22 04:38:13 PM PDT 24
Finished Jul 22 04:38:14 PM PDT 24
Peak memory 194460 kb
Host smart-dbe2dec7-ab6d-4817-84bd-51f0791769b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934744195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1934744195
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1627450069
Short name T604
Test name
Test status
Simulation time 4652640242 ps
CPU time 17.87 seconds
Started Jul 22 04:38:09 PM PDT 24
Finished Jul 22 04:38:27 PM PDT 24
Peak memory 197628 kb
Host smart-06e6c000-9a35-43a0-98b1-34e131eebd50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627450069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1627450069
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3648504931
Short name T316
Test name
Test status
Simulation time 74827708 ps
CPU time 0.71 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:12 PM PDT 24
Peak memory 195028 kb
Host smart-114cb21d-0da7-4823-a24a-cc5eedf69042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648504931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3648504931
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1629341423
Short name T159
Test name
Test status
Simulation time 313103310 ps
CPU time 1.18 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:12 PM PDT 24
Peak memory 196532 kb
Host smart-41bdddf0-c6b9-402d-b43d-60b33e25ae69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629341423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1629341423
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.4001604315
Short name T709
Test name
Test status
Simulation time 19740267 ps
CPU time 0.93 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:12 PM PDT 24
Peak memory 197472 kb
Host smart-6ca0ea90-125d-4774-9d4a-0a75d27fb6ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001604315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.4001604315
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2789684795
Short name T218
Test name
Test status
Simulation time 93683259 ps
CPU time 2.42 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:14 PM PDT 24
Peak memory 197644 kb
Host smart-e06d1048-196b-44ac-9250-eb0ab400c8db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789684795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2789684795
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.4103050705
Short name T235
Test name
Test status
Simulation time 229636814 ps
CPU time 1.4 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:12 PM PDT 24
Peak memory 197324 kb
Host smart-addbcfc4-c1f8-4ea8-8990-462dd4d72fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103050705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.4103050705
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.441508225
Short name T611
Test name
Test status
Simulation time 76734643 ps
CPU time 1.25 seconds
Started Jul 22 04:38:11 PM PDT 24
Finished Jul 22 04:38:13 PM PDT 24
Peak memory 196276 kb
Host smart-0b63c759-3762-4d5c-a7a0-aee5ecb84bbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441508225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.441508225
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3192988736
Short name T556
Test name
Test status
Simulation time 201692700 ps
CPU time 2.65 seconds
Started Jul 22 04:38:11 PM PDT 24
Finished Jul 22 04:38:14 PM PDT 24
Peak memory 198472 kb
Host smart-f1f7681b-2421-4575-8fcb-c3ace3fc5a0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192988736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3192988736
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1789497182
Short name T167
Test name
Test status
Simulation time 76169013 ps
CPU time 0.79 seconds
Started Jul 22 04:38:02 PM PDT 24
Finished Jul 22 04:38:03 PM PDT 24
Peak memory 195548 kb
Host smart-2c5cc60b-23a3-4128-9a5b-c1db2f3009ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789497182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1789497182
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1835619517
Short name T418
Test name
Test status
Simulation time 216647863 ps
CPU time 1.17 seconds
Started Jul 22 04:40:51 PM PDT 24
Finished Jul 22 04:40:54 PM PDT 24
Peak memory 196772 kb
Host smart-0a4b82c7-bf03-4ac2-bf20-e8f9c03abd55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835619517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1835619517
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1100494295
Short name T312
Test name
Test status
Simulation time 2162429497 ps
CPU time 22.35 seconds
Started Jul 22 04:40:51 PM PDT 24
Finished Jul 22 04:41:15 PM PDT 24
Peak memory 198264 kb
Host smart-ab913297-7666-49a9-ba5c-064ea06e76ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100494295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1100494295
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2370976807
Short name T22
Test name
Test status
Simulation time 60909393431 ps
CPU time 1609.75 seconds
Started Jul 22 04:38:09 PM PDT 24
Finished Jul 22 05:04:59 PM PDT 24
Peak memory 198608 kb
Host smart-3b26180b-ee24-4e6a-b8c9-9ee9ea310f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2370976807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2370976807
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1724567014
Short name T73
Test name
Test status
Simulation time 23456498 ps
CPU time 0.61 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 04:40:30 PM PDT 24
Peak memory 194868 kb
Host smart-84007997-3b15-43b8-860e-8525e331c773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724567014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1724567014
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.639380813
Short name T679
Test name
Test status
Simulation time 49246101 ps
CPU time 0.83 seconds
Started Jul 22 04:38:12 PM PDT 24
Finished Jul 22 04:38:13 PM PDT 24
Peak memory 196580 kb
Host smart-3d9d5075-822f-48bb-a107-2d5f5d878819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639380813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.639380813
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.917107078
Short name T296
Test name
Test status
Simulation time 1263134841 ps
CPU time 19.76 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:30 PM PDT 24
Peak memory 197304 kb
Host smart-4ae9db06-5a3f-4333-9ff6-ef507d946f49
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917107078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.917107078
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1231438995
Short name T637
Test name
Test status
Simulation time 37053288 ps
CPU time 0.73 seconds
Started Jul 22 04:38:11 PM PDT 24
Finished Jul 22 04:38:12 PM PDT 24
Peak memory 195168 kb
Host smart-2cd1e3fa-d174-4bdc-beba-78dd4f080736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231438995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1231438995
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1955277889
Short name T555
Test name
Test status
Simulation time 189204458 ps
CPU time 1.23 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:12 PM PDT 24
Peak memory 196440 kb
Host smart-9be3e8f2-a4a3-4dab-abac-0d33fd87ff9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955277889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1955277889
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.143425559
Short name T334
Test name
Test status
Simulation time 380827212 ps
CPU time 2.27 seconds
Started Jul 22 04:40:51 PM PDT 24
Finished Jul 22 04:40:54 PM PDT 24
Peak memory 198372 kb
Host smart-3feba0fb-9022-4f00-a304-1f536c061ab9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143425559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.143425559
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3190120675
Short name T420
Test name
Test status
Simulation time 115677260 ps
CPU time 1.92 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 04:40:32 PM PDT 24
Peak memory 196780 kb
Host smart-180d7f3d-eed4-488e-a4ba-ab5e5dcdb4a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190120675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3190120675
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3558135812
Short name T508
Test name
Test status
Simulation time 47649522 ps
CPU time 1 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 04:40:31 PM PDT 24
Peak memory 196328 kb
Host smart-49fa2f9c-4020-4978-8293-191587f85f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558135812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3558135812
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.4034060636
Short name T626
Test name
Test status
Simulation time 62716691 ps
CPU time 0.68 seconds
Started Jul 22 04:38:11 PM PDT 24
Finished Jul 22 04:38:12 PM PDT 24
Peak memory 195320 kb
Host smart-64021033-e3c5-4a87-b1d1-91d57321442c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034060636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.4034060636
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1709212534
Short name T473
Test name
Test status
Simulation time 226737148 ps
CPU time 5.41 seconds
Started Jul 22 04:38:09 PM PDT 24
Finished Jul 22 04:38:14 PM PDT 24
Peak memory 198444 kb
Host smart-a405ecd3-019f-4350-8d54-4843b6a7833d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709212534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1709212534
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3076173959
Short name T625
Test name
Test status
Simulation time 67156629 ps
CPU time 1 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:11 PM PDT 24
Peak memory 196172 kb
Host smart-252a8396-5d3e-4034-8f21-f6d88923211d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076173959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3076173959
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.345739367
Short name T47
Test name
Test status
Simulation time 66426644 ps
CPU time 1.24 seconds
Started Jul 22 04:38:10 PM PDT 24
Finished Jul 22 04:38:11 PM PDT 24
Peak memory 198324 kb
Host smart-d9a0fc06-10bc-4e9f-a9e2-e5422fbeb1e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345739367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.345739367
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1175119297
Short name T499
Test name
Test status
Simulation time 31485762590 ps
CPU time 175.53 seconds
Started Jul 22 04:38:11 PM PDT 24
Finished Jul 22 04:41:07 PM PDT 24
Peak memory 198460 kb
Host smart-4aa7c756-b5e9-40a0-b60b-b8460693b82f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175119297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1175119297
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.973028008
Short name T531
Test name
Test status
Simulation time 45291522 ps
CPU time 0.59 seconds
Started Jul 22 04:38:19 PM PDT 24
Finished Jul 22 04:38:20 PM PDT 24
Peak memory 195044 kb
Host smart-6487349f-eb9d-425f-94cb-a47db6688a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973028008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.973028008
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3905910378
Short name T322
Test name
Test status
Simulation time 339130129 ps
CPU time 0.88 seconds
Started Jul 22 04:38:19 PM PDT 24
Finished Jul 22 04:38:20 PM PDT 24
Peak memory 196964 kb
Host smart-56e7211f-fde3-4bee-85a0-d24f8e2f0223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905910378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3905910378
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.4201464560
Short name T379
Test name
Test status
Simulation time 3339037441 ps
CPU time 24.81 seconds
Started Jul 22 04:38:19 PM PDT 24
Finished Jul 22 04:38:45 PM PDT 24
Peak memory 197232 kb
Host smart-4ab65e79-bc99-4be4-ab6e-8ca83cf8c29f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201464560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.4201464560
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.717135022
Short name T409
Test name
Test status
Simulation time 225166059 ps
CPU time 0.9 seconds
Started Jul 22 04:38:17 PM PDT 24
Finished Jul 22 04:38:18 PM PDT 24
Peak memory 196420 kb
Host smart-ef397da8-3ca5-4198-9b1b-470f1a7f2fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717135022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.717135022
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4233658260
Short name T300
Test name
Test status
Simulation time 79624541 ps
CPU time 0.82 seconds
Started Jul 22 04:38:18 PM PDT 24
Finished Jul 22 04:38:20 PM PDT 24
Peak memory 196020 kb
Host smart-3aa022b4-3c12-4630-90b8-ab4af0daee4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233658260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4233658260
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3709345500
Short name T393
Test name
Test status
Simulation time 48143966 ps
CPU time 1.21 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 04:40:31 PM PDT 24
Peak memory 197968 kb
Host smart-c96ca573-7f08-4467-b664-0f700c656cb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709345500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3709345500
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3707939165
Short name T202
Test name
Test status
Simulation time 81478880 ps
CPU time 1.92 seconds
Started Jul 22 04:38:19 PM PDT 24
Finished Jul 22 04:38:22 PM PDT 24
Peak memory 197160 kb
Host smart-532ddf14-261c-45d6-b47f-789a7beb322d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707939165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3707939165
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2919876551
Short name T360
Test name
Test status
Simulation time 201509341 ps
CPU time 1.19 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 04:40:31 PM PDT 24
Peak memory 198436 kb
Host smart-5818d32a-3051-4aec-a225-c8b274005816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919876551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2919876551
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4108573997
Short name T421
Test name
Test status
Simulation time 239241304 ps
CPU time 1.16 seconds
Started Jul 22 04:38:17 PM PDT 24
Finished Jul 22 04:38:19 PM PDT 24
Peak memory 196432 kb
Host smart-c561500d-eac4-4218-ba10-111f92380097
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108573997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4108573997
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_smoke.3467535293
Short name T684
Test name
Test status
Simulation time 726847229 ps
CPU time 1.19 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 04:40:31 PM PDT 24
Peak memory 196088 kb
Host smart-e82fe516-bd54-4f7f-a64c-c83ae2ac8a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467535293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3467535293
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.237749092
Short name T364
Test name
Test status
Simulation time 263328231 ps
CPU time 1.49 seconds
Started Jul 22 04:38:09 PM PDT 24
Finished Jul 22 04:38:11 PM PDT 24
Peak memory 197156 kb
Host smart-a9b94c69-2b19-4d99-b686-022c2978b3f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237749092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.237749092
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.913642063
Short name T650
Test name
Test status
Simulation time 5518540927 ps
CPU time 125.85 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 04:42:35 PM PDT 24
Peak memory 198472 kb
Host smart-ca462e30-1720-408d-b05f-95025d2ba8e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913642063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.913642063
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3788977361
Short name T507
Test name
Test status
Simulation time 14510463 ps
CPU time 0.61 seconds
Started Jul 22 04:38:56 PM PDT 24
Finished Jul 22 04:38:57 PM PDT 24
Peak memory 194812 kb
Host smart-bf5ae767-d420-46fe-8dd2-5c92cc22c43a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788977361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3788977361
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.204299688
Short name T568
Test name
Test status
Simulation time 25252664 ps
CPU time 0.75 seconds
Started Jul 22 04:38:16 PM PDT 24
Finished Jul 22 04:38:17 PM PDT 24
Peak memory 195668 kb
Host smart-daf78852-e8f5-437e-8b61-41e7d1d9c6ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204299688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.204299688
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.273015044
Short name T319
Test name
Test status
Simulation time 519249605 ps
CPU time 6.81 seconds
Started Jul 22 04:38:26 PM PDT 24
Finished Jul 22 04:38:33 PM PDT 24
Peak memory 195952 kb
Host smart-2a14c257-15e7-439c-ae0e-8f00505e75e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273015044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.273015044
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.176766578
Short name T205
Test name
Test status
Simulation time 32090949 ps
CPU time 0.68 seconds
Started Jul 22 04:38:25 PM PDT 24
Finished Jul 22 04:38:26 PM PDT 24
Peak memory 195216 kb
Host smart-c5313568-48a3-408a-be02-30322033bd69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176766578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.176766578
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3347346077
Short name T212
Test name
Test status
Simulation time 36311249 ps
CPU time 0.85 seconds
Started Jul 22 04:38:18 PM PDT 24
Finished Jul 22 04:38:19 PM PDT 24
Peak memory 196624 kb
Host smart-ceceaa66-b0d3-4a51-99df-bc01c210466b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347346077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3347346077
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.779574861
Short name T117
Test name
Test status
Simulation time 108808111 ps
CPU time 3.09 seconds
Started Jul 22 04:38:28 PM PDT 24
Finished Jul 22 04:38:32 PM PDT 24
Peak memory 198428 kb
Host smart-b9b5acf2-59ef-42d9-99fa-47dc90589724
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779574861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.779574861
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.984264558
Short name T588
Test name
Test status
Simulation time 61039081 ps
CPU time 1.52 seconds
Started Jul 22 04:40:27 PM PDT 24
Finished Jul 22 04:40:30 PM PDT 24
Peak memory 196380 kb
Host smart-413d0525-fe69-4a1b-b517-d5ecaf9d8ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984264558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.984264558
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1080887235
Short name T171
Test name
Test status
Simulation time 91558142 ps
CPU time 1.19 seconds
Started Jul 22 04:38:18 PM PDT 24
Finished Jul 22 04:38:20 PM PDT 24
Peak memory 196228 kb
Host smart-73a4b739-07c4-4a5a-b8a2-e3b8421b02f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080887235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1080887235
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3896846082
Short name T657
Test name
Test status
Simulation time 45024660 ps
CPU time 1.05 seconds
Started Jul 22 04:38:49 PM PDT 24
Finished Jul 22 04:38:51 PM PDT 24
Peak memory 197204 kb
Host smart-fba9edcb-c102-4af3-ad8f-f9ab70769f65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896846082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3896846082
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2677400790
Short name T303
Test name
Test status
Simulation time 101381904 ps
CPU time 2.58 seconds
Started Jul 22 04:40:27 PM PDT 24
Finished Jul 22 04:40:31 PM PDT 24
Peak memory 198188 kb
Host smart-930e3909-4a32-4379-b27a-278ac6421bcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677400790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2677400790
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2709605193
Short name T454
Test name
Test status
Simulation time 56132842 ps
CPU time 1 seconds
Started Jul 22 04:38:18 PM PDT 24
Finished Jul 22 04:38:20 PM PDT 24
Peak memory 196412 kb
Host smart-eb0fcb3a-62fd-47d2-9b67-c45acc938fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709605193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2709605193
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1086276276
Short name T378
Test name
Test status
Simulation time 108868969 ps
CPU time 1.04 seconds
Started Jul 22 04:38:18 PM PDT 24
Finished Jul 22 04:38:20 PM PDT 24
Peak memory 196728 kb
Host smart-6caf151b-ca0a-4bbd-9ea2-054c0302275b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086276276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1086276276
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.97101788
Short name T263
Test name
Test status
Simulation time 62110715264 ps
CPU time 240.16 seconds
Started Jul 22 04:38:26 PM PDT 24
Finished Jul 22 04:42:27 PM PDT 24
Peak memory 198572 kb
Host smart-d8512a8a-6d04-483c-af3b-ff8bae0170d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97101788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpi
o_stress_all.97101788
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2743013886
Short name T513
Test name
Test status
Simulation time 15624880 ps
CPU time 0.55 seconds
Started Jul 22 04:40:29 PM PDT 24
Finished Jul 22 04:40:30 PM PDT 24
Peak memory 193072 kb
Host smart-fa3aee3c-1daa-4ce4-ba32-afd44c6c2c14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743013886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2743013886
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1147925952
Short name T277
Test name
Test status
Simulation time 54771555 ps
CPU time 0.86 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:29 PM PDT 24
Peak memory 197580 kb
Host smart-d0cfeba6-8ac2-4b1f-9fc7-a49203d7d446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147925952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1147925952
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3771995765
Short name T156
Test name
Test status
Simulation time 4904472162 ps
CPU time 27.28 seconds
Started Jul 22 04:38:56 PM PDT 24
Finished Jul 22 04:39:23 PM PDT 24
Peak memory 198316 kb
Host smart-b21ee5b0-85b9-4fc7-88b7-eec478c7cf89
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771995765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3771995765
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.935486964
Short name T427
Test name
Test status
Simulation time 564499043 ps
CPU time 0.95 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:29 PM PDT 24
Peak memory 197324 kb
Host smart-18114de0-69f1-4345-afdf-1963d75457ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935486964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.935486964
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3483059966
Short name T254
Test name
Test status
Simulation time 95787768 ps
CPU time 1.32 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:29 PM PDT 24
Peak memory 197504 kb
Host smart-9a72f1dc-31c8-40b7-8f4c-1cc3d722bcb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483059966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3483059966
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2551456963
Short name T662
Test name
Test status
Simulation time 160550733 ps
CPU time 1.98 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:30 PM PDT 24
Peak memory 198516 kb
Host smart-39ffe4cf-37c5-4485-aafd-774ea0e84159
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551456963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2551456963
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.28978929
Short name T121
Test name
Test status
Simulation time 244898712 ps
CPU time 2.2 seconds
Started Jul 22 04:38:26 PM PDT 24
Finished Jul 22 04:38:29 PM PDT 24
Peak memory 196648 kb
Host smart-10e2730b-35b6-4859-908b-92dd4e38e3e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28978929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.28978929
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1375193513
Short name T372
Test name
Test status
Simulation time 35513424 ps
CPU time 0.84 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:29 PM PDT 24
Peak memory 195848 kb
Host smart-171568c3-c122-47cc-b63e-7c9ba40e4182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375193513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1375193513
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1439834927
Short name T593
Test name
Test status
Simulation time 124542834 ps
CPU time 1.31 seconds
Started Jul 22 04:38:26 PM PDT 24
Finished Jul 22 04:38:27 PM PDT 24
Peak memory 198448 kb
Host smart-82e1f9ae-c7b3-4670-9cfd-1afa7a5e99d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439834927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1439834927
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2846567389
Short name T419
Test name
Test status
Simulation time 75905550 ps
CPU time 3.59 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:38:32 PM PDT 24
Peak memory 198472 kb
Host smart-614e40ca-95c0-4e10-932b-ad830fdcbd27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846567389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2846567389
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2852540914
Short name T573
Test name
Test status
Simulation time 37625645 ps
CPU time 0.89 seconds
Started Jul 22 04:38:26 PM PDT 24
Finished Jul 22 04:38:28 PM PDT 24
Peak memory 196480 kb
Host smart-6ebca226-e248-47f3-9ab6-daa7377919c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852540914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2852540914
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.226155713
Short name T687
Test name
Test status
Simulation time 95011032 ps
CPU time 1.2 seconds
Started Jul 22 04:38:26 PM PDT 24
Finished Jul 22 04:38:28 PM PDT 24
Peak memory 196040 kb
Host smart-1c46bff8-1087-495b-8390-2de3e45366b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226155713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.226155713
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.118375584
Short name T600
Test name
Test status
Simulation time 26023761087 ps
CPU time 200.08 seconds
Started Jul 22 04:38:27 PM PDT 24
Finished Jul 22 04:41:48 PM PDT 24
Peak memory 198532 kb
Host smart-2dadba89-028e-4773-901f-ec79f8e507ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118375584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.118375584
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.528956423
Short name T396
Test name
Test status
Simulation time 54428664711 ps
CPU time 632.24 seconds
Started Jul 22 04:38:30 PM PDT 24
Finished Jul 22 04:49:03 PM PDT 24
Peak memory 198724 kb
Host smart-bb817f0d-49ad-4250-be35-5808d5a6e803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=528956423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.528956423
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.848618383
Short name T878
Test name
Test status
Simulation time 33302674 ps
CPU time 0.78 seconds
Started Jul 22 04:36:17 PM PDT 24
Finished Jul 22 04:36:18 PM PDT 24
Peak memory 191564 kb
Host smart-fa8f306a-441a-4fb3-aaf8-0b217b4b3763
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=848618383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.848618383
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2464074632
Short name T913
Test name
Test status
Simulation time 33235640 ps
CPU time 0.83 seconds
Started Jul 22 04:36:17 PM PDT 24
Finished Jul 22 04:36:18 PM PDT 24
Peak memory 191540 kb
Host smart-30e04816-5555-4973-a8e0-ced7669e4750
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464074632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2464074632
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.868920941
Short name T859
Test name
Test status
Simulation time 37838547 ps
CPU time 1.07 seconds
Started Jul 22 04:36:35 PM PDT 24
Finished Jul 22 04:36:36 PM PDT 24
Peak memory 191628 kb
Host smart-e2131f89-9ebd-4634-935f-ffed51aa61b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=868920941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.868920941
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3010829418
Short name T858
Test name
Test status
Simulation time 85889379 ps
CPU time 1.38 seconds
Started Jul 22 04:36:16 PM PDT 24
Finished Jul 22 04:36:18 PM PDT 24
Peak memory 197996 kb
Host smart-8ffc9275-67d0-40da-bb3b-6e2e1fb8ca83
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010829418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3010829418
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.958967863
Short name T917
Test name
Test status
Simulation time 146911640 ps
CPU time 1.26 seconds
Started Jul 22 04:36:39 PM PDT 24
Finished Jul 22 04:36:41 PM PDT 24
Peak memory 191680 kb
Host smart-53eaec8a-e417-4345-9d5b-381a3487d571
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=958967863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.958967863
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1587831497
Short name T862
Test name
Test status
Simulation time 40789875 ps
CPU time 1.21 seconds
Started Jul 22 04:36:43 PM PDT 24
Finished Jul 22 04:36:45 PM PDT 24
Peak memory 197476 kb
Host smart-eeace7ea-3a17-4068-b37c-18b6da7509af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587831497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1587831497
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2679881353
Short name T927
Test name
Test status
Simulation time 224470384 ps
CPU time 1.27 seconds
Started Jul 22 04:36:43 PM PDT 24
Finished Jul 22 04:36:45 PM PDT 24
Peak memory 191740 kb
Host smart-9e2e8824-b233-45aa-8343-c551e2241cdb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2679881353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2679881353
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3961169497
Short name T847
Test name
Test status
Simulation time 182736571 ps
CPU time 0.91 seconds
Started Jul 22 04:37:23 PM PDT 24
Finished Jul 22 04:37:24 PM PDT 24
Peak memory 191468 kb
Host smart-f1e24968-dd1b-43fd-a551-7b24c57d6300
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961169497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3961169497
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2232432166
Short name T889
Test name
Test status
Simulation time 69339923 ps
CPU time 1.47 seconds
Started Jul 22 04:36:38 PM PDT 24
Finished Jul 22 04:36:40 PM PDT 24
Peak memory 191740 kb
Host smart-4ff92fb6-5d01-4389-ad25-295605177fdf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2232432166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2232432166
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2438868349
Short name T906
Test name
Test status
Simulation time 106200074 ps
CPU time 1.3 seconds
Started Jul 22 04:37:10 PM PDT 24
Finished Jul 22 04:37:12 PM PDT 24
Peak memory 191748 kb
Host smart-44965d3c-94fc-4de4-8f18-ab6fcd8ddc17
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438868349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2438868349
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2916121538
Short name T875
Test name
Test status
Simulation time 161522147 ps
CPU time 1.37 seconds
Started Jul 22 04:36:47 PM PDT 24
Finished Jul 22 04:36:49 PM PDT 24
Peak memory 191684 kb
Host smart-000fb10c-1715-4c21-97fc-7ca0e33e979c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2916121538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2916121538
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2281927578
Short name T920
Test name
Test status
Simulation time 71721812 ps
CPU time 1.31 seconds
Started Jul 22 04:36:47 PM PDT 24
Finished Jul 22 04:36:49 PM PDT 24
Peak memory 198084 kb
Host smart-b6619d50-b922-421a-a8d4-a3183f090f06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281927578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2281927578
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3317304437
Short name T944
Test name
Test status
Simulation time 245374184 ps
CPU time 1.01 seconds
Started Jul 22 04:36:52 PM PDT 24
Finished Jul 22 04:36:54 PM PDT 24
Peak memory 191740 kb
Host smart-1c695894-4177-4218-afa9-403297e5ae55
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3317304437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3317304437
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4054858086
Short name T864
Test name
Test status
Simulation time 43412084 ps
CPU time 1.13 seconds
Started Jul 22 04:36:52 PM PDT 24
Finished Jul 22 04:36:54 PM PDT 24
Peak memory 198116 kb
Host smart-12af0d84-9798-4df8-a7ff-5984cdbc5af8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054858086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4054858086
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.158284532
Short name T886
Test name
Test status
Simulation time 123420632 ps
CPU time 1.15 seconds
Started Jul 22 04:36:52 PM PDT 24
Finished Jul 22 04:36:54 PM PDT 24
Peak memory 191712 kb
Host smart-1bd34c53-0191-44a8-8595-169d0df2bc43
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=158284532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.158284532
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1792569068
Short name T860
Test name
Test status
Simulation time 151626606 ps
CPU time 0.88 seconds
Started Jul 22 04:36:47 PM PDT 24
Finished Jul 22 04:36:48 PM PDT 24
Peak memory 196056 kb
Host smart-532c3842-b584-480a-839a-d0a0ee4b0b55
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792569068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1792569068
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1563154855
Short name T918
Test name
Test status
Simulation time 151425841 ps
CPU time 1.24 seconds
Started Jul 22 04:38:23 PM PDT 24
Finished Jul 22 04:38:24 PM PDT 24
Peak memory 191688 kb
Host smart-f44b9fca-8a77-4f19-8e7d-b0ea228c273d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1563154855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1563154855
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1415764017
Short name T925
Test name
Test status
Simulation time 109518704 ps
CPU time 1.32 seconds
Started Jul 22 04:36:54 PM PDT 24
Finished Jul 22 04:36:56 PM PDT 24
Peak memory 191740 kb
Host smart-44f4ec6d-b848-416d-b920-d4c6523787df
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415764017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1415764017
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.82748444
Short name T899
Test name
Test status
Simulation time 398482746 ps
CPU time 1 seconds
Started Jul 22 04:36:47 PM PDT 24
Finished Jul 22 04:36:49 PM PDT 24
Peak memory 191524 kb
Host smart-78ee30f1-2c16-48da-a302-8a2ebb502433
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=82748444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.82748444
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1258234302
Short name T895
Test name
Test status
Simulation time 182461377 ps
CPU time 1.23 seconds
Started Jul 22 04:36:48 PM PDT 24
Finished Jul 22 04:36:50 PM PDT 24
Peak memory 191688 kb
Host smart-264e751b-5d0f-4b43-afb1-0467be202f65
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258234302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1258234302
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2414892339
Short name T911
Test name
Test status
Simulation time 40283506 ps
CPU time 1.05 seconds
Started Jul 22 04:36:47 PM PDT 24
Finished Jul 22 04:36:49 PM PDT 24
Peak memory 191496 kb
Host smart-3aae8550-256a-4dab-ab69-f80c90c26976
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2414892339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2414892339
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2985686576
Short name T907
Test name
Test status
Simulation time 103845544 ps
CPU time 1.58 seconds
Started Jul 22 04:36:55 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 198072 kb
Host smart-2c671511-1196-4d00-9040-515e0abee842
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985686576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2985686576
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2939760829
Short name T888
Test name
Test status
Simulation time 197055079 ps
CPU time 1.16 seconds
Started Jul 22 04:36:56 PM PDT 24
Finished Jul 22 04:36:58 PM PDT 24
Peak memory 191700 kb
Host smart-d556e46b-fb3a-43f6-996a-0d7bc5268611
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2939760829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2939760829
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2472833056
Short name T908
Test name
Test status
Simulation time 119257195 ps
CPU time 1.49 seconds
Started Jul 22 04:36:55 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 191732 kb
Host smart-86ea581e-69b4-40ce-adea-9f200945ca04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472833056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2472833056
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2583926295
Short name T853
Test name
Test status
Simulation time 164719160 ps
CPU time 1.12 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:42 PM PDT 24
Peak memory 191188 kb
Host smart-b589df92-e74b-4d73-9de7-f512d5aa7238
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2583926295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2583926295
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2916977185
Short name T893
Test name
Test status
Simulation time 67059029 ps
CPU time 0.94 seconds
Started Jul 22 04:36:25 PM PDT 24
Finished Jul 22 04:36:27 PM PDT 24
Peak memory 191516 kb
Host smart-e8721cc8-c7e5-4664-b8f8-e1ed5c4e0e73
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916977185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2916977185
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1626632259
Short name T887
Test name
Test status
Simulation time 99447995 ps
CPU time 1.32 seconds
Started Jul 22 04:36:54 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 198084 kb
Host smart-53cddc3e-6cff-4b34-94c5-37f32bdaf28c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1626632259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1626632259
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2807669255
Short name T910
Test name
Test status
Simulation time 63516663 ps
CPU time 1.26 seconds
Started Jul 22 04:36:55 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 191684 kb
Host smart-3a3c4e94-6f2a-40fc-aeee-f30e564bf276
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807669255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2807669255
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2451740038
Short name T912
Test name
Test status
Simulation time 56871554 ps
CPU time 1.1 seconds
Started Jul 22 04:36:56 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 191620 kb
Host smart-e4b4d7bd-6a35-4103-ba3d-956fad55d069
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2451740038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2451740038
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.106227391
Short name T866
Test name
Test status
Simulation time 75567321 ps
CPU time 1.31 seconds
Started Jul 22 04:36:55 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 198112 kb
Host smart-ed869fb3-3af7-43b6-8b8d-9d249b84bd7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106227391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.106227391
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1384399604
Short name T882
Test name
Test status
Simulation time 262766667 ps
CPU time 1.27 seconds
Started Jul 22 04:36:57 PM PDT 24
Finished Jul 22 04:36:59 PM PDT 24
Peak memory 192012 kb
Host smart-6595adf8-a252-4edf-869f-049e1879af62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1384399604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1384399604
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.576040503
Short name T850
Test name
Test status
Simulation time 147861342 ps
CPU time 1.15 seconds
Started Jul 22 04:36:56 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 191716 kb
Host smart-d322ce3d-4919-4204-a299-7d5869403a21
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576040503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.576040503
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1288490061
Short name T936
Test name
Test status
Simulation time 110517229 ps
CPU time 1.53 seconds
Started Jul 22 04:36:56 PM PDT 24
Finished Jul 22 04:36:58 PM PDT 24
Peak memory 191604 kb
Host smart-c9b1eb15-41e5-453c-93af-ca83d92db123
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1288490061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1288490061
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2953165873
Short name T922
Test name
Test status
Simulation time 174395763 ps
CPU time 1.32 seconds
Started Jul 22 04:36:55 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 191744 kb
Host smart-622a4361-843d-4b92-9335-dd8b93c30322
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953165873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2953165873
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2578733041
Short name T861
Test name
Test status
Simulation time 40427382 ps
CPU time 0.89 seconds
Started Jul 22 04:36:57 PM PDT 24
Finished Jul 22 04:36:58 PM PDT 24
Peak memory 191472 kb
Host smart-787c76ac-101c-4805-b346-ae04cfe7dc0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2578733041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2578733041
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2319798957
Short name T940
Test name
Test status
Simulation time 321949074 ps
CPU time 1.51 seconds
Started Jul 22 04:36:55 PM PDT 24
Finished Jul 22 04:36:57 PM PDT 24
Peak memory 191696 kb
Host smart-caa401ad-de3e-4fad-b29e-28533e531f5d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319798957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2319798957
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3634194474
Short name T874
Test name
Test status
Simulation time 161338165 ps
CPU time 1.42 seconds
Started Jul 22 04:37:07 PM PDT 24
Finished Jul 22 04:37:09 PM PDT 24
Peak memory 191624 kb
Host smart-54e7f700-a165-4c65-a090-d3e9e397960c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3634194474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3634194474
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3037116261
Short name T857
Test name
Test status
Simulation time 393367536 ps
CPU time 1.66 seconds
Started Jul 22 04:37:05 PM PDT 24
Finished Jul 22 04:37:07 PM PDT 24
Peak memory 198004 kb
Host smart-daf38804-4b07-4f7d-abd5-06052802ddfc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037116261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3037116261
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.143589996
Short name T854
Test name
Test status
Simulation time 143981034 ps
CPU time 1.27 seconds
Started Jul 22 04:37:04 PM PDT 24
Finished Jul 22 04:37:05 PM PDT 24
Peak memory 191704 kb
Host smart-6e2ec04c-10f0-4176-87c4-5ef30cdbf6d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=143589996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.143589996
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.514479284
Short name T870
Test name
Test status
Simulation time 97680231 ps
CPU time 1.4 seconds
Started Jul 22 04:37:59 PM PDT 24
Finished Jul 22 04:38:01 PM PDT 24
Peak memory 191612 kb
Host smart-43dcfab8-80bb-4704-b167-85a55ffb3ef4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514479284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.514479284
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.791377630
Short name T915
Test name
Test status
Simulation time 49039762 ps
CPU time 1.38 seconds
Started Jul 22 04:37:06 PM PDT 24
Finished Jul 22 04:37:08 PM PDT 24
Peak memory 191764 kb
Host smart-ec2fb012-d410-4745-9ddd-5385955aa6ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=791377630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.791377630
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.869152496
Short name T855
Test name
Test status
Simulation time 73792724 ps
CPU time 1.08 seconds
Started Jul 22 04:37:05 PM PDT 24
Finished Jul 22 04:37:07 PM PDT 24
Peak memory 191700 kb
Host smart-09b906a8-382a-43ec-9ea1-db0d597cf8b6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869152496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.869152496
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1132912824
Short name T930
Test name
Test status
Simulation time 67878985 ps
CPU time 1.26 seconds
Started Jul 22 04:37:03 PM PDT 24
Finished Jul 22 04:37:05 PM PDT 24
Peak memory 191756 kb
Host smart-a85c1a20-58e5-429d-9dc9-ea1738d76519
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1132912824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1132912824
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3582476900
Short name T937
Test name
Test status
Simulation time 105426611 ps
CPU time 0.97 seconds
Started Jul 22 04:37:15 PM PDT 24
Finished Jul 22 04:37:17 PM PDT 24
Peak memory 197172 kb
Host smart-eb7e2d99-933a-40fa-8ef7-e94cdf741e72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582476900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3582476900
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3903477474
Short name T924
Test name
Test status
Simulation time 633116222 ps
CPU time 1.36 seconds
Started Jul 22 04:37:03 PM PDT 24
Finished Jul 22 04:37:05 PM PDT 24
Peak memory 198048 kb
Host smart-6ed7a691-d1d7-47b1-9a1e-f95b97165483
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3903477474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3903477474
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.138689847
Short name T876
Test name
Test status
Simulation time 38401524 ps
CPU time 0.92 seconds
Started Jul 22 04:37:06 PM PDT 24
Finished Jul 22 04:37:07 PM PDT 24
Peak memory 196128 kb
Host smart-812d4094-5f96-4d83-824f-115e1492f123
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138689847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.138689847
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3876582972
Short name T935
Test name
Test status
Simulation time 51880777 ps
CPU time 0.72 seconds
Started Jul 22 04:36:26 PM PDT 24
Finished Jul 22 04:36:27 PM PDT 24
Peak memory 195196 kb
Host smart-2dc0487e-bfeb-44b4-b448-1eee3aea6703
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3876582972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3876582972
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3707485032
Short name T903
Test name
Test status
Simulation time 80398724 ps
CPU time 1.61 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:43 PM PDT 24
Peak memory 191324 kb
Host smart-d63e29b8-0d96-4548-a3c1-e01b2ad25374
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707485032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3707485032
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3000891861
Short name T885
Test name
Test status
Simulation time 674262333 ps
CPU time 1.03 seconds
Started Jul 22 04:37:06 PM PDT 24
Finished Jul 22 04:37:08 PM PDT 24
Peak memory 191740 kb
Host smart-b5eb90e4-80c8-4f67-b5ac-ed1a75a8cd0e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3000891861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3000891861
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.688956428
Short name T848
Test name
Test status
Simulation time 216771763 ps
CPU time 1.22 seconds
Started Jul 22 04:37:26 PM PDT 24
Finished Jul 22 04:37:28 PM PDT 24
Peak memory 191696 kb
Host smart-714375a3-e331-493e-a18b-6e815b15f0f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688956428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.688956428
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4161985401
Short name T867
Test name
Test status
Simulation time 55500267 ps
CPU time 1.33 seconds
Started Jul 22 04:37:04 PM PDT 24
Finished Jul 22 04:37:05 PM PDT 24
Peak memory 191704 kb
Host smart-ee3e2893-f143-45c6-a02e-33227e06b794
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4161985401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.4161985401
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2226602242
Short name T904
Test name
Test status
Simulation time 28892555 ps
CPU time 0.91 seconds
Started Jul 22 04:37:06 PM PDT 24
Finished Jul 22 04:37:07 PM PDT 24
Peak memory 191484 kb
Host smart-72d14b50-151c-4067-999c-2fdcfa2d1193
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226602242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2226602242
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2673791317
Short name T923
Test name
Test status
Simulation time 292208956 ps
CPU time 1.27 seconds
Started Jul 22 04:37:05 PM PDT 24
Finished Jul 22 04:37:07 PM PDT 24
Peak memory 191696 kb
Host smart-bf803763-bf0f-4440-9628-6184616cabbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2673791317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2673791317
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1388340367
Short name T941
Test name
Test status
Simulation time 69268907 ps
CPU time 0.89 seconds
Started Jul 22 04:37:06 PM PDT 24
Finished Jul 22 04:37:08 PM PDT 24
Peak memory 191524 kb
Host smart-7ece4a95-bf49-426e-9164-5b507a83e6b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388340367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1388340367
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1823289801
Short name T869
Test name
Test status
Simulation time 263254975 ps
CPU time 1.39 seconds
Started Jul 22 04:37:05 PM PDT 24
Finished Jul 22 04:37:07 PM PDT 24
Peak memory 191700 kb
Host smart-a71665a3-0b85-4b78-a001-dd4d5bb8066a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1823289801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1823289801
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1772505147
Short name T897
Test name
Test status
Simulation time 68218031 ps
CPU time 0.99 seconds
Started Jul 22 04:37:07 PM PDT 24
Finished Jul 22 04:37:09 PM PDT 24
Peak memory 191660 kb
Host smart-e3dc63aa-86cd-4525-9d52-f28997b605fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772505147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1772505147
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2269709892
Short name T933
Test name
Test status
Simulation time 39564377 ps
CPU time 1.07 seconds
Started Jul 22 04:37:06 PM PDT 24
Finished Jul 22 04:37:08 PM PDT 24
Peak memory 191508 kb
Host smart-7b815501-d759-4497-9fd7-f09cb2020803
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2269709892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2269709892
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1213139252
Short name T868
Test name
Test status
Simulation time 34689631 ps
CPU time 0.94 seconds
Started Jul 22 04:37:05 PM PDT 24
Finished Jul 22 04:37:06 PM PDT 24
Peak memory 197324 kb
Host smart-282e643e-4e8c-41e7-bfe9-aa08bd92b06e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213139252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1213139252
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.564663154
Short name T846
Test name
Test status
Simulation time 90345760 ps
CPU time 1.37 seconds
Started Jul 22 04:37:17 PM PDT 24
Finished Jul 22 04:37:19 PM PDT 24
Peak memory 198092 kb
Host smart-99460cf6-bf99-4251-b191-4b2e27ccf323
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=564663154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.564663154
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.914054679
Short name T883
Test name
Test status
Simulation time 55582646 ps
CPU time 1.66 seconds
Started Jul 22 04:37:27 PM PDT 24
Finished Jul 22 04:37:29 PM PDT 24
Peak memory 198008 kb
Host smart-944b7383-ce79-4bb4-8af3-4cc946e82a18
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914054679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.914054679
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2044266236
Short name T914
Test name
Test status
Simulation time 49370300 ps
CPU time 1.04 seconds
Started Jul 22 04:37:15 PM PDT 24
Finished Jul 22 04:37:17 PM PDT 24
Peak memory 191756 kb
Host smart-11932bc5-78ab-4dca-8d88-ed607180ca88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2044266236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2044266236
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1024817628
Short name T921
Test name
Test status
Simulation time 88717535 ps
CPU time 1.4 seconds
Started Jul 22 04:37:15 PM PDT 24
Finished Jul 22 04:37:17 PM PDT 24
Peak memory 191708 kb
Host smart-70b983a6-4eeb-427f-a767-7357a97833e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024817628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1024817628
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1037776996
Short name T896
Test name
Test status
Simulation time 43266651 ps
CPU time 1.1 seconds
Started Jul 22 04:37:15 PM PDT 24
Finished Jul 22 04:37:16 PM PDT 24
Peak memory 191712 kb
Host smart-c287d79c-cb8a-4887-970d-8b96844d4eaf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1037776996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1037776996
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3631124511
Short name T909
Test name
Test status
Simulation time 75739859 ps
CPU time 1.41 seconds
Started Jul 22 04:37:39 PM PDT 24
Finished Jul 22 04:37:41 PM PDT 24
Peak memory 198020 kb
Host smart-69b1ff12-7e45-42ee-b815-ca52f08798d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631124511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3631124511
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1854994210
Short name T929
Test name
Test status
Simulation time 43248529 ps
CPU time 1.25 seconds
Started Jul 22 04:37:15 PM PDT 24
Finished Jul 22 04:37:17 PM PDT 24
Peak memory 191696 kb
Host smart-4b8883f4-35f5-457b-a52e-cd5434574346
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1854994210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1854994210
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3720012738
Short name T863
Test name
Test status
Simulation time 161784757 ps
CPU time 1.13 seconds
Started Jul 22 04:37:13 PM PDT 24
Finished Jul 22 04:37:15 PM PDT 24
Peak memory 198132 kb
Host smart-8c5d1509-3474-4096-a7b3-afc35883e7d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720012738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3720012738
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3577461132
Short name T943
Test name
Test status
Simulation time 60825605 ps
CPU time 1.37 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:26 PM PDT 24
Peak memory 191680 kb
Host smart-8b6ffbc7-64d5-4423-b056-eadc0a97121b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3577461132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3577461132
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.561876764
Short name T856
Test name
Test status
Simulation time 234307757 ps
CPU time 1.32 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:26 PM PDT 24
Peak memory 191688 kb
Host smart-ed3133cf-9dc2-4a06-b7a3-3589c5ebb4ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561876764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.561876764
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1656804817
Short name T880
Test name
Test status
Simulation time 277966579 ps
CPU time 1.13 seconds
Started Jul 22 04:36:26 PM PDT 24
Finished Jul 22 04:36:28 PM PDT 24
Peak memory 191700 kb
Host smart-5af3aecd-704e-472a-af1d-8df74e87d786
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1656804817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1656804817
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3012923807
Short name T884
Test name
Test status
Simulation time 229766980 ps
CPU time 1.25 seconds
Started Jul 22 04:36:26 PM PDT 24
Finished Jul 22 04:36:27 PM PDT 24
Peak memory 191640 kb
Host smart-de9843d1-c347-4500-b2ab-0422ba51eefd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012923807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3012923807
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4126142843
Short name T852
Test name
Test status
Simulation time 151554563 ps
CPU time 1.16 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:26 PM PDT 24
Peak memory 191704 kb
Host smart-58eba9ea-8331-4164-82be-b01793f1c057
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4126142843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4126142843
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.111240466
Short name T873
Test name
Test status
Simulation time 129895699 ps
CPU time 0.79 seconds
Started Jul 22 04:37:23 PM PDT 24
Finished Jul 22 04:37:24 PM PDT 24
Peak memory 191520 kb
Host smart-7fc2c080-42dc-44c1-b518-bbe035aa3e74
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111240466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.111240466
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3135024050
Short name T939
Test name
Test status
Simulation time 222002675 ps
CPU time 1.06 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:25 PM PDT 24
Peak memory 191752 kb
Host smart-d74f0372-da3b-4ffd-a368-1a556b37b15e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3135024050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3135024050
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1046931964
Short name T879
Test name
Test status
Simulation time 418347349 ps
CPU time 1.05 seconds
Started Jul 22 04:37:26 PM PDT 24
Finished Jul 22 04:37:28 PM PDT 24
Peak memory 191740 kb
Host smart-fdbcce25-9e06-4aba-84ef-e6e6e515b017
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046931964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1046931964
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1601636401
Short name T871
Test name
Test status
Simulation time 773424556 ps
CPU time 1.49 seconds
Started Jul 22 04:37:23 PM PDT 24
Finished Jul 22 04:37:25 PM PDT 24
Peak memory 198088 kb
Host smart-44c334fc-9669-4357-8ab1-c688da6368cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1601636401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1601636401
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3542421272
Short name T931
Test name
Test status
Simulation time 163146797 ps
CPU time 1.42 seconds
Started Jul 22 04:37:40 PM PDT 24
Finished Jul 22 04:37:42 PM PDT 24
Peak memory 191624 kb
Host smart-d51b9a68-8b1b-48c7-885b-7e8da2cc1ffd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542421272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3542421272
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.407711730
Short name T877
Test name
Test status
Simulation time 185883104 ps
CPU time 1.21 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:27 PM PDT 24
Peak memory 198048 kb
Host smart-75e8b972-69b3-4422-8733-964cb26e97da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=407711730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.407711730
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1719850426
Short name T890
Test name
Test status
Simulation time 167858634 ps
CPU time 1.19 seconds
Started Jul 22 04:37:25 PM PDT 24
Finished Jul 22 04:37:27 PM PDT 24
Peak memory 191672 kb
Host smart-d94c59fc-c1c2-4a78-bca9-71a7a34df265
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719850426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1719850426
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2089648659
Short name T865
Test name
Test status
Simulation time 90635766 ps
CPU time 1.24 seconds
Started Jul 22 04:37:25 PM PDT 24
Finished Jul 22 04:37:27 PM PDT 24
Peak memory 191604 kb
Host smart-a0369eac-7cb8-4daf-9533-00a1627edf20
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2089648659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2089648659
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1348949951
Short name T892
Test name
Test status
Simulation time 22106813 ps
CPU time 0.7 seconds
Started Jul 22 04:37:23 PM PDT 24
Finished Jul 22 04:37:24 PM PDT 24
Peak memory 195036 kb
Host smart-35dd7887-5f93-4a8c-a908-5c9738699f3f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348949951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1348949951
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.757383400
Short name T881
Test name
Test status
Simulation time 73237401 ps
CPU time 1.43 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:27 PM PDT 24
Peak memory 198052 kb
Host smart-d6328f88-c911-49b0-a7fe-5aa1645a07d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=757383400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.757383400
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.296950297
Short name T872
Test name
Test status
Simulation time 65029184 ps
CPU time 1.25 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:26 PM PDT 24
Peak memory 198096 kb
Host smart-1c1a39f3-7da1-4f2e-9d0b-7c2ad42a1f44
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296950297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.296950297
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4085599998
Short name T845
Test name
Test status
Simulation time 49264245 ps
CPU time 0.88 seconds
Started Jul 22 04:37:25 PM PDT 24
Finished Jul 22 04:37:27 PM PDT 24
Peak memory 191516 kb
Host smart-65ccc0d8-4377-40ce-b07d-23f733fae582
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4085599998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.4085599998
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1315252617
Short name T928
Test name
Test status
Simulation time 179392385 ps
CPU time 1.39 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:27 PM PDT 24
Peak memory 191688 kb
Host smart-4aabb383-8376-4f00-9186-885bf24b7f1d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315252617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1315252617
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1687734923
Short name T851
Test name
Test status
Simulation time 50831179 ps
CPU time 1 seconds
Started Jul 22 04:37:23 PM PDT 24
Finished Jul 22 04:37:25 PM PDT 24
Peak memory 197180 kb
Host smart-e8f916c3-d603-4b98-b9f5-376071f76197
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1687734923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1687734923
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3027610300
Short name T901
Test name
Test status
Simulation time 27943304 ps
CPU time 0.79 seconds
Started Jul 22 04:37:26 PM PDT 24
Finished Jul 22 04:37:28 PM PDT 24
Peak memory 191524 kb
Host smart-6b89ae68-67d3-4ce2-9f9e-dec71fb14ac7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027610300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3027610300
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.723338387
Short name T938
Test name
Test status
Simulation time 60295492 ps
CPU time 1.33 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:26 PM PDT 24
Peak memory 191720 kb
Host smart-a9e6d8c0-8b7e-4ec8-8b2a-12cbc7f8e988
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=723338387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.723338387
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2905008296
Short name T894
Test name
Test status
Simulation time 731823330 ps
CPU time 1.12 seconds
Started Jul 22 04:37:26 PM PDT 24
Finished Jul 22 04:37:28 PM PDT 24
Peak memory 192012 kb
Host smart-66e3554e-540a-4965-954c-a922014f9c4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905008296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2905008296
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.721732260
Short name T916
Test name
Test status
Simulation time 120520696 ps
CPU time 1.22 seconds
Started Jul 22 04:37:24 PM PDT 24
Finished Jul 22 04:37:27 PM PDT 24
Peak memory 191624 kb
Host smart-3ef27b52-e93a-4284-9148-a1234df05e6f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=721732260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.721732260
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2428496743
Short name T934
Test name
Test status
Simulation time 78110414 ps
CPU time 1.55 seconds
Started Jul 22 04:37:33 PM PDT 24
Finished Jul 22 04:37:35 PM PDT 24
Peak memory 191668 kb
Host smart-d3b82b4d-33ae-4d54-9b81-fb1c9987072c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428496743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2428496743
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3963546373
Short name T942
Test name
Test status
Simulation time 206620600 ps
CPU time 1.11 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:42 PM PDT 24
Peak memory 191416 kb
Host smart-0cea52a6-a433-4a16-9a82-faa164f47e2b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3963546373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3963546373
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.796715531
Short name T849
Test name
Test status
Simulation time 67488813 ps
CPU time 1.15 seconds
Started Jul 22 04:36:25 PM PDT 24
Finished Jul 22 04:36:26 PM PDT 24
Peak memory 198064 kb
Host smart-51196f2e-8125-4ca8-9970-14d4548c4b48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796715531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.796715531
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.680445850
Short name T900
Test name
Test status
Simulation time 127847597 ps
CPU time 0.81 seconds
Started Jul 22 04:36:25 PM PDT 24
Finished Jul 22 04:36:27 PM PDT 24
Peak memory 191532 kb
Host smart-446bda1a-d605-400e-b436-32b2081ab077
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=680445850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.680445850
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2224548393
Short name T891
Test name
Test status
Simulation time 640166904 ps
CPU time 1.21 seconds
Started Jul 22 04:36:26 PM PDT 24
Finished Jul 22 04:36:28 PM PDT 24
Peak memory 191624 kb
Host smart-fb8df7fb-e8f3-4450-a9cc-a83721de615a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224548393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2224548393
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2920584391
Short name T926
Test name
Test status
Simulation time 50604971 ps
CPU time 1.11 seconds
Started Jul 22 04:36:39 PM PDT 24
Finished Jul 22 04:36:41 PM PDT 24
Peak memory 198088 kb
Host smart-db095403-0004-4fef-81de-a15a219432df
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2920584391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2920584391
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3036319073
Short name T919
Test name
Test status
Simulation time 26861902 ps
CPU time 0.98 seconds
Started Jul 22 04:37:41 PM PDT 24
Finished Jul 22 04:37:42 PM PDT 24
Peak memory 191400 kb
Host smart-a841dca3-d6b8-4a0f-87e8-42fbd046a85b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036319073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3036319073
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1264983847
Short name T932
Test name
Test status
Simulation time 165367406 ps
CPU time 0.94 seconds
Started Jul 22 04:36:43 PM PDT 24
Finished Jul 22 04:36:44 PM PDT 24
Peak memory 197212 kb
Host smart-c1d6aba4-6c9e-49d7-9d6d-b09e04cd9389
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1264983847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1264983847
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3206185410
Short name T898
Test name
Test status
Simulation time 74981645 ps
CPU time 1.31 seconds
Started Jul 22 04:36:38 PM PDT 24
Finished Jul 22 04:36:40 PM PDT 24
Peak memory 191640 kb
Host smart-5e0d0323-c74f-42c8-9fe6-ad5c16f8cfe6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206185410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3206185410
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.998254592
Short name T905
Test name
Test status
Simulation time 554197956 ps
CPU time 0.88 seconds
Started Jul 22 04:36:40 PM PDT 24
Finished Jul 22 04:36:42 PM PDT 24
Peak memory 196200 kb
Host smart-3d915a57-a89a-4e1d-b2ce-dc9bbb76dd6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=998254592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.998254592
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2884433813
Short name T902
Test name
Test status
Simulation time 37145328 ps
CPU time 0.85 seconds
Started Jul 22 04:36:40 PM PDT 24
Finished Jul 22 04:36:41 PM PDT 24
Peak memory 191488 kb
Host smart-5f62909c-e66f-49ed-8590-4401d52cf2a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884433813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2884433813
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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