Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3501387	1			T20	1		T21	835		T22	1
all_pins[1]	3501387	1			T20	1		T21	835		T22	1
all_pins[2]	3501387	1			T20	1		T21	835		T22	1
all_pins[3]	3501387	1			T20	1		T21	835		T22	1
all_pins[4]	3501387	1			T20	1		T21	835		T22	1
all_pins[5]	3501387	1			T20	1		T21	835		T22	1
all_pins[6]	3501387	1			T20	1		T21	835		T22	1
all_pins[7]	3501387	1			T20	1		T21	835		T22	1
all_pins[8]	3501387	1			T20	1		T21	835		T22	1
all_pins[9]	3501387	1			T20	1		T21	835		T22	1
all_pins[10]	3501387	1			T20	1		T21	835		T22	1
all_pins[11]	3501387	1			T20	1		T21	835		T22	1
all_pins[12]	3501387	1			T20	1		T21	835		T22	1
all_pins[13]	3501387	1			T20	1		T21	835		T22	1
all_pins[14]	3501387	1			T20	1		T21	835		T22	1
all_pins[15]	3501387	1			T20	1		T21	835		T22	1
all_pins[16]	3501387	1			T20	1		T21	835		T22	1
all_pins[17]	3501387	1			T20	1		T21	835		T22	1
all_pins[18]	3501387	1			T20	1		T21	835		T22	1
all_pins[19]	3501387	1			T20	1		T21	835		T22	1
all_pins[20]	3501387	1			T20	1		T21	835		T22	1
all_pins[21]	3501387	1			T20	1		T21	835		T22	1
all_pins[22]	3501387	1			T20	1		T21	835		T22	1
all_pins[23]	3501387	1			T20	1		T21	835		T22	1
all_pins[24]	3501387	1			T20	1		T21	835		T22	1
all_pins[25]	3501387	1			T20	1		T21	835		T22	1
all_pins[26]	3501387	1			T20	1		T21	835		T22	1
all_pins[27]	3501387	1			T20	1		T21	835		T22	1
all_pins[28]	3501387	1			T20	1		T21	835		T22	1
all_pins[29]	3501387	1			T20	1		T21	835		T22	1
all_pins[30]	3501387	1			T20	1		T21	835		T22	1
all_pins[31]	3501387	1			T20	1		T21	835		T22	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	69581412	1			T20	32		T21	16737		T22	32
values[0x1]	42462972	1			T21	9983		T23	1119		T24	1034
transitions[0x0=>0x1]	25432795	1			T21	6112		T23	538		T24	645
transitions[0x1=>0x0]	25432653	1			T21	6112		T23	538		T24	644

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2172747	1			T20	1		T21	584		T22	1
all_pins[0]	values[0x1]	1328640	1			T21	251		T23	38		T24	50
all_pins[0]	transitions[0x0=>0x1]	824266	1			T21	155		T23	18		T24	43
all_pins[0]	transitions[0x1=>0x0]	822058	1			T21	299		T23	21		T24	19
all_pins[1]	values[0x0]	2172568	1			T20	1		T21	596		T22	1
all_pins[1]	values[0x1]	1328819	1			T21	239		T23	26		T24	17
all_pins[1]	transitions[0x0=>0x1]	793082	1			T21	164		T23	9		T24	6
all_pins[1]	transitions[0x1=>0x0]	792903	1			T21	176		T23	21		T24	39
all_pins[2]	values[0x0]	2171951	1			T20	1		T21	583		T22	1
all_pins[2]	values[0x1]	1329436	1			T21	252		T23	38		T24	12
all_pins[2]	transitions[0x0=>0x1]	795468	1			T21	169		T23	25		T24	12
all_pins[2]	transitions[0x1=>0x0]	794851	1			T21	156		T23	13		T24	17
all_pins[3]	values[0x0]	2170548	1			T20	1		T21	427		T22	1
all_pins[3]	values[0x1]	1330839	1			T21	408		T23	28		T24	24
all_pins[3]	transitions[0x0=>0x1]	796828	1			T21	287		T23	13		T24	22
all_pins[3]	transitions[0x1=>0x0]	795425	1			T21	131		T23	23		T24	10
all_pins[4]	values[0x0]	2173420	1			T20	1		T21	608		T22	1
all_pins[4]	values[0x1]	1327967	1			T21	227		T23	34		T24	35
all_pins[4]	transitions[0x0=>0x1]	793228	1			T21	78		T23	19		T24	17
all_pins[4]	transitions[0x1=>0x0]	796100	1			T21	259		T23	13		T24	6
all_pins[5]	values[0x0]	2174293	1			T20	1		T21	549		T22	1
all_pins[5]	values[0x1]	1327094	1			T21	286		T23	31		T24	42
all_pins[5]	transitions[0x0=>0x1]	793214	1			T21	207		T23	15		T24	23
all_pins[5]	transitions[0x1=>0x0]	794087	1			T21	148		T23	18		T24	16
all_pins[6]	values[0x0]	2177168	1			T20	1		T21	520		T22	1
all_pins[6]	values[0x1]	1324219	1			T21	315		T23	32		T24	45
all_pins[6]	transitions[0x0=>0x1]	790356	1			T21	189		T23	17		T24	28
all_pins[6]	transitions[0x1=>0x0]	793231	1			T21	160		T23	16		T24	25
all_pins[7]	values[0x0]	2172333	1			T20	1		T21	429		T22	1
all_pins[7]	values[0x1]	1329054	1			T21	406		T23	37		T24	38
all_pins[7]	transitions[0x0=>0x1]	796415	1			T21	270		T23	23		T24	16
all_pins[7]	transitions[0x1=>0x0]	791580	1			T21	179		T23	18		T24	23
all_pins[8]	values[0x0]	2175737	1			T20	1		T21	494		T22	1
all_pins[8]	values[0x1]	1325650	1			T21	341		T23	35		T24	45
all_pins[8]	transitions[0x0=>0x1]	791726	1			T21	225		T23	17		T24	25
all_pins[8]	transitions[0x1=>0x0]	795130	1			T21	290		T23	19		T24	18
all_pins[9]	values[0x0]	2178163	1			T20	1		T21	590		T22	1
all_pins[9]	values[0x1]	1323224	1			T21	245		T23	40		T24	27
all_pins[9]	transitions[0x0=>0x1]	791557	1			T21	144		T23	15		T24	19
all_pins[9]	transitions[0x1=>0x0]	793983	1			T21	240		T23	10		T24	37
all_pins[10]	values[0x0]	2172629	1			T20	1		T21	569		T22	1
all_pins[10]	values[0x1]	1328758	1			T21	266		T23	35		T24	37
all_pins[10]	transitions[0x0=>0x1]	797638	1			T21	198		T23	13		T24	19
all_pins[10]	transitions[0x1=>0x0]	792104	1			T21	177		T23	18		T24	9
all_pins[11]	values[0x0]	2173202	1			T20	1		T21	539		T22	1
all_pins[11]	values[0x1]	1328185	1			T21	296		T23	42		T24	46
all_pins[11]	transitions[0x0=>0x1]	791870	1			T21	152		T23	19		T24	27
all_pins[11]	transitions[0x1=>0x0]	792443	1			T21	122		T23	12		T24	18
all_pins[12]	values[0x0]	2172199	1			T20	1		T21	523		T22	1
all_pins[12]	values[0x1]	1329188	1			T21	312		T23	41		T24	25
all_pins[12]	transitions[0x0=>0x1]	794539	1			T21	183		T23	19		T24	11
all_pins[12]	transitions[0x1=>0x0]	793536	1			T21	167		T23	20		T24	32
all_pins[13]	values[0x0]	2178346	1			T20	1		T21	470		T22	1
all_pins[13]	values[0x1]	1323041	1			T21	365		T23	37		T24	23
all_pins[13]	transitions[0x0=>0x1]	790621	1			T21	217		T23	16		T24	10
all_pins[13]	transitions[0x1=>0x0]	796768	1			T21	164		T23	20		T24	12
all_pins[14]	values[0x0]	2175620	1			T20	1		T21	556		T22	1
all_pins[14]	values[0x1]	1325767	1			T21	279		T23	33		T24	8
all_pins[14]	transitions[0x0=>0x1]	793499	1			T21	147		T23	15		T24	4
all_pins[14]	transitions[0x1=>0x0]	790773	1			T21	233		T23	19		T24	19
all_pins[15]	values[0x0]	2169472	1			T20	1		T21	552		T22	1
all_pins[15]	values[0x1]	1331915	1			T21	283		T23	41		T24	10
all_pins[15]	transitions[0x0=>0x1]	797758	1			T21	205		T23	18		T24	8
all_pins[15]	transitions[0x1=>0x0]	791610	1			T21	201		T23	10		T24	6
all_pins[16]	values[0x0]	2174586	1			T20	1		T21	516		T22	1
all_pins[16]	values[0x1]	1326801	1			T21	319		T23	40		T24	20
all_pins[16]	transitions[0x0=>0x1]	794807	1			T21	231		T23	17		T24	17
all_pins[16]	transitions[0x1=>0x0]	799921	1			T21	195		T23	18		T24	7
all_pins[17]	values[0x0]	2171303	1			T20	1		T21	509		T22	1
all_pins[17]	values[0x1]	1330084	1			T21	326		T23	33		T24	32
all_pins[17]	transitions[0x0=>0x1]	794995	1			T21	202		T23	12		T24	25
all_pins[17]	transitions[0x1=>0x0]	791712	1			T21	195		T23	19		T24	13
all_pins[18]	values[0x0]	2178192	1			T20	1		T21	467		T22	1
all_pins[18]	values[0x1]	1323195	1			T21	368		T23	31		T24	5
all_pins[18]	transitions[0x0=>0x1]	793390	1			T21	200		T23	19		T24	3
all_pins[18]	transitions[0x1=>0x0]	800279	1			T21	158		T23	21		T24	30
all_pins[19]	values[0x0]	2172877	1			T20	1		T21	499		T22	1
all_pins[19]	values[0x1]	1328510	1			T21	336		T23	35		T24	27
all_pins[19]	transitions[0x0=>0x1]	794791	1			T21	175		T23	16		T24	27
all_pins[19]	transitions[0x1=>0x0]	789476	1			T21	207		T23	12		T24	5
all_pins[20]	values[0x0]	2174421	1			T20	1		T21	429		T22	1
all_pins[20]	values[0x1]	1326966	1			T21	406		T23	35		T24	66
all_pins[20]	transitions[0x0=>0x1]	792827	1			T21	202		T23	20		T24	47
all_pins[20]	transitions[0x1=>0x0]	794371	1			T21	132		T23	20		T24	8
all_pins[21]	values[0x0]	2173903	1			T20	1		T21	496		T22	1
all_pins[21]	values[0x1]	1327484	1			T21	339		T23	35		T24	34
all_pins[21]	transitions[0x0=>0x1]	794044	1			T21	144		T23	17		T24	19
all_pins[21]	transitions[0x1=>0x0]	793526	1			T21	211		T23	17		T24	51
all_pins[22]	values[0x0]	2174908	1			T20	1		T21	551		T22	1
all_pins[22]	values[0x1]	1326479	1			T21	284		T23	32		T24	43
all_pins[22]	transitions[0x0=>0x1]	794329	1			T21	191		T23	15		T24	23
all_pins[22]	transitions[0x1=>0x0]	795334	1			T21	246		T23	18		T24	14
all_pins[23]	values[0x0]	2176888	1			T20	1		T21	520		T22	1
all_pins[23]	values[0x1]	1324499	1			T21	315		T23	38		T24	35
all_pins[23]	transitions[0x0=>0x1]	791229	1			T21	197		T23	18		T24	20
all_pins[23]	transitions[0x1=>0x0]	793209	1			T21	166		T23	12		T24	28
all_pins[24]	values[0x0]	2179062	1			T20	1		T21	572		T22	1
all_pins[24]	values[0x1]	1322325	1			T21	263		T23	31		T24	44
all_pins[24]	transitions[0x0=>0x1]	790629	1			T21	169		T23	11		T24	28
all_pins[24]	transitions[0x1=>0x0]	792803	1			T21	221		T23	18		T24	19
all_pins[25]	values[0x0]	2171147	1			T20	1		T21	498		T22	1
all_pins[25]	values[0x1]	1330240	1			T21	337		T23	31		T24	45
all_pins[25]	transitions[0x0=>0x1]	798491	1			T21	221		T23	18		T24	22
all_pins[25]	transitions[0x1=>0x0]	790576	1			T21	147		T23	18		T24	21
all_pins[26]	values[0x0]	2178642	1			T20	1		T21	504		T22	1
all_pins[26]	values[0x1]	1322745	1			T21	331		T23	35		T24	44
all_pins[26]	transitions[0x0=>0x1]	792527	1			T21	208		T23	18		T24	21
all_pins[26]	transitions[0x1=>0x0]	800022	1			T21	214		T23	14		T24	22
all_pins[27]	values[0x0]	2173292	1			T20	1		T21	582		T22	1
all_pins[27]	values[0x1]	1328095	1			T21	253		T23	33		T24	29
all_pins[27]	transitions[0x0=>0x1]	797708	1			T21	168		T23	16		T24	16
all_pins[27]	transitions[0x1=>0x0]	792358	1			T21	246		T23	18		T24	31
all_pins[28]	values[0x0]	2175548	1			T20	1		T21	532		T22	1
all_pins[28]	values[0x1]	1325839	1			T21	303		T23	34		T24	39
all_pins[28]	transitions[0x0=>0x1]	791404	1			T21	195		T23	17		T24	34
all_pins[28]	transitions[0x1=>0x0]	793660	1			T21	145		T23	16		T24	24
all_pins[29]	values[0x0]	2174801	1			T20	1		T21	484		T22	1
all_pins[29]	values[0x1]	1326586	1			T21	351		T23	32		T24	28
all_pins[29]	transitions[0x0=>0x1]	794156	1			T21	220		T23	15		T24	18
all_pins[29]	transitions[0x1=>0x0]	793409	1			T21	172		T23	17		T24	29
all_pins[30]	values[0x0]	2176633	1			T20	1		T21	549		T22	1
all_pins[30]	values[0x1]	1324754	1			T21	286		T23	35		T24	32
all_pins[30]	transitions[0x0=>0x1]	791494	1			T21	151		T23	18		T24	22
all_pins[30]	transitions[0x1=>0x0]	793326	1			T21	216		T23	15		T24	18
all_pins[31]	values[0x0]	2174813	1			T20	1		T21	440		T22	1
all_pins[31]	values[0x1]	1326574	1			T21	395		T23	41		T24	27
all_pins[31]	transitions[0x0=>0x1]	793909	1			T21	248		T23	20		T24	13
all_pins[31]	transitions[0x1=>0x0]	792089	1			T21	139		T23	14		T24	18