Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[1]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[2]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[3]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[4]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[5]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[6]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[7]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[8]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[9]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[10]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[11]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[12]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[13]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[14]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[15]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[16]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[17]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[18]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[19]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[20]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[21]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[22]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[23]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[24]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[25]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[26]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[27]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[28]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[29]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[30]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[31]	11841218	1			T20	1		T21	2000		T22	703

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223697133

1

T20

32

T21

31957

T22

17496

auto[1]

155221843

1

T21

32043

T22

5000

T23

662994

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306539223

1

T20

32

T21

64000

T22

16670

auto[1]

72379753

1

T22

5826

T1

13890

T2

14063

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

284892407

1

T20

32

T21

64000

T22

11229

auto[1]

94026569

1

T22

11267

T1

16591

T2

15806

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4430840	1			T20	1		T21	1025		T22	187
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3341657	1			T21	975		T22	15		T23	20722
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1136173	1			T22	114		T1	223		T2	289
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1427458	1			T22	220		T1	11		T2	14
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	379774	1			T22	40		T1	257		T2	191
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1125316	1			T22	127		T1	230		T2	180
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4423783	1			T20	1		T21	1015		T22	214
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3339376	1			T21	985		T22	20		T23	20731
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1139723	1			T22	85		T1	248		T2	192
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1424313	1			T22	262		T1	13		T2	13
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	380174	1			T22	33		T1	228		T2	241
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1133849	1			T22	89		T1	315		T2	148
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4417814	1			T20	1		T21	989		T22	256
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3343987	1			T21	1011		T22	35		T23	19914
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1142976	1			T22	104		T1	283		T2	242
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1426506	1			T22	187		T1	9		T2	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	380085	1			T22	34		T1	243		T2	220
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1129850	1			T22	87		T1	189		T2	121
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4419358	1			T20	1		T21	1008		T22	212
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3344866	1			T21	992		T22	30		T23	21178
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1134515	1			T22	49		T1	228		T2	141
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1434098	1			T22	264		T1	15		T2	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	377124	1			T22	39		T1	325		T2	382
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1131257	1			T22	109		T1	220		T2	244
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4412857	1			T20	1		T21	969		T22	261
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3353799	1			T21	1031		T22	41		T23	20160
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1141870	1			T22	131		T1	229		T2	251
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1424333	1			T22	144		T1	12		T2	9
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	380121	1			T22	33		T1	248		T2	242
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1128238	1			T22	93		T1	212		T2	245
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4424937	1			T20	1		T21	986		T22	251
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3343084	1			T21	1014		T22	44		T23	19509
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1136034	1			T22	125		T1	253		T2	216
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1427777	1			T22	194		T1	14		T2	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	382440	1			T22	29		T1	269		T2	293
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1126946	1			T22	60		T1	172		T2	160
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4425352	1			T20	1		T21	998		T22	262
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3337832	1			T21	1002		T22	29		T23	21077
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1137888	1			T22	62		T1	148		T2	218
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1430999	1			T22	239		T1	28		T2	10
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	379539	1			T22	19		T1	351		T2	246
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1129608	1			T22	92		T1	218		T2	277
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4423474	1			T20	1		T21	1011		T22	226
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3344764	1			T21	989		T22	32		T23	19655
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1141823	1			T22	102		T1	238		T2	229
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1426736	1			T22	241		T1	8		T2	13
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	378574	1			T22	29		T1	255		T2	222
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1125847	1			T22	73		T1	205		T2	279
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4427598	1			T20	1		T21	1005		T22	248
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3335206	1			T21	995		T22	26		T23	20836
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1136893	1			T22	88		T1	183		T2	223
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1430885	1			T22	224		T1	17		T2	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	380621	1			T22	30		T1	325		T2	267
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1130015	1			T22	87		T1	250		T2	183
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4423496	1			T20	1		T21	1043		T22	191
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3337977	1			T21	957		T22	37		T23	20076
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1133932	1			T22	90		T1	145		T2	172
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1433475	1			T22	255		T1	10		T2	7
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	384590	1			T22	32		T1	306		T2	323
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1127748	1			T22	98		T1	166		T2	251
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4420886	1			T20	1		T21	1004		T22	272
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3341212	1			T21	996		T22	28		T23	20633
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1137338	1			T22	57		T1	216		T2	221
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1428455	1			T22	175		T1	16		T2	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	380631	1			T22	30		T1	433		T2	279
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1132696	1			T22	141		T1	145		T2	244
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4434020	1			T20	1		T21	993		T22	200
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3337815	1			T21	1007		T22	20		T23	20721
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1138892	1			T22	70		T1	137		T2	227
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1425816	1			T22	282		T1	18		T2	9
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	376834	1			T22	35		T1	332		T2	260
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1127841	1			T22	96		T1	237		T2	242
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4416388	1			T20	1		T21	988		T22	206
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3350154	1			T21	1012		T22	24		T23	20064
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1137044	1			T22	94		T1	217		T2	238
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1429497	1			T22	258		T1	20		T2	7
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	378889	1			T22	28		T1	226		T2	187
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1129246	1			T22	93		T1	287		T2	246
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4409835	1			T20	1		T21	1004		T22	190
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3346961	1			T21	996		T22	27		T23	20650
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1136665	1			T22	113		T1	186		T2	215
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1434615	1			T22	203		T1	21		T2	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	381401	1			T22	40		T1	330		T2	295
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1131741	1			T22	130		T1	178		T2	246
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4421900	1			T20	1		T21	1019		T22	232
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3343682	1			T21	981		T22	50		T23	21994
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1135094	1			T22	94		T1	174		T2	221
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1432625	1			T22	215		T1	3		T2	11
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	382212	1			T22	29		T1	355		T2	321
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1125705	1			T22	83		T1	229		T2	187
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4409339	1			T20	1		T21	1020		T22	177
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3353747	1			T21	980		T22	19		T23	20422
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1135135	1			T22	75		T1	206		T2	278
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1434956	1			T22	308		T1	9		T2	11
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	380532	1			T22	34		T1	223		T2	264
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1127509	1			T22	90		T1	297		T2	224
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4418862	1			T20	1		T21	976		T22	187
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3351198	1			T21	1024		T22	43		T23	20005
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1130333	1			T22	64		T1	266		T2	198
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1434358	1			T22	276		T1	14		T2	5
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	381925	1			T22	27		T1	334		T2	261
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1124542	1			T22	106		T1	147		T2	185
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4429694	1			T20	1		T21	994		T22	261
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3346028	1			T21	1006		T22	48		T23	20490
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1132487	1			T22	98		T1	318		T2	127
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1428714	1			T22	166		T1	12		T2	13
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	381479	1			T22	25		T1	205		T2	315
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1122816	1			T22	105		T1	211		T2	219
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4431230	1			T20	1		T21	957		T22	246
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3335445	1			T21	1043		T22	36		T23	18798
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1135414	1			T22	92		T1	249		T2	231
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1429641	1			T22	226		T1	12		T2	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	381939	1			T22	36		T1	270		T2	275
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1127549	1			T22	67		T1	251		T2	243
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4420235	1			T20	1		T21	969		T22	242
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3346350	1			T21	1031		T22	39		T23	21395
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1134926	1			T22	65		T1	224		T2	192
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1433832	1			T22	242		T1	19		T2	19
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	382613	1			T22	18		T1	285		T2	302
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1123262	1			T22	97		T1	157		T2	166
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4416729	1			T20	1		T21	1006		T22	278
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3352577	1			T21	994		T22	46		T23	19904
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1135981	1			T22	133		T1	190		T2	244
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1432260	1			T22	155		T1	12		T2	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	381724	1			T22	24		T1	383		T2	241
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1121947	1			T22	67		T1	168		T2	203
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4428268	1			T20	1		T21	982		T22	217
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3340207	1			T21	1018		T22	32		T23	21568
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1137079	1			T22	106		T1	253		T2	252
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1432874	1			T22	219		T1	8		T2	4
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	379175	1			T22	31		T1	213		T2	233
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1123615	1			T22	98		T1	224		T2	231
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4428132	1			T20	1		T21	1010		T22	236
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3339100	1			T21	990		T22	44		T23	22939
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1135621	1			T22	105		T1	171		T2	195
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1433593	1			T22	188		T1	9		T2	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	381797	1			T22	30		T1	297		T2	325
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1122975	1			T22	100		T1	260		T2	230
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4427875	1			T20	1		T21	980		T22	237
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3339742	1			T21	1020		T22	45		T23	21371
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1137685	1			T22	73		T1	159		T2	187
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1431917	1			T22	241		T1	12		T2	3
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	381103	1			T22	26		T1	370		T2	304
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1122896	1			T22	81		T1	197		T2	220
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4423387	1			T20	1		T21	998		T22	206
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3345972	1			T21	1002		T22	32		T23	22161
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1131487	1			T22	111		T1	242		T2	204
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1436636	1			T22	239		T1	6		T2	8
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	381822	1			T22	41		T1	289		T2	266
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1121914	1			T22	74		T1	264		T2	236
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4432850	1			T20	1		T21	1021		T22	208
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3342677	1			T21	979		T22	32		T23	20231
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1135484	1			T22	106		T1	234		T2	251
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1427279	1			T22	259		T1	16		T2	5
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	378093	1			T22	32		T1	212		T2	228
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1124835	1			T22	66		T1	219		T2	236
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4422440	1			T20	1		T21	970		T22	239
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3346971	1			T21	1030		T22	23		T23	18946
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1136025	1			T22	87		T1	271		T2	243
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1429541	1			T22	237		T1	13		T2	11
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	381422	1			T22	27		T1	212		T2	227
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1124819	1			T22	90		T1	239		T2	275
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4435350	1			T20	1		T21	993		T22	216
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3336190	1			T21	1007		T22	31		T23	21909
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1129682	1			T22	81		T1	165		T2	217
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1437407	1			T22	247		T1	10		T2	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	381709	1			T22	35		T1	294		T2	300
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1120880	1			T22	93		T1	228		T2	223
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4433500	1			T20	1		T21	982		T22	255
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3336542	1			T21	1018		T22	35		T23	22364
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1128707	1			T22	81		T1	177		T2	216
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1433003	1			T22	229		T1	10		T2	7
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	381915	1			T22	31		T1	277		T2	266
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1127551	1			T22	72		T1	215		T2	178
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4424441	1			T20	1		T21	1019		T22	233
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3347167	1			T21	981		T22	27		T23	20335
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1133891	1			T22	57		T1	195		T2	273
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1436574	1			T22	274		T1	12		T2	4
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	380826	1			T22	37		T1	344		T2	209
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1118319	1			T22	75		T1	214		T2	254
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4419264	1			T20	1		T21	1017		T22	238
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3347245	1			T21	983		T22	25		T23	20257
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1133466	1			T22	88		T1	206		T2	200
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1434293	1			T22	220		T1	8		T2	11
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	382763	1			T22	26		T1	282		T2	287
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1124187	1			T22	106		T1	226		T2	213
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4420480	1			T20	1		T21	1006		T22	213
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3346963	1			T21	994		T22	34		T23	21979
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1131037	1			T22	83		T1	256		T2	240
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1436753	1			T22	227		T1	14		T2	3
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	383051	1			T22	48		T1	207		T2	228
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1122934	1			T22	98		T1	230		T2	231

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal