Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[1]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[2]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[3]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[4]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[5]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[6]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[7]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[8]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[9]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[10]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[11]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[12]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[13]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[14]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[15]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[16]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[17]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[18]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[19]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[20]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[21]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[22]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[23]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[24]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[25]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[26]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[27]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[28]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[29]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[30]	11841218	1			T20	1		T21	2000		T22	703
bins_for_gpio_bits[31]	11841218	1			T20	1		T21	2000		T22	703

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223697133

1

T20

32

T21

31957

T22

17496

auto[1]

155221843

1

T21

32043

T22

5000

T23

662994

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

223688276

1

T20

32

T21

31957

T22

17496

auto[1]

155230700

1

T21

32043

T22

5000

T23

662994

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6793292	1			T20	1		T21	1025		T22	497
bins_for_gpio_bits[0]	auto[0]	auto[1]	200910	1			T22	24		T1	35		T2	40
bins_for_gpio_bits[0]	auto[1]	auto[0]	201179	1			T22	24		T1	34		T2	40
bins_for_gpio_bits[0]	auto[1]	auto[1]	4645837	1			T21	975		T22	158		T23	20722
bins_for_gpio_bits[1]	auto[0]	auto[0]	6785840	1			T20	1		T21	1015		T22	546
bins_for_gpio_bits[1]	auto[0]	auto[1]	201660	1			T22	15		T1	38		T2	27
bins_for_gpio_bits[1]	auto[1]	auto[0]	201979	1			T22	15		T1	38		T2	27
bins_for_gpio_bits[1]	auto[1]	auto[1]	4651739	1			T21	985		T22	127		T23	20731
bins_for_gpio_bits[2]	auto[0]	auto[0]	6785770	1			T20	1		T21	989		T22	531
bins_for_gpio_bits[2]	auto[0]	auto[1]	201254	1			T22	16		T1	38		T2	31
bins_for_gpio_bits[2]	auto[1]	auto[0]	201526	1			T22	16		T1	38		T2	31
bins_for_gpio_bits[2]	auto[1]	auto[1]	4652668	1			T21	1011		T22	140		T23	19914
bins_for_gpio_bits[3]	auto[0]	auto[0]	6785915	1			T20	1		T21	1008		T22	506
bins_for_gpio_bits[3]	auto[0]	auto[1]	201755	1			T22	19		T1	35		T2	26
bins_for_gpio_bits[3]	auto[1]	auto[0]	202056	1			T22	19		T1	35		T2	26
bins_for_gpio_bits[3]	auto[1]	auto[1]	4651492	1			T21	992		T22	159		T23	21178
bins_for_gpio_bits[4]	auto[0]	auto[0]	6777401	1			T20	1		T21	969		T22	521
bins_for_gpio_bits[4]	auto[0]	auto[1]	201338	1			T22	15		T1	32		T2	33
bins_for_gpio_bits[4]	auto[1]	auto[0]	201659	1			T22	15		T1	32		T2	33
bins_for_gpio_bits[4]	auto[1]	auto[1]	4660820	1			T21	1031		T22	152		T23	20160
bins_for_gpio_bits[5]	auto[0]	auto[0]	6787431	1			T20	1		T21	986		T22	559
bins_for_gpio_bits[5]	auto[0]	auto[1]	201025	1			T22	11		T1	34		T2	27
bins_for_gpio_bits[5]	auto[1]	auto[0]	201317	1			T22	11		T1	34		T2	27
bins_for_gpio_bits[5]	auto[1]	auto[1]	4651445	1			T21	1014		T22	122		T23	19509
bins_for_gpio_bits[6]	auto[0]	auto[0]	6792549	1			T20	1		T21	998		T22	545
bins_for_gpio_bits[6]	auto[0]	auto[1]	201400	1			T22	18		T1	26		T2	32
bins_for_gpio_bits[6]	auto[1]	auto[0]	201690	1			T22	18		T1	25		T2	32
bins_for_gpio_bits[6]	auto[1]	auto[1]	4645579	1			T21	1002		T22	122		T23	21077
bins_for_gpio_bits[7]	auto[0]	auto[0]	6790486	1			T20	1		T21	1011		T22	560
bins_for_gpio_bits[7]	auto[0]	auto[1]	201244	1			T22	9		T1	36		T2	33
bins_for_gpio_bits[7]	auto[1]	auto[0]	201547	1			T22	9		T1	35		T2	33
bins_for_gpio_bits[7]	auto[1]	auto[1]	4647941	1			T21	989		T22	125		T23	19655
bins_for_gpio_bits[8]	auto[0]	auto[0]	6793898	1			T20	1		T21	1005		T22	549
bins_for_gpio_bits[8]	auto[0]	auto[1]	201220	1			T22	11		T1	29		T2	33
bins_for_gpio_bits[8]	auto[1]	auto[0]	201478	1			T22	11		T1	29		T2	33
bins_for_gpio_bits[8]	auto[1]	auto[1]	4644622	1			T21	995		T22	132		T23	20836
bins_for_gpio_bits[9]	auto[0]	auto[0]	6789463	1			T20	1		T21	1043		T22	517
bins_for_gpio_bits[9]	auto[0]	auto[1]	201184	1			T22	19		T1	29		T2	26
bins_for_gpio_bits[9]	auto[1]	auto[0]	201440	1			T22	19		T1	28		T2	26
bins_for_gpio_bits[9]	auto[1]	auto[1]	4649131	1			T21	957		T22	148		T23	20076
bins_for_gpio_bits[10]	auto[0]	auto[0]	6784774	1			T20	1		T21	1004		T22	489
bins_for_gpio_bits[10]	auto[0]	auto[1]	201645	1			T22	15		T1	25		T2	35
bins_for_gpio_bits[10]	auto[1]	auto[0]	201905	1			T22	15		T1	24		T2	35
bins_for_gpio_bits[10]	auto[1]	auto[1]	4652894	1			T21	996		T22	184		T23	20633
bins_for_gpio_bits[11]	auto[0]	auto[0]	6797769	1			T20	1		T21	993		T22	534
bins_for_gpio_bits[11]	auto[0]	auto[1]	200689	1			T22	18		T1	23		T2	31
bins_for_gpio_bits[11]	auto[1]	auto[0]	200959	1			T22	18		T1	23		T2	31
bins_for_gpio_bits[11]	auto[1]	auto[1]	4641801	1			T21	1007		T22	133		T23	20721
bins_for_gpio_bits[12]	auto[0]	auto[0]	6781393	1			T20	1		T21	988		T22	546
bins_for_gpio_bits[12]	auto[0]	auto[1]	201239	1			T22	12		T1	39		T2	37
bins_for_gpio_bits[12]	auto[1]	auto[0]	201536	1			T22	12		T1	38		T2	37
bins_for_gpio_bits[12]	auto[1]	auto[1]	4657050	1			T21	1012		T22	133		T23	20064
bins_for_gpio_bits[13]	auto[0]	auto[0]	6778674	1			T20	1		T21	1004		T22	487
bins_for_gpio_bits[13]	auto[0]	auto[1]	202163	1			T22	19		T1	30		T2	38
bins_for_gpio_bits[13]	auto[1]	auto[0]	202441	1			T22	19		T1	29		T2	38
bins_for_gpio_bits[13]	auto[1]	auto[1]	4657940	1			T21	996		T22	178		T23	20650
bins_for_gpio_bits[14]	auto[0]	auto[0]	6787523	1			T20	1		T21	1019		T22	525
bins_for_gpio_bits[14]	auto[0]	auto[1]	201834	1			T22	16		T1	28		T2	29
bins_for_gpio_bits[14]	auto[1]	auto[0]	202096	1			T22	16		T1	28		T2	29
bins_for_gpio_bits[14]	auto[1]	auto[1]	4649765	1			T21	981		T22	146		T23	21994
bins_for_gpio_bits[15]	auto[0]	auto[0]	6778183	1			T20	1		T21	1020		T22	543
bins_for_gpio_bits[15]	auto[0]	auto[1]	200981	1			T22	17		T1	33		T2	37
bins_for_gpio_bits[15]	auto[1]	auto[0]	201247	1			T22	17		T1	33		T2	37
bins_for_gpio_bits[15]	auto[1]	auto[1]	4660807	1			T21	980		T22	126		T23	20422
bins_for_gpio_bits[16]	auto[0]	auto[0]	6781881	1			T20	1		T21	976		T22	510
bins_for_gpio_bits[16]	auto[0]	auto[1]	201425	1			T22	17		T1	26		T2	28
bins_for_gpio_bits[16]	auto[1]	auto[0]	201672	1			T22	17		T1	25		T2	28
bins_for_gpio_bits[16]	auto[1]	auto[1]	4656240	1			T21	1024		T22	159		T23	20005
bins_for_gpio_bits[17]	auto[0]	auto[0]	6789583	1			T20	1		T21	994		T22	508
bins_for_gpio_bits[17]	auto[0]	auto[1]	201063	1			T22	17		T1	34		T2	25
bins_for_gpio_bits[17]	auto[1]	auto[0]	201312	1			T22	17		T1	34		T2	25
bins_for_gpio_bits[17]	auto[1]	auto[1]	4649260	1			T21	1006		T22	161		T23	20490
bins_for_gpio_bits[18]	auto[0]	auto[0]	6794054	1			T20	1		T21	957		T22	552
bins_for_gpio_bits[18]	auto[0]	auto[1]	201957	1			T22	12		T1	40		T2	34
bins_for_gpio_bits[18]	auto[1]	auto[0]	202231	1			T22	12		T1	40		T2	34
bins_for_gpio_bits[18]	auto[1]	auto[1]	4642976	1			T21	1043		T22	127		T23	18798
bins_for_gpio_bits[19]	auto[0]	auto[0]	6787204	1			T20	1		T21	969		T22	536
bins_for_gpio_bits[19]	auto[0]	auto[1]	201484	1			T22	13		T1	27		T2	24
bins_for_gpio_bits[19]	auto[1]	auto[0]	201789	1			T22	13		T1	27		T2	24
bins_for_gpio_bits[19]	auto[1]	auto[1]	4650741	1			T21	1031		T22	141		T23	21395
bins_for_gpio_bits[20]	auto[0]	auto[0]	6783352	1			T20	1		T21	1006		T22	553
bins_for_gpio_bits[20]	auto[0]	auto[1]	201355	1			T22	13		T1	31		T2	37
bins_for_gpio_bits[20]	auto[1]	auto[0]	201618	1			T22	13		T1	31		T2	37
bins_for_gpio_bits[20]	auto[1]	auto[1]	4654893	1			T21	994		T22	124		T23	19904
bins_for_gpio_bits[21]	auto[0]	auto[0]	6796156	1			T20	1		T21	982		T22	525
bins_for_gpio_bits[21]	auto[0]	auto[1]	201786	1			T22	17		T1	37		T2	30
bins_for_gpio_bits[21]	auto[1]	auto[0]	202065	1			T22	17		T1	36		T2	30
bins_for_gpio_bits[21]	auto[1]	auto[1]	4641211	1			T21	1018		T22	144		T23	21568
bins_for_gpio_bits[22]	auto[0]	auto[0]	6795227	1			T20	1		T21	1010		T22	512
bins_for_gpio_bits[22]	auto[0]	auto[1]	201848	1			T22	17		T1	30		T2	31
bins_for_gpio_bits[22]	auto[1]	auto[0]	202119	1			T22	17		T1	30		T2	31
bins_for_gpio_bits[22]	auto[1]	auto[1]	4642024	1			T21	990		T22	157		T23	22939
bins_for_gpio_bits[23]	auto[0]	auto[0]	6795669	1			T20	1		T21	980		T22	534
bins_for_gpio_bits[23]	auto[0]	auto[1]	201537	1			T22	17		T1	21		T2	28
bins_for_gpio_bits[23]	auto[1]	auto[0]	201808	1			T22	17		T1	20		T2	28
bins_for_gpio_bits[23]	auto[1]	auto[1]	4642204	1			T21	1020		T22	135		T23	21371
bins_for_gpio_bits[24]	auto[0]	auto[0]	6789837	1			T20	1		T21	998		T22	540
bins_for_gpio_bits[24]	auto[0]	auto[1]	201403	1			T22	16		T1	35		T2	31
bins_for_gpio_bits[24]	auto[1]	auto[0]	201673	1			T22	16		T1	35		T2	31
bins_for_gpio_bits[24]	auto[1]	auto[1]	4648305	1			T21	1002		T22	131		T23	22161
bins_for_gpio_bits[25]	auto[0]	auto[0]	6793772	1			T20	1		T21	1021		T22	557
bins_for_gpio_bits[25]	auto[0]	auto[1]	201591	1			T22	16		T1	32		T2	30
bins_for_gpio_bits[25]	auto[1]	auto[0]	201841	1			T22	16		T1	32		T2	30
bins_for_gpio_bits[25]	auto[1]	auto[1]	4644014	1			T21	979		T22	114		T23	20231
bins_for_gpio_bits[26]	auto[0]	auto[0]	6786251	1			T20	1		T21	970		T22	549
bins_for_gpio_bits[26]	auto[0]	auto[1]	201451	1			T22	14		T1	35		T2	28
bins_for_gpio_bits[26]	auto[1]	auto[0]	201755	1			T22	14		T1	35		T2	28
bins_for_gpio_bits[26]	auto[1]	auto[1]	4651761	1			T21	1030		T22	126		T23	18946
bins_for_gpio_bits[27]	auto[0]	auto[0]	6801416	1			T20	1		T21	993		T22	529
bins_for_gpio_bits[27]	auto[0]	auto[1]	200749	1			T22	15		T1	33		T2	26
bins_for_gpio_bits[27]	auto[1]	auto[0]	201023	1			T22	15		T1	32		T2	26
bins_for_gpio_bits[27]	auto[1]	auto[1]	4638030	1			T21	1007		T22	144		T23	21909
bins_for_gpio_bits[28]	auto[0]	auto[0]	6793937	1			T20	1		T21	982		T22	552
bins_for_gpio_bits[28]	auto[0]	auto[1]	201008	1			T22	13		T1	30		T2	25
bins_for_gpio_bits[28]	auto[1]	auto[0]	201273	1			T22	13		T1	30		T2	25
bins_for_gpio_bits[28]	auto[1]	auto[1]	4645000	1			T21	1018		T22	125		T23	22364
bins_for_gpio_bits[29]	auto[0]	auto[0]	6793486	1			T20	1		T21	1019		T22	552
bins_for_gpio_bits[29]	auto[0]	auto[1]	201162	1			T22	12		T1	22		T2	35
bins_for_gpio_bits[29]	auto[1]	auto[0]	201420	1			T22	12		T1	22		T2	35
bins_for_gpio_bits[29]	auto[1]	auto[1]	4645150	1			T21	981		T22	127		T23	20335
bins_for_gpio_bits[30]	auto[0]	auto[0]	6785346	1			T20	1		T21	1017		T22	531
bins_for_gpio_bits[30]	auto[0]	auto[1]	201376	1			T22	15		T1	30		T2	31
bins_for_gpio_bits[30]	auto[1]	auto[0]	201677	1			T22	15		T1	30		T2	31
bins_for_gpio_bits[30]	auto[1]	auto[1]	4652819	1			T21	983		T22	142		T23	20257
bins_for_gpio_bits[31]	auto[0]	auto[0]	6787111	1			T20	1		T21	1006		T22	506
bins_for_gpio_bits[31]	auto[0]	auto[1]	200897	1			T22	17		T1	34		T2	36
bins_for_gpio_bits[31]	auto[1]	auto[0]	201159	1			T22	17		T1	34		T2	36
bins_for_gpio_bits[31]	auto[1]	auto[1]	4652051	1			T21	994		T22	163		T23	21979