Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096894 |
1 |
|
|
T20 |
1 |
|
T21 |
1491 |
|
T22 |
365 |
| auto[1] |
4933448 |
1 |
|
|
T21 |
1096 |
|
T24 |
117 |
|
T25 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11393309 |
1 |
|
|
T20 |
1 |
|
T21 |
2364 |
|
T22 |
365 |
| auto[1] |
637033 |
1 |
|
|
T21 |
223 |
|
T24 |
4 |
|
T25 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7059059 |
1 |
|
|
T20 |
1 |
|
T21 |
1434 |
|
T22 |
365 |
| auto[1] |
4971283 |
1 |
|
|
T21 |
1153 |
|
T24 |
62 |
|
T25 |
53 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2165978 |
1 |
|
|
T21 |
517 |
|
T24 |
17 |
|
T25 |
19 |
| auto[1] |
auto[0] |
auto[1] |
316735 |
1 |
|
|
T21 |
126 |
|
T24 |
1 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2168272 |
1 |
|
|
T21 |
413 |
|
T24 |
41 |
|
T25 |
29 |
| auto[1] |
auto[1] |
auto[1] |
320298 |
1 |
|
|
T21 |
97 |
|
T24 |
3 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097842 |
1 |
|
|
T20 |
1 |
|
T21 |
1594 |
|
T22 |
365 |
| auto[1] |
4932500 |
1 |
|
|
T21 |
993 |
|
T24 |
49 |
|
T25 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11396843 |
1 |
|
|
T20 |
1 |
|
T21 |
2322 |
|
T22 |
365 |
| auto[1] |
633499 |
1 |
|
|
T21 |
265 |
|
T24 |
10 |
|
T25 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097705 |
1 |
|
|
T20 |
1 |
|
T21 |
1240 |
|
T22 |
365 |
| auto[1] |
4932637 |
1 |
|
|
T21 |
1347 |
|
T24 |
105 |
|
T25 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2153990 |
1 |
|
|
T21 |
723 |
|
T24 |
60 |
|
T25 |
15 |
| auto[1] |
auto[0] |
auto[1] |
316722 |
1 |
|
|
T21 |
178 |
|
T24 |
7 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2145148 |
1 |
|
|
T21 |
359 |
|
T24 |
35 |
|
T25 |
32 |
| auto[1] |
auto[1] |
auto[1] |
316777 |
1 |
|
|
T21 |
87 |
|
T24 |
3 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7105328 |
1 |
|
|
T20 |
1 |
|
T21 |
1524 |
|
T22 |
365 |
| auto[1] |
4925014 |
1 |
|
|
T21 |
1063 |
|
T24 |
74 |
|
T25 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11402255 |
1 |
|
|
T20 |
1 |
|
T21 |
2303 |
|
T22 |
365 |
| auto[1] |
628087 |
1 |
|
|
T21 |
284 |
|
T24 |
5 |
|
T25 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7127309 |
1 |
|
|
T20 |
1 |
|
T21 |
1132 |
|
T22 |
365 |
| auto[1] |
4903033 |
1 |
|
|
T21 |
1455 |
|
T24 |
72 |
|
T25 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2150600 |
1 |
|
|
T21 |
647 |
|
T24 |
42 |
|
T25 |
27 |
| auto[1] |
auto[0] |
auto[1] |
316638 |
1 |
|
|
T21 |
160 |
|
T24 |
3 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2124346 |
1 |
|
|
T21 |
524 |
|
T24 |
25 |
|
T25 |
23 |
| auto[1] |
auto[1] |
auto[1] |
311449 |
1 |
|
|
T21 |
124 |
|
T24 |
2 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7099259 |
1 |
|
|
T20 |
1 |
|
T21 |
1524 |
|
T22 |
365 |
| auto[1] |
4931083 |
1 |
|
|
T21 |
1063 |
|
T24 |
104 |
|
T25 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11399302 |
1 |
|
|
T20 |
1 |
|
T21 |
2354 |
|
T22 |
365 |
| auto[1] |
631040 |
1 |
|
|
T21 |
233 |
|
T24 |
10 |
|
T25 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7104283 |
1 |
|
|
T20 |
1 |
|
T21 |
1334 |
|
T22 |
365 |
| auto[1] |
4926059 |
1 |
|
|
T21 |
1253 |
|
T24 |
98 |
|
T25 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2155850 |
1 |
|
|
T21 |
597 |
|
T24 |
33 |
|
T25 |
35 |
| auto[1] |
auto[0] |
auto[1] |
317166 |
1 |
|
|
T21 |
141 |
|
T24 |
5 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2139169 |
1 |
|
|
T21 |
423 |
|
T24 |
55 |
|
T25 |
15 |
| auto[1] |
auto[1] |
auto[1] |
313874 |
1 |
|
|
T21 |
92 |
|
T24 |
5 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7121434 |
1 |
|
|
T20 |
1 |
|
T21 |
1278 |
|
T22 |
365 |
| auto[1] |
4908908 |
1 |
|
|
T21 |
1309 |
|
T24 |
53 |
|
T1 |
569 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11395494 |
1 |
|
|
T20 |
1 |
|
T21 |
2365 |
|
T22 |
365 |
| auto[1] |
634848 |
1 |
|
|
T21 |
222 |
|
T24 |
9 |
|
T25 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7086596 |
1 |
|
|
T20 |
1 |
|
T21 |
1436 |
|
T22 |
365 |
| auto[1] |
4943746 |
1 |
|
|
T21 |
1151 |
|
T24 |
96 |
|
T25 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2170414 |
1 |
|
|
T21 |
377 |
|
T24 |
70 |
|
T25 |
41 |
| auto[1] |
auto[0] |
auto[1] |
319909 |
1 |
|
|
T21 |
87 |
|
T24 |
8 |
|
T25 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2138484 |
1 |
|
|
T21 |
552 |
|
T24 |
17 |
|
T1 |
236 |
| auto[1] |
auto[1] |
auto[1] |
314939 |
1 |
|
|
T21 |
135 |
|
T24 |
1 |
|
T1 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7117473 |
1 |
|
|
T20 |
1 |
|
T21 |
1171 |
|
T22 |
365 |
| auto[1] |
4912869 |
1 |
|
|
T21 |
1416 |
|
T24 |
59 |
|
T25 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11396127 |
1 |
|
|
T20 |
1 |
|
T21 |
2362 |
|
T22 |
365 |
| auto[1] |
634215 |
1 |
|
|
T21 |
225 |
|
T24 |
5 |
|
T1 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7094436 |
1 |
|
|
T20 |
1 |
|
T21 |
1402 |
|
T22 |
365 |
| auto[1] |
4935906 |
1 |
|
|
T21 |
1185 |
|
T24 |
92 |
|
T25 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2153554 |
1 |
|
|
T21 |
379 |
|
T24 |
50 |
|
T25 |
26 |
| auto[1] |
auto[0] |
auto[1] |
317709 |
1 |
|
|
T21 |
86 |
|
T24 |
2 |
|
T1 |
14 |
| auto[1] |
auto[1] |
auto[0] |
2148137 |
1 |
|
|
T21 |
581 |
|
T24 |
37 |
|
T25 |
23 |
| auto[1] |
auto[1] |
auto[1] |
316506 |
1 |
|
|
T21 |
139 |
|
T24 |
3 |
|
T1 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7101140 |
1 |
|
|
T20 |
1 |
|
T21 |
1551 |
|
T22 |
365 |
| auto[1] |
4929202 |
1 |
|
|
T21 |
1036 |
|
T24 |
36 |
|
T25 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11404306 |
1 |
|
|
T20 |
1 |
|
T21 |
2350 |
|
T22 |
365 |
| auto[1] |
626036 |
1 |
|
|
T21 |
237 |
|
T24 |
5 |
|
T25 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7138971 |
1 |
|
|
T20 |
1 |
|
T21 |
1321 |
|
T22 |
365 |
| auto[1] |
4891371 |
1 |
|
|
T21 |
1266 |
|
T24 |
80 |
|
T25 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2141214 |
1 |
|
|
T21 |
592 |
|
T24 |
67 |
|
T25 |
39 |
| auto[1] |
auto[0] |
auto[1] |
314194 |
1 |
|
|
T21 |
129 |
|
T24 |
5 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2124121 |
1 |
|
|
T21 |
437 |
|
T24 |
8 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[1] |
311842 |
1 |
|
|
T21 |
108 |
|
T25 |
1 |
|
T1 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7103499 |
1 |
|
|
T20 |
1 |
|
T21 |
1383 |
|
T22 |
365 |
| auto[1] |
4926843 |
1 |
|
|
T21 |
1204 |
|
T24 |
21 |
|
T25 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11397978 |
1 |
|
|
T20 |
1 |
|
T21 |
2366 |
|
T22 |
365 |
| auto[1] |
632364 |
1 |
|
|
T21 |
221 |
|
T24 |
5 |
|
T25 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7098457 |
1 |
|
|
T20 |
1 |
|
T21 |
1461 |
|
T22 |
365 |
| auto[1] |
4931885 |
1 |
|
|
T21 |
1126 |
|
T24 |
85 |
|
T25 |
37 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2140406 |
1 |
|
|
T21 |
422 |
|
T24 |
70 |
|
T25 |
26 |
| auto[1] |
auto[0] |
auto[1] |
314691 |
1 |
|
|
T21 |
88 |
|
T24 |
5 |
|
T1 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2159115 |
1 |
|
|
T21 |
483 |
|
T24 |
10 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[1] |
317673 |
1 |
|
|
T21 |
133 |
|
T25 |
2 |
|
T1 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100600 |
1 |
|
|
T20 |
1 |
|
T21 |
1305 |
|
T22 |
365 |
| auto[1] |
4929742 |
1 |
|
|
T21 |
1282 |
|
T24 |
54 |
|
T25 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11399421 |
1 |
|
|
T20 |
1 |
|
T21 |
2371 |
|
T22 |
365 |
| auto[1] |
630921 |
1 |
|
|
T21 |
216 |
|
T24 |
11 |
|
T25 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7107487 |
1 |
|
|
T20 |
1 |
|
T21 |
1472 |
|
T22 |
365 |
| auto[1] |
4922855 |
1 |
|
|
T21 |
1115 |
|
T24 |
100 |
|
T25 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2140844 |
1 |
|
|
T21 |
401 |
|
T24 |
62 |
|
T25 |
52 |
| auto[1] |
auto[0] |
auto[1] |
315155 |
1 |
|
|
T21 |
87 |
|
T24 |
7 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2151090 |
1 |
|
|
T21 |
498 |
|
T24 |
27 |
|
T1 |
322 |
| auto[1] |
auto[1] |
auto[1] |
315766 |
1 |
|
|
T21 |
129 |
|
T24 |
4 |
|
T1 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7117835 |
1 |
|
|
T20 |
1 |
|
T21 |
1377 |
|
T22 |
365 |
| auto[1] |
4912507 |
1 |
|
|
T21 |
1210 |
|
T24 |
74 |
|
T25 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11392617 |
1 |
|
|
T20 |
1 |
|
T21 |
2349 |
|
T22 |
365 |
| auto[1] |
637725 |
1 |
|
|
T21 |
238 |
|
T24 |
6 |
|
T25 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7070367 |
1 |
|
|
T20 |
1 |
|
T21 |
1379 |
|
T22 |
365 |
| auto[1] |
4959975 |
1 |
|
|
T21 |
1208 |
|
T24 |
95 |
|
T25 |
54 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2171456 |
1 |
|
|
T21 |
426 |
|
T24 |
61 |
|
T25 |
26 |
| auto[1] |
auto[0] |
auto[1] |
320620 |
1 |
|
|
T21 |
102 |
|
T24 |
4 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2150794 |
1 |
|
|
T21 |
544 |
|
T24 |
28 |
|
T25 |
25 |
| auto[1] |
auto[1] |
auto[1] |
317105 |
1 |
|
|
T21 |
136 |
|
T24 |
2 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7099508 |
1 |
|
|
T20 |
1 |
|
T21 |
1057 |
|
T22 |
365 |
| auto[1] |
4930834 |
1 |
|
|
T21 |
1530 |
|
T24 |
42 |
|
T25 |
49 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11392940 |
1 |
|
|
T20 |
1 |
|
T21 |
2381 |
|
T22 |
365 |
| auto[1] |
637402 |
1 |
|
|
T21 |
206 |
|
T24 |
5 |
|
T25 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7064911 |
1 |
|
|
T20 |
1 |
|
T21 |
1511 |
|
T22 |
365 |
| auto[1] |
4965431 |
1 |
|
|
T21 |
1076 |
|
T24 |
74 |
|
T25 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2172915 |
1 |
|
|
T21 |
451 |
|
T24 |
51 |
|
T25 |
34 |
| auto[1] |
auto[0] |
auto[1] |
320104 |
1 |
|
|
T21 |
112 |
|
T24 |
3 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2155114 |
1 |
|
|
T21 |
419 |
|
T24 |
18 |
|
T25 |
12 |
| auto[1] |
auto[1] |
auto[1] |
317298 |
1 |
|
|
T21 |
94 |
|
T24 |
2 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096805 |
1 |
|
|
T20 |
1 |
|
T21 |
1271 |
|
T22 |
365 |
| auto[1] |
4933537 |
1 |
|
|
T21 |
1316 |
|
T24 |
67 |
|
T25 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11400781 |
1 |
|
|
T20 |
1 |
|
T21 |
2329 |
|
T22 |
365 |
| auto[1] |
629561 |
1 |
|
|
T21 |
258 |
|
T24 |
6 |
|
T25 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7114046 |
1 |
|
|
T20 |
1 |
|
T21 |
1229 |
|
T22 |
365 |
| auto[1] |
4916296 |
1 |
|
|
T21 |
1358 |
|
T24 |
66 |
|
T25 |
38 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2143048 |
1 |
|
|
T21 |
600 |
|
T24 |
29 |
|
T25 |
23 |
| auto[1] |
auto[0] |
auto[1] |
314948 |
1 |
|
|
T21 |
142 |
|
T24 |
3 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2143687 |
1 |
|
|
T21 |
500 |
|
T24 |
31 |
|
T25 |
13 |
| auto[1] |
auto[1] |
auto[1] |
314613 |
1 |
|
|
T21 |
116 |
|
T24 |
3 |
|
T1 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7104185 |
1 |
|
|
T20 |
1 |
|
T21 |
1539 |
|
T22 |
365 |
| auto[1] |
4926157 |
1 |
|
|
T21 |
1048 |
|
T24 |
46 |
|
T25 |
58 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11399630 |
1 |
|
|
T20 |
1 |
|
T21 |
2326 |
|
T22 |
365 |
| auto[1] |
630712 |
1 |
|
|
T21 |
261 |
|
T24 |
4 |
|
T25 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7110891 |
1 |
|
|
T20 |
1 |
|
T21 |
1277 |
|
T22 |
365 |
| auto[1] |
4919451 |
1 |
|
|
T21 |
1310 |
|
T24 |
73 |
|
T25 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2149799 |
1 |
|
|
T21 |
694 |
|
T24 |
49 |
|
T25 |
16 |
| auto[1] |
auto[0] |
auto[1] |
315960 |
1 |
|
|
T21 |
171 |
|
T24 |
4 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2138940 |
1 |
|
|
T21 |
355 |
|
T24 |
20 |
|
T25 |
27 |
| auto[1] |
auto[1] |
auto[1] |
314752 |
1 |
|
|
T21 |
90 |
|
T25 |
1 |
|
T1 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100003 |
1 |
|
|
T20 |
1 |
|
T21 |
1108 |
|
T22 |
365 |
| auto[1] |
4930339 |
1 |
|
|
T21 |
1479 |
|
T24 |
114 |
|
T25 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11396907 |
1 |
|
|
T20 |
1 |
|
T21 |
2336 |
|
T22 |
365 |
| auto[1] |
633435 |
1 |
|
|
T21 |
251 |
|
T24 |
5 |
|
T25 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7093730 |
1 |
|
|
T20 |
1 |
|
T21 |
1293 |
|
T22 |
365 |
| auto[1] |
4936612 |
1 |
|
|
T21 |
1294 |
|
T24 |
61 |
|
T25 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2161621 |
1 |
|
|
T21 |
473 |
|
T24 |
16 |
|
T25 |
4 |
| auto[1] |
auto[0] |
auto[1] |
318889 |
1 |
|
|
T21 |
113 |
|
T25 |
1 |
|
T1 |
10 |
| auto[1] |
auto[1] |
auto[0] |
2141556 |
1 |
|
|
T21 |
570 |
|
T24 |
40 |
|
T25 |
10 |
| auto[1] |
auto[1] |
auto[1] |
314546 |
1 |
|
|
T21 |
138 |
|
T24 |
5 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092952 |
1 |
|
|
T20 |
1 |
|
T21 |
1219 |
|
T22 |
365 |
| auto[1] |
4937390 |
1 |
|
|
T21 |
1368 |
|
T24 |
80 |
|
T25 |
60 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11396142 |
1 |
|
|
T20 |
1 |
|
T21 |
2409 |
|
T22 |
365 |
| auto[1] |
634200 |
1 |
|
|
T21 |
178 |
|
T24 |
4 |
|
T25 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7088192 |
1 |
|
|
T20 |
1 |
|
T21 |
1686 |
|
T22 |
365 |
| auto[1] |
4942150 |
1 |
|
|
T21 |
901 |
|
T24 |
51 |
|
T25 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2158761 |
1 |
|
|
T21 |
284 |
|
T24 |
22 |
|
T25 |
23 |
| auto[1] |
auto[0] |
auto[1] |
317507 |
1 |
|
|
T21 |
71 |
|
T24 |
2 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2149189 |
1 |
|
|
T21 |
439 |
|
T24 |
25 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[1] |
316693 |
1 |
|
|
T21 |
107 |
|
T24 |
2 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7135333 |
1 |
|
|
T20 |
1 |
|
T21 |
1481 |
|
T22 |
365 |
| auto[1] |
4895009 |
1 |
|
|
T21 |
1106 |
|
T24 |
93 |
|
T25 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11396401 |
1 |
|
|
T20 |
1 |
|
T21 |
2263 |
|
T22 |
365 |
| auto[1] |
633941 |
1 |
|
|
T21 |
324 |
|
T24 |
9 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7098361 |
1 |
|
|
T20 |
1 |
|
T21 |
938 |
|
T22 |
365 |
| auto[1] |
4931981 |
1 |
|
|
T21 |
1649 |
|
T24 |
110 |
|
T25 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2169300 |
1 |
|
|
T21 |
749 |
|
T24 |
35 |
|
T25 |
41 |
| auto[1] |
auto[0] |
auto[1] |
321042 |
1 |
|
|
T21 |
183 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2128740 |
1 |
|
|
T21 |
576 |
|
T24 |
66 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[1] |
312899 |
1 |
|
|
T21 |
141 |
|
T24 |
6 |
|
T1 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100141 |
1 |
|
|
T20 |
1 |
|
T21 |
1278 |
|
T22 |
365 |
| auto[1] |
4930201 |
1 |
|
|
T21 |
1309 |
|
T24 |
74 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11400891 |
1 |
|
|
T20 |
1 |
|
T21 |
2253 |
|
T22 |
365 |
| auto[1] |
629451 |
1 |
|
|
T21 |
334 |
|
T24 |
10 |
|
T25 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7109180 |
1 |
|
|
T20 |
1 |
|
T21 |
884 |
|
T22 |
365 |
| auto[1] |
4921162 |
1 |
|
|
T21 |
1703 |
|
T24 |
95 |
|
T25 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2152356 |
1 |
|
|
T21 |
608 |
|
T24 |
45 |
|
T25 |
23 |
| auto[1] |
auto[0] |
auto[1] |
315178 |
1 |
|
|
T21 |
151 |
|
T24 |
5 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2139355 |
1 |
|
|
T21 |
761 |
|
T24 |
40 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
314273 |
1 |
|
|
T21 |
183 |
|
T24 |
5 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7120510 |
1 |
|
|
T20 |
1 |
|
T21 |
1488 |
|
T22 |
365 |
| auto[1] |
4909832 |
1 |
|
|
T21 |
1099 |
|
T24 |
105 |
|
T25 |
62 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11398146 |
1 |
|
|
T20 |
1 |
|
T21 |
2308 |
|
T22 |
365 |
| auto[1] |
632196 |
1 |
|
|
T21 |
279 |
|
T24 |
5 |
|
T25 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7103805 |
1 |
|
|
T20 |
1 |
|
T21 |
1089 |
|
T22 |
365 |
| auto[1] |
4926537 |
1 |
|
|
T21 |
1498 |
|
T24 |
78 |
|
T25 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2166678 |
1 |
|
|
T21 |
807 |
|
T24 |
30 |
|
T25 |
23 |
| auto[1] |
auto[0] |
auto[1] |
319943 |
1 |
|
|
T21 |
182 |
|
T25 |
2 |
|
T1 |
13 |
| auto[1] |
auto[1] |
auto[0] |
2127663 |
1 |
|
|
T21 |
412 |
|
T24 |
43 |
|
T25 |
20 |
| auto[1] |
auto[1] |
auto[1] |
312253 |
1 |
|
|
T21 |
97 |
|
T24 |
5 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092892 |
1 |
|
|
T20 |
1 |
|
T21 |
1364 |
|
T22 |
365 |
| auto[1] |
4937450 |
1 |
|
|
T21 |
1223 |
|
T24 |
96 |
|
T25 |
67 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11396984 |
1 |
|
|
T20 |
1 |
|
T21 |
2350 |
|
T22 |
365 |
| auto[1] |
633358 |
1 |
|
|
T21 |
237 |
|
T24 |
5 |
|
T25 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092093 |
1 |
|
|
T20 |
1 |
|
T21 |
1370 |
|
T22 |
365 |
| auto[1] |
4938249 |
1 |
|
|
T21 |
1217 |
|
T24 |
54 |
|
T25 |
49 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2149956 |
1 |
|
|
T21 |
593 |
|
T24 |
17 |
|
T25 |
23 |
| auto[1] |
auto[0] |
auto[1] |
316463 |
1 |
|
|
T21 |
145 |
|
T24 |
1 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2154935 |
1 |
|
|
T21 |
387 |
|
T24 |
32 |
|
T25 |
21 |
| auto[1] |
auto[1] |
auto[1] |
316895 |
1 |
|
|
T21 |
92 |
|
T24 |
4 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7101695 |
1 |
|
|
T20 |
1 |
|
T21 |
1306 |
|
T22 |
365 |
| auto[1] |
4928647 |
1 |
|
|
T21 |
1281 |
|
T24 |
64 |
|
T25 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11398098 |
1 |
|
|
T20 |
1 |
|
T21 |
2352 |
|
T22 |
365 |
| auto[1] |
632244 |
1 |
|
|
T21 |
235 |
|
T24 |
5 |
|
T25 |
5 |