Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7107167 |
1 |
|
|
T20 |
1 |
|
T21 |
1441 |
|
T22 |
365 |
| auto[1] |
4923175 |
1 |
|
|
T21 |
1146 |
|
T24 |
76 |
|
T25 |
62 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11400677 |
1 |
|
|
T20 |
1 |
|
T21 |
2323 |
|
T22 |
365 |
| auto[1] |
629665 |
1 |
|
|
T21 |
264 |
|
T24 |
11 |
|
T25 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7112405 |
1 |
|
|
T20 |
1 |
|
T21 |
1191 |
|
T22 |
365 |
| auto[1] |
4917937 |
1 |
|
|
T21 |
1396 |
|
T24 |
94 |
|
T25 |
59 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2151218 |
1 |
|
|
T21 |
646 |
|
T24 |
47 |
|
T25 |
18 |
| auto[1] |
auto[0] |
auto[1] |
316093 |
1 |
|
|
T21 |
145 |
|
T24 |
6 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2137054 |
1 |
|
|
T21 |
486 |
|
T24 |
36 |
|
T25 |
38 |
| auto[1] |
auto[1] |
auto[1] |
313572 |
1 |
|
|
T21 |
119 |
|
T24 |
5 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |