Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096102 |
1 |
|
|
T20 |
1 |
|
T21 |
1260 |
|
T22 |
365 |
| auto[1] |
4934240 |
1 |
|
|
T21 |
1327 |
|
T24 |
105 |
|
T25 |
34 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11401174 |
1 |
|
|
T20 |
1 |
|
T21 |
2341 |
|
T22 |
365 |
| auto[1] |
629168 |
1 |
|
|
T21 |
246 |
|
T24 |
6 |
|
T25 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7120312 |
1 |
|
|
T20 |
1 |
|
T21 |
1314 |
|
T22 |
365 |
| auto[1] |
4910030 |
1 |
|
|
T21 |
1273 |
|
T24 |
94 |
|
T25 |
36 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2142500 |
1 |
|
|
T21 |
551 |
|
T24 |
40 |
|
T25 |
26 |
| auto[1] |
auto[0] |
auto[1] |
314817 |
1 |
|
|
T21 |
131 |
|
T24 |
2 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2138362 |
1 |
|
|
T21 |
476 |
|
T24 |
48 |
|
T25 |
6 |
| auto[1] |
auto[1] |
auto[1] |
314351 |
1 |
|
|
T21 |
115 |
|
T24 |
4 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |