Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7112188 |
1 |
|
|
T20 |
1 |
|
T21 |
1178 |
|
T22 |
365 |
| auto[1] |
4918154 |
1 |
|
|
T21 |
1409 |
|
T24 |
82 |
|
T25 |
89 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11398143 |
1 |
|
|
T20 |
1 |
|
T21 |
2367 |
|
T22 |
365 |
| auto[1] |
632199 |
1 |
|
|
T21 |
220 |
|
T24 |
3 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7098877 |
1 |
|
|
T20 |
1 |
|
T21 |
1485 |
|
T22 |
365 |
| auto[1] |
4931465 |
1 |
|
|
T21 |
1102 |
|
T24 |
54 |
|
T25 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2165089 |
1 |
|
|
T21 |
403 |
|
T24 |
31 |
|
T25 |
3 |
| auto[1] |
auto[0] |
auto[1] |
317907 |
1 |
|
|
T21 |
95 |
|
T24 |
3 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2134177 |
1 |
|
|
T21 |
479 |
|
T24 |
20 |
|
T25 |
16 |
| auto[1] |
auto[1] |
auto[1] |
314292 |
1 |
|
|
T21 |
125 |
|
T25 |
1 |
|
T1 |
19 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |