Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7123692 |
1 |
|
|
T20 |
1 |
|
T21 |
1285 |
|
T22 |
365 |
| auto[1] |
4906650 |
1 |
|
|
T21 |
1302 |
|
T24 |
114 |
|
T25 |
31 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11397812 |
1 |
|
|
T20 |
1 |
|
T21 |
2331 |
|
T22 |
365 |
| auto[1] |
632530 |
1 |
|
|
T21 |
256 |
|
T24 |
10 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096612 |
1 |
|
|
T20 |
1 |
|
T21 |
1272 |
|
T22 |
365 |
| auto[1] |
4933730 |
1 |
|
|
T21 |
1315 |
|
T24 |
128 |
|
T25 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2153776 |
1 |
|
|
T21 |
532 |
|
T24 |
43 |
|
T25 |
12 |
| auto[1] |
auto[0] |
auto[1] |
317480 |
1 |
|
|
T21 |
123 |
|
T24 |
2 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2147424 |
1 |
|
|
T21 |
527 |
|
T24 |
75 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[1] |
315050 |
1 |
|
|
T21 |
133 |
|
T24 |
8 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |