Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7114669 |
1 |
|
|
T20 |
1 |
|
T21 |
1601 |
|
T22 |
365 |
| auto[1] |
4915673 |
1 |
|
|
T21 |
986 |
|
T24 |
60 |
|
T25 |
92 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11404862 |
1 |
|
|
T20 |
1 |
|
T21 |
2352 |
|
T22 |
365 |
| auto[1] |
625480 |
1 |
|
|
T21 |
235 |
|
T24 |
5 |
|
T1 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7149436 |
1 |
|
|
T20 |
1 |
|
T21 |
1377 |
|
T22 |
365 |
| auto[1] |
4880906 |
1 |
|
|
T21 |
1210 |
|
T24 |
67 |
|
T25 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2136685 |
1 |
|
|
T21 |
575 |
|
T24 |
39 |
|
T25 |
1 |
| auto[1] |
auto[0] |
auto[1] |
314439 |
1 |
|
|
T21 |
136 |
|
T24 |
4 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
2118741 |
1 |
|
|
T21 |
400 |
|
T24 |
23 |
|
T25 |
44 |
| auto[1] |
auto[1] |
auto[1] |
311041 |
1 |
|
|
T21 |
99 |
|
T24 |
1 |
|
T1 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |