Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096894 |
1 |
|
|
T20 |
1 |
|
T21 |
1491 |
|
T22 |
365 |
| auto[1] |
4933448 |
1 |
|
|
T21 |
1096 |
|
T24 |
117 |
|
T25 |
55 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9981822 |
1 |
|
|
T20 |
1 |
|
T21 |
1924 |
|
T22 |
365 |
| auto[1] |
2048520 |
1 |
|
|
T21 |
663 |
|
T24 |
55 |
|
T25 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7118677 |
1 |
|
|
T20 |
1 |
|
T21 |
1211 |
|
T22 |
365 |
| auto[1] |
4911665 |
1 |
|
|
T21 |
1376 |
|
T24 |
95 |
|
T25 |
17 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1439915 |
1 |
|
|
T21 |
419 |
|
T24 |
13 |
|
T25 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1026952 |
1 |
|
|
T21 |
364 |
|
T24 |
14 |
|
T1 |
258 |
| auto[1] |
auto[1] |
auto[0] |
1423230 |
1 |
|
|
T21 |
294 |
|
T24 |
27 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1021568 |
1 |
|
|
T21 |
299 |
|
T24 |
41 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |