Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097842 |
1 |
|
|
T20 |
1 |
|
T21 |
1594 |
|
T22 |
365 |
| auto[1] |
4932500 |
1 |
|
|
T21 |
993 |
|
T24 |
49 |
|
T25 |
43 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9968811 |
1 |
|
|
T20 |
1 |
|
T21 |
2002 |
|
T22 |
365 |
| auto[1] |
2061531 |
1 |
|
|
T21 |
585 |
|
T24 |
39 |
|
T25 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7093127 |
1 |
|
|
T20 |
1 |
|
T21 |
1449 |
|
T22 |
365 |
| auto[1] |
4937215 |
1 |
|
|
T21 |
1138 |
|
T24 |
74 |
|
T25 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1440385 |
1 |
|
|
T21 |
375 |
|
T24 |
30 |
|
T25 |
4 |
| auto[1] |
auto[0] |
auto[1] |
1029152 |
1 |
|
|
T21 |
409 |
|
T24 |
25 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1435299 |
1 |
|
|
T21 |
178 |
|
T24 |
5 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1032379 |
1 |
|
|
T21 |
176 |
|
T24 |
14 |
|
T25 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |