Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7105328 |
1 |
|
|
T20 |
1 |
|
T21 |
1524 |
|
T22 |
365 |
| auto[1] |
4925014 |
1 |
|
|
T21 |
1063 |
|
T24 |
74 |
|
T25 |
40 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9971057 |
1 |
|
|
T20 |
1 |
|
T21 |
1983 |
|
T22 |
365 |
| auto[1] |
2059285 |
1 |
|
|
T21 |
604 |
|
T24 |
36 |
|
T25 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7110494 |
1 |
|
|
T20 |
1 |
|
T21 |
1350 |
|
T22 |
365 |
| auto[1] |
4919848 |
1 |
|
|
T21 |
1237 |
|
T24 |
65 |
|
T25 |
60 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1432145 |
1 |
|
|
T21 |
359 |
|
T24 |
15 |
|
T25 |
25 |
| auto[1] |
auto[0] |
auto[1] |
1033118 |
1 |
|
|
T21 |
343 |
|
T24 |
26 |
|
T25 |
20 |
| auto[1] |
auto[1] |
auto[0] |
1428418 |
1 |
|
|
T21 |
274 |
|
T24 |
14 |
|
T25 |
13 |
| auto[1] |
auto[1] |
auto[1] |
1026167 |
1 |
|
|
T21 |
261 |
|
T24 |
10 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |