Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7099259 |
1 |
|
|
T20 |
1 |
|
T21 |
1524 |
|
T22 |
365 |
| auto[1] |
4931083 |
1 |
|
|
T21 |
1063 |
|
T24 |
104 |
|
T25 |
27 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9981635 |
1 |
|
|
T20 |
1 |
|
T21 |
1830 |
|
T22 |
365 |
| auto[1] |
2048707 |
1 |
|
|
T21 |
757 |
|
T24 |
22 |
|
T25 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7121182 |
1 |
|
|
T20 |
1 |
|
T21 |
1103 |
|
T22 |
365 |
| auto[1] |
4909160 |
1 |
|
|
T21 |
1484 |
|
T24 |
77 |
|
T25 |
78 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1424976 |
1 |
|
|
T21 |
384 |
|
T24 |
26 |
|
T25 |
38 |
| auto[1] |
auto[0] |
auto[1] |
1023954 |
1 |
|
|
T21 |
444 |
|
T24 |
16 |
|
T25 |
22 |
| auto[1] |
auto[1] |
auto[0] |
1435477 |
1 |
|
|
T21 |
343 |
|
T24 |
29 |
|
T25 |
15 |
| auto[1] |
auto[1] |
auto[1] |
1024753 |
1 |
|
|
T21 |
313 |
|
T24 |
6 |
|
T25 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |