Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097857 |
1 |
|
|
T20 |
1 |
|
T21 |
1411 |
|
T22 |
365 |
| auto[1] |
4932485 |
1 |
|
|
T21 |
1176 |
|
T24 |
78 |
|
T25 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2163069 |
1 |
|
|
T21 |
511 |
|
T24 |
36 |
|
T25 |
32 |
| auto[1] |
auto[0] |
auto[1] |
318180 |
1 |
|
|
T21 |
127 |
|
T24 |
4 |
|
T25 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2137172 |
1 |
|
|
T21 |
430 |
|
T24 |
37 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[1] |
314064 |
1 |
|
|
T21 |
108 |
|
T24 |
1 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |