Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7117473 |
1 |
|
|
T20 |
1 |
|
T21 |
1171 |
|
T22 |
365 |
| auto[1] |
4912869 |
1 |
|
|
T21 |
1416 |
|
T24 |
59 |
|
T25 |
51 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9964530 |
1 |
|
|
T20 |
1 |
|
T21 |
1900 |
|
T22 |
365 |
| auto[1] |
2065812 |
1 |
|
|
T21 |
687 |
|
T24 |
70 |
|
T25 |
42 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7099095 |
1 |
|
|
T20 |
1 |
|
T21 |
1152 |
|
T22 |
365 |
| auto[1] |
4931247 |
1 |
|
|
T21 |
1435 |
|
T24 |
119 |
|
T25 |
55 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1433322 |
1 |
|
|
T21 |
365 |
|
T24 |
27 |
|
T25 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1039642 |
1 |
|
|
T21 |
315 |
|
T24 |
44 |
|
T25 |
16 |
| auto[1] |
auto[1] |
auto[0] |
1432113 |
1 |
|
|
T21 |
383 |
|
T24 |
22 |
|
T25 |
5 |
| auto[1] |
auto[1] |
auto[1] |
1026170 |
1 |
|
|
T21 |
372 |
|
T24 |
26 |
|
T25 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |