Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7101140 |
1 |
|
|
T20 |
1 |
|
T21 |
1551 |
|
T22 |
365 |
| auto[1] |
4929202 |
1 |
|
|
T21 |
1036 |
|
T24 |
36 |
|
T25 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9975255 |
1 |
|
|
T20 |
1 |
|
T21 |
1956 |
|
T22 |
365 |
| auto[1] |
2055087 |
1 |
|
|
T21 |
631 |
|
T24 |
32 |
|
T25 |
35 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7107243 |
1 |
|
|
T20 |
1 |
|
T21 |
1272 |
|
T22 |
365 |
| auto[1] |
4923099 |
1 |
|
|
T21 |
1315 |
|
T24 |
77 |
|
T25 |
70 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1446984 |
1 |
|
|
T21 |
383 |
|
T24 |
39 |
|
T25 |
32 |
| auto[1] |
auto[0] |
auto[1] |
1033837 |
1 |
|
|
T21 |
357 |
|
T24 |
30 |
|
T25 |
23 |
| auto[1] |
auto[1] |
auto[0] |
1421028 |
1 |
|
|
T21 |
301 |
|
T24 |
6 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[1] |
1021250 |
1 |
|
|
T21 |
274 |
|
T24 |
2 |
|
T25 |
12 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |