Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7103499 |
1 |
|
|
T20 |
1 |
|
T21 |
1383 |
|
T22 |
365 |
| auto[1] |
4926843 |
1 |
|
|
T21 |
1204 |
|
T24 |
21 |
|
T25 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9961366 |
1 |
|
|
T20 |
1 |
|
T21 |
2047 |
|
T22 |
365 |
| auto[1] |
2068976 |
1 |
|
|
T21 |
540 |
|
T24 |
42 |
|
T25 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7076939 |
1 |
|
|
T20 |
1 |
|
T21 |
1516 |
|
T22 |
365 |
| auto[1] |
4953403 |
1 |
|
|
T21 |
1071 |
|
T24 |
55 |
|
T25 |
64 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1442306 |
1 |
|
|
T21 |
321 |
|
T24 |
13 |
|
T25 |
26 |
| auto[1] |
auto[0] |
auto[1] |
1033294 |
1 |
|
|
T21 |
312 |
|
T24 |
36 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1442121 |
1 |
|
|
T21 |
210 |
|
T25 |
15 |
|
T1 |
87 |
| auto[1] |
auto[1] |
auto[1] |
1035682 |
1 |
|
|
T21 |
228 |
|
T24 |
6 |
|
T25 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |