Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100600 |
1 |
|
|
T20 |
1 |
|
T21 |
1305 |
|
T22 |
365 |
| auto[1] |
4929742 |
1 |
|
|
T21 |
1282 |
|
T24 |
54 |
|
T25 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9971269 |
1 |
|
|
T20 |
1 |
|
T21 |
1901 |
|
T22 |
365 |
| auto[1] |
2059073 |
1 |
|
|
T21 |
686 |
|
T24 |
44 |
|
T25 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7114862 |
1 |
|
|
T20 |
1 |
|
T21 |
1286 |
|
T22 |
365 |
| auto[1] |
4915480 |
1 |
|
|
T21 |
1301 |
|
T24 |
107 |
|
T25 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1424289 |
1 |
|
|
T21 |
313 |
|
T24 |
39 |
|
T25 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1031713 |
1 |
|
|
T21 |
343 |
|
T24 |
31 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1432118 |
1 |
|
|
T21 |
302 |
|
T24 |
24 |
|
T1 |
36 |
| auto[1] |
auto[1] |
auto[1] |
1027360 |
1 |
|
|
T21 |
343 |
|
T24 |
13 |
|
T1 |
245 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |