Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7099508 |
1 |
|
|
T20 |
1 |
|
T21 |
1057 |
|
T22 |
365 |
| auto[1] |
4930834 |
1 |
|
|
T21 |
1530 |
|
T24 |
42 |
|
T25 |
49 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9965719 |
1 |
|
|
T20 |
1 |
|
T21 |
1915 |
|
T22 |
365 |
| auto[1] |
2064623 |
1 |
|
|
T21 |
672 |
|
T24 |
47 |
|
T25 |
12 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7081909 |
1 |
|
|
T20 |
1 |
|
T21 |
1207 |
|
T22 |
365 |
| auto[1] |
4948433 |
1 |
|
|
T21 |
1380 |
|
T24 |
77 |
|
T25 |
55 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1437284 |
1 |
|
|
T21 |
271 |
|
T24 |
28 |
|
T25 |
34 |
| auto[1] |
auto[0] |
auto[1] |
1033407 |
1 |
|
|
T21 |
264 |
|
T24 |
38 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1446526 |
1 |
|
|
T21 |
437 |
|
T24 |
2 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[1] |
1031216 |
1 |
|
|
T21 |
408 |
|
T24 |
9 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |