Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096805 |
1 |
|
|
T20 |
1 |
|
T21 |
1271 |
|
T22 |
365 |
| auto[1] |
4933537 |
1 |
|
|
T21 |
1316 |
|
T24 |
67 |
|
T25 |
52 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9967470 |
1 |
|
|
T20 |
1 |
|
T21 |
1837 |
|
T22 |
365 |
| auto[1] |
2062872 |
1 |
|
|
T21 |
750 |
|
T24 |
61 |
|
T25 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7082157 |
1 |
|
|
T20 |
1 |
|
T21 |
1153 |
|
T22 |
365 |
| auto[1] |
4948185 |
1 |
|
|
T21 |
1434 |
|
T24 |
134 |
|
T25 |
30 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1440165 |
1 |
|
|
T21 |
349 |
|
T24 |
41 |
|
T25 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1030084 |
1 |
|
|
T21 |
379 |
|
T24 |
40 |
|
T25 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1445148 |
1 |
|
|
T21 |
335 |
|
T24 |
32 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[1] |
1032788 |
1 |
|
|
T21 |
371 |
|
T24 |
21 |
|
T25 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |