Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7104185 |
1 |
|
|
T20 |
1 |
|
T21 |
1539 |
|
T22 |
365 |
| auto[1] |
4926157 |
1 |
|
|
T21 |
1048 |
|
T24 |
46 |
|
T25 |
58 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9968554 |
1 |
|
|
T20 |
1 |
|
T21 |
2099 |
|
T22 |
365 |
| auto[1] |
2061788 |
1 |
|
|
T21 |
488 |
|
T24 |
28 |
|
T25 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092417 |
1 |
|
|
T20 |
1 |
|
T21 |
1590 |
|
T22 |
365 |
| auto[1] |
4937925 |
1 |
|
|
T21 |
997 |
|
T24 |
52 |
|
T25 |
55 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1441272 |
1 |
|
|
T21 |
228 |
|
T24 |
14 |
|
T25 |
9 |
| auto[1] |
auto[0] |
auto[1] |
1033141 |
1 |
|
|
T21 |
242 |
|
T24 |
20 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1434865 |
1 |
|
|
T21 |
281 |
|
T24 |
10 |
|
T25 |
41 |
| auto[1] |
auto[1] |
auto[1] |
1028647 |
1 |
|
|
T21 |
246 |
|
T24 |
8 |
|
T25 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |