Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100003 |
1 |
|
|
T20 |
1 |
|
T21 |
1108 |
|
T22 |
365 |
| auto[1] |
4930339 |
1 |
|
|
T21 |
1479 |
|
T24 |
114 |
|
T25 |
47 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9979734 |
1 |
|
|
T20 |
1 |
|
T21 |
2063 |
|
T22 |
365 |
| auto[1] |
2050608 |
1 |
|
|
T21 |
524 |
|
T24 |
16 |
|
T25 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7102155 |
1 |
|
|
T20 |
1 |
|
T21 |
1512 |
|
T22 |
365 |
| auto[1] |
4928187 |
1 |
|
|
T21 |
1075 |
|
T24 |
43 |
|
T25 |
46 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1435495 |
1 |
|
|
T21 |
210 |
|
T24 |
17 |
|
T25 |
8 |
| auto[1] |
auto[0] |
auto[1] |
1021003 |
1 |
|
|
T21 |
198 |
|
T24 |
6 |
|
T25 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1442084 |
1 |
|
|
T21 |
341 |
|
T24 |
10 |
|
T25 |
12 |
| auto[1] |
auto[1] |
auto[1] |
1029605 |
1 |
|
|
T21 |
326 |
|
T24 |
10 |
|
T25 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |