Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7092952 |
1 |
|
|
T20 |
1 |
|
T21 |
1219 |
|
T22 |
365 |
| auto[1] |
4937390 |
1 |
|
|
T21 |
1368 |
|
T24 |
80 |
|
T25 |
60 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9973018 |
1 |
|
|
T20 |
1 |
|
T21 |
1965 |
|
T22 |
365 |
| auto[1] |
2057324 |
1 |
|
|
T21 |
622 |
|
T24 |
64 |
|
T25 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097076 |
1 |
|
|
T20 |
1 |
|
T21 |
1381 |
|
T22 |
365 |
| auto[1] |
4933266 |
1 |
|
|
T21 |
1206 |
|
T24 |
126 |
|
T25 |
67 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1442254 |
1 |
|
|
T21 |
221 |
|
T24 |
27 |
|
T25 |
33 |
| auto[1] |
auto[0] |
auto[1] |
1030448 |
1 |
|
|
T21 |
254 |
|
T24 |
34 |
|
T25 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1433688 |
1 |
|
|
T21 |
363 |
|
T24 |
35 |
|
T25 |
17 |
| auto[1] |
auto[1] |
auto[1] |
1026876 |
1 |
|
|
T21 |
368 |
|
T24 |
30 |
|
T25 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |