Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7135333 |
1 |
|
|
T20 |
1 |
|
T21 |
1481 |
|
T22 |
365 |
| auto[1] |
4895009 |
1 |
|
|
T21 |
1106 |
|
T24 |
93 |
|
T25 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9982850 |
1 |
|
|
T20 |
1 |
|
T21 |
2031 |
|
T22 |
365 |
| auto[1] |
2047492 |
1 |
|
|
T21 |
556 |
|
T24 |
40 |
|
T25 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7132623 |
1 |
|
|
T20 |
1 |
|
T21 |
1531 |
|
T22 |
365 |
| auto[1] |
4897719 |
1 |
|
|
T21 |
1056 |
|
T24 |
98 |
|
T25 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1428361 |
1 |
|
|
T21 |
274 |
|
T24 |
13 |
|
T25 |
26 |
| auto[1] |
auto[0] |
auto[1] |
1026518 |
1 |
|
|
T21 |
323 |
|
T24 |
17 |
|
T25 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1421866 |
1 |
|
|
T21 |
226 |
|
T24 |
45 |
|
T1 |
57 |
| auto[1] |
auto[1] |
auto[1] |
1020974 |
1 |
|
|
T21 |
233 |
|
T24 |
23 |
|
T1 |
192 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |