Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7100141 |
1 |
|
|
T20 |
1 |
|
T21 |
1278 |
|
T22 |
365 |
| auto[1] |
4930201 |
1 |
|
|
T21 |
1309 |
|
T24 |
74 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9965094 |
1 |
|
|
T20 |
1 |
|
T21 |
2000 |
|
T22 |
365 |
| auto[1] |
2065248 |
1 |
|
|
T21 |
587 |
|
T24 |
43 |
|
T25 |
40 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7085376 |
1 |
|
|
T20 |
1 |
|
T21 |
1421 |
|
T22 |
365 |
| auto[1] |
4944966 |
1 |
|
|
T21 |
1166 |
|
T24 |
87 |
|
T25 |
85 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1435280 |
1 |
|
|
T21 |
282 |
|
T24 |
25 |
|
T25 |
34 |
| auto[1] |
auto[0] |
auto[1] |
1032378 |
1 |
|
|
T21 |
264 |
|
T24 |
30 |
|
T25 |
36 |
| auto[1] |
auto[1] |
auto[0] |
1444438 |
1 |
|
|
T21 |
297 |
|
T24 |
19 |
|
T25 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1032870 |
1 |
|
|
T21 |
323 |
|
T24 |
13 |
|
T25 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |