Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7116915 |
1 |
|
|
T20 |
1 |
|
T21 |
1298 |
|
T22 |
365 |
| auto[1] |
4913427 |
1 |
|
|
T21 |
1289 |
|
T24 |
88 |
|
T25 |
46 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11399372 |
1 |
|
|
T20 |
1 |
|
T21 |
2352 |
|
T22 |
365 |
| auto[1] |
630970 |
1 |
|
|
T21 |
235 |
|
T24 |
9 |
|
T25 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7102122 |
1 |
|
|
T20 |
1 |
|
T21 |
1380 |
|
T22 |
365 |
| auto[1] |
4928220 |
1 |
|
|
T21 |
1207 |
|
T24 |
84 |
|
T25 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2150269 |
1 |
|
|
T21 |
472 |
|
T24 |
28 |
|
T25 |
28 |
| auto[1] |
auto[0] |
auto[1] |
315660 |
1 |
|
|
T21 |
113 |
|
T24 |
4 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2146981 |
1 |
|
|
T21 |
500 |
|
T24 |
47 |
|
T25 |
19 |
| auto[1] |
auto[1] |
auto[1] |
315310 |
1 |
|
|
T21 |
122 |
|
T24 |
5 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |