Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7061989 |
1 |
|
|
T20 |
1 |
|
T21 |
1194 |
|
T22 |
365 |
| auto[1] |
4968353 |
1 |
|
|
T21 |
1393 |
|
T24 |
69 |
|
T25 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11399060 |
1 |
|
|
T20 |
1 |
|
T21 |
2308 |
|
T22 |
365 |
| auto[1] |
631282 |
1 |
|
|
T21 |
279 |
|
T24 |
6 |
|
T25 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7104369 |
1 |
|
|
T20 |
1 |
|
T21 |
1207 |
|
T22 |
365 |
| auto[1] |
4925973 |
1 |
|
|
T21 |
1380 |
|
T24 |
73 |
|
T25 |
63 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2134919 |
1 |
|
|
T21 |
430 |
|
T24 |
34 |
|
T25 |
38 |
| auto[1] |
auto[0] |
auto[1] |
313092 |
1 |
|
|
T21 |
103 |
|
T24 |
5 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2159772 |
1 |
|
|
T21 |
671 |
|
T24 |
33 |
|
T25 |
20 |
| auto[1] |
auto[1] |
auto[1] |
318190 |
1 |
|
|
T21 |
176 |
|
T24 |
1 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |