Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7086968 |
1 |
|
|
T20 |
1 |
|
T21 |
1108 |
|
T22 |
365 |
| auto[1] |
4943374 |
1 |
|
|
T21 |
1479 |
|
T24 |
47 |
|
T25 |
83 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11401570 |
1 |
|
|
T20 |
1 |
|
T21 |
2380 |
|
T22 |
365 |
| auto[1] |
628772 |
1 |
|
|
T21 |
207 |
|
T24 |
8 |
|
T25 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7116517 |
1 |
|
|
T20 |
1 |
|
T21 |
1462 |
|
T22 |
365 |
| auto[1] |
4913825 |
1 |
|
|
T21 |
1125 |
|
T24 |
82 |
|
T25 |
83 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2140435 |
1 |
|
|
T21 |
436 |
|
T24 |
52 |
|
T25 |
23 |
| auto[1] |
auto[0] |
auto[1] |
312735 |
1 |
|
|
T21 |
99 |
|
T24 |
7 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2144618 |
1 |
|
|
T21 |
482 |
|
T24 |
22 |
|
T25 |
54 |
| auto[1] |
auto[1] |
auto[1] |
316037 |
1 |
|
|
T21 |
108 |
|
T24 |
1 |
|
T25 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |