Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7119912 |
1 |
|
|
T20 |
1 |
|
T21 |
1437 |
|
T22 |
365 |
| auto[1] |
4910430 |
1 |
|
|
T21 |
1150 |
|
T24 |
101 |
|
T25 |
62 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11401482 |
1 |
|
|
T20 |
1 |
|
T21 |
2354 |
|
T22 |
365 |
| auto[1] |
628860 |
1 |
|
|
T21 |
233 |
|
T24 |
10 |
|
T1 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7112725 |
1 |
|
|
T20 |
1 |
|
T21 |
1393 |
|
T22 |
365 |
| auto[1] |
4917617 |
1 |
|
|
T21 |
1194 |
|
T24 |
104 |
|
T25 |
14 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2160775 |
1 |
|
|
T21 |
528 |
|
T24 |
40 |
|
T1 |
316 |
| auto[1] |
auto[0] |
auto[1] |
317343 |
1 |
|
|
T21 |
127 |
|
T24 |
4 |
|
T1 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2127982 |
1 |
|
|
T21 |
433 |
|
T24 |
54 |
|
T25 |
14 |
| auto[1] |
auto[1] |
auto[1] |
311517 |
1 |
|
|
T21 |
106 |
|
T24 |
6 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |