Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7090795 |
1 |
|
|
T20 |
1 |
|
T21 |
1185 |
|
T22 |
365 |
| auto[1] |
4939547 |
1 |
|
|
T21 |
1402 |
|
T24 |
76 |
|
T25 |
28 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11396924 |
1 |
|
|
T20 |
1 |
|
T21 |
2285 |
|
T22 |
365 |
| auto[1] |
633418 |
1 |
|
|
T21 |
302 |
|
T24 |
12 |
|
T25 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7089977 |
1 |
|
|
T20 |
1 |
|
T21 |
1038 |
|
T22 |
365 |
| auto[1] |
4940365 |
1 |
|
|
T21 |
1549 |
|
T24 |
90 |
|
T25 |
39 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2147258 |
1 |
|
|
T21 |
598 |
|
T24 |
60 |
|
T25 |
29 |
| auto[1] |
auto[0] |
auto[1] |
314746 |
1 |
|
|
T21 |
134 |
|
T24 |
10 |
|
T25 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2159689 |
1 |
|
|
T21 |
649 |
|
T24 |
18 |
|
T25 |
5 |
| auto[1] |
auto[1] |
auto[1] |
318672 |
1 |
|
|
T21 |
168 |
|
T24 |
2 |
|
T1 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |