Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097816 |
1 |
|
|
T20 |
1 |
|
T21 |
1579 |
|
T22 |
365 |
| auto[1] |
4932526 |
1 |
|
|
T21 |
1008 |
|
T24 |
81 |
|
T25 |
92 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11397856 |
1 |
|
|
T20 |
1 |
|
T21 |
2329 |
|
T22 |
365 |
| auto[1] |
632486 |
1 |
|
|
T21 |
258 |
|
T24 |
9 |
|
T25 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7096495 |
1 |
|
|
T20 |
1 |
|
T21 |
1332 |
|
T22 |
365 |
| auto[1] |
4933847 |
1 |
|
|
T21 |
1255 |
|
T24 |
114 |
|
T25 |
50 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2151274 |
1 |
|
|
T21 |
603 |
|
T24 |
44 |
|
T25 |
5 |
| auto[1] |
auto[0] |
auto[1] |
315854 |
1 |
|
|
T21 |
153 |
|
T24 |
4 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2150087 |
1 |
|
|
T21 |
394 |
|
T24 |
61 |
|
T25 |
43 |
| auto[1] |
auto[1] |
auto[1] |
316632 |
1 |
|
|
T21 |
105 |
|
T24 |
5 |
|
T25 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |