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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T759 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1810275760 Jul 23 06:48:54 PM PDT 24 Jul 23 06:48:58 PM PDT 24 83240645 ps
T760 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1619109366 Jul 23 06:48:24 PM PDT 24 Jul 23 06:48:33 PM PDT 24 20806341 ps
T761 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.219005120 Jul 23 06:48:25 PM PDT 24 Jul 23 06:48:35 PM PDT 24 22502726 ps
T762 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.448303166 Jul 23 06:48:46 PM PDT 24 Jul 23 06:48:51 PM PDT 24 93988559 ps
T763 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3614635686 Jul 23 06:48:52 PM PDT 24 Jul 23 06:48:57 PM PDT 24 16151177 ps
T764 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2136768785 Jul 23 06:48:33 PM PDT 24 Jul 23 06:48:42 PM PDT 24 70465046 ps
T765 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2983784665 Jul 23 06:48:38 PM PDT 24 Jul 23 06:48:46 PM PDT 24 129266478 ps
T766 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1261682243 Jul 23 06:48:41 PM PDT 24 Jul 23 06:48:47 PM PDT 24 18011234 ps
T38 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.275483474 Jul 23 06:48:24 PM PDT 24 Jul 23 06:48:35 PM PDT 24 83681049 ps
T767 /workspace/coverage/cover_reg_top/33.gpio_intr_test.3347278599 Jul 23 06:48:48 PM PDT 24 Jul 23 06:48:53 PM PDT 24 52031120 ps
T768 /workspace/coverage/cover_reg_top/43.gpio_intr_test.4223892523 Jul 23 06:48:49 PM PDT 24 Jul 23 06:48:54 PM PDT 24 12660750 ps
T769 /workspace/coverage/cover_reg_top/8.gpio_intr_test.559166201 Jul 23 06:48:52 PM PDT 24 Jul 23 06:48:58 PM PDT 24 42482014 ps
T73 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2812847055 Jul 23 06:48:26 PM PDT 24 Jul 23 06:48:36 PM PDT 24 15567247 ps
T770 /workspace/coverage/cover_reg_top/37.gpio_intr_test.1704214978 Jul 23 06:48:48 PM PDT 24 Jul 23 06:48:53 PM PDT 24 14061022 ps
T39 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1268590941 Jul 23 06:48:38 PM PDT 24 Jul 23 06:48:46 PM PDT 24 51076415 ps
T40 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3059197770 Jul 23 06:48:42 PM PDT 24 Jul 23 06:48:48 PM PDT 24 847270541 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1062314094 Jul 23 06:48:37 PM PDT 24 Jul 23 06:48:44 PM PDT 24 61779540 ps
T772 /workspace/coverage/cover_reg_top/29.gpio_intr_test.4266778353 Jul 23 06:48:54 PM PDT 24 Jul 23 06:48:59 PM PDT 24 20642037 ps
T773 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.773045017 Jul 23 06:48:36 PM PDT 24 Jul 23 06:48:44 PM PDT 24 24863864 ps
T774 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.544863119 Jul 23 06:48:52 PM PDT 24 Jul 23 06:48:58 PM PDT 24 164090136 ps
T41 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2817544608 Jul 23 06:48:35 PM PDT 24 Jul 23 06:48:44 PM PDT 24 281942448 ps
T775 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2611772480 Jul 23 06:48:31 PM PDT 24 Jul 23 06:48:41 PM PDT 24 363284592 ps
T776 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1582585756 Jul 23 06:48:49 PM PDT 24 Jul 23 06:48:54 PM PDT 24 27423081 ps
T74 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3427742843 Jul 23 06:48:24 PM PDT 24 Jul 23 06:48:33 PM PDT 24 16935761 ps
T777 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1641659221 Jul 23 06:48:47 PM PDT 24 Jul 23 06:48:52 PM PDT 24 15131449 ps
T778 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2171305089 Jul 23 06:48:35 PM PDT 24 Jul 23 06:48:43 PM PDT 24 174409233 ps
T779 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2486465057 Jul 23 06:48:49 PM PDT 24 Jul 23 06:48:57 PM PDT 24 329997894 ps
T780 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2351851956 Jul 23 06:48:24 PM PDT 24 Jul 23 06:48:33 PM PDT 24 27481342 ps
T781 /workspace/coverage/cover_reg_top/12.gpio_intr_test.1863367350 Jul 23 06:48:38 PM PDT 24 Jul 23 06:48:45 PM PDT 24 41057551 ps
T782 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2990287821 Jul 23 06:49:00 PM PDT 24 Jul 23 06:49:02 PM PDT 24 22403968 ps
T783 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1269737525 Jul 23 06:48:51 PM PDT 24 Jul 23 06:48:57 PM PDT 24 71812303 ps
T784 /workspace/coverage/cover_reg_top/27.gpio_intr_test.221540922 Jul 23 06:48:57 PM PDT 24 Jul 23 06:49:00 PM PDT 24 12780639 ps
T785 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2870347588 Jul 23 06:48:42 PM PDT 24 Jul 23 06:48:48 PM PDT 24 35972415 ps
T786 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3140488831 Jul 23 06:48:47 PM PDT 24 Jul 23 06:48:52 PM PDT 24 58523790 ps
T787 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.669047053 Jul 23 06:48:45 PM PDT 24 Jul 23 06:48:49 PM PDT 24 41609490 ps
T788 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3171793042 Jul 23 06:48:41 PM PDT 24 Jul 23 06:48:48 PM PDT 24 29943683 ps
T789 /workspace/coverage/cover_reg_top/3.gpio_intr_test.4157495877 Jul 23 06:48:24 PM PDT 24 Jul 23 06:48:33 PM PDT 24 18726005 ps
T790 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2030552312 Jul 23 06:48:42 PM PDT 24 Jul 23 06:48:47 PM PDT 24 20941022 ps
T75 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1283437931 Jul 23 06:48:32 PM PDT 24 Jul 23 06:48:43 PM PDT 24 766457382 ps
T791 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1001015723 Jul 23 06:48:55 PM PDT 24 Jul 23 06:48:59 PM PDT 24 39342128 ps
T792 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2510773437 Jul 23 06:48:48 PM PDT 24 Jul 23 06:48:53 PM PDT 24 18756855 ps
T793 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2555834076 Jul 23 06:49:02 PM PDT 24 Jul 23 06:49:04 PM PDT 24 69715504 ps
T794 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1396576443 Jul 23 06:48:46 PM PDT 24 Jul 23 06:48:50 PM PDT 24 191971036 ps
T795 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.622152436 Jul 23 06:48:22 PM PDT 24 Jul 23 06:48:29 PM PDT 24 44474419 ps
T796 /workspace/coverage/cover_reg_top/46.gpio_intr_test.774861394 Jul 23 06:48:55 PM PDT 24 Jul 23 06:49:00 PM PDT 24 50549050 ps
T797 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.306748886 Jul 23 06:48:26 PM PDT 24 Jul 23 06:48:37 PM PDT 24 36134711 ps
T798 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1735591514 Jul 23 06:48:47 PM PDT 24 Jul 23 06:48:53 PM PDT 24 39567335 ps
T799 /workspace/coverage/cover_reg_top/22.gpio_intr_test.3219707130 Jul 23 06:48:58 PM PDT 24 Jul 23 06:49:01 PM PDT 24 40067713 ps
T800 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4217396769 Jul 23 06:48:47 PM PDT 24 Jul 23 06:48:53 PM PDT 24 76925715 ps
T801 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4284900847 Jul 23 06:48:30 PM PDT 24 Jul 23 06:48:40 PM PDT 24 161247335 ps
T802 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.513838227 Jul 23 06:48:24 PM PDT 24 Jul 23 06:48:35 PM PDT 24 530507632 ps
T803 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.109481798 Jul 23 06:48:46 PM PDT 24 Jul 23 06:48:51 PM PDT 24 229169331 ps
T804 /workspace/coverage/cover_reg_top/30.gpio_intr_test.1142047107 Jul 23 06:48:57 PM PDT 24 Jul 23 06:49:01 PM PDT 24 12267107 ps
T805 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2265269719 Jul 23 06:48:33 PM PDT 24 Jul 23 06:48:43 PM PDT 24 168677270 ps
T806 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.252506004 Jul 23 06:48:37 PM PDT 24 Jul 23 06:48:45 PM PDT 24 277172611 ps
T807 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2070827838 Jul 23 06:48:32 PM PDT 24 Jul 23 06:48:44 PM PDT 24 23921757 ps
T808 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1093924840 Jul 23 06:48:53 PM PDT 24 Jul 23 06:48:58 PM PDT 24 65871073 ps
T809 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1819321015 Jul 23 06:48:46 PM PDT 24 Jul 23 06:48:51 PM PDT 24 181244292 ps
T810 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4205303293 Jul 23 06:48:33 PM PDT 24 Jul 23 06:48:42 PM PDT 24 44679102 ps
T811 /workspace/coverage/cover_reg_top/1.gpio_intr_test.4275274939 Jul 23 06:48:31 PM PDT 24 Jul 23 06:48:40 PM PDT 24 119779293 ps
T812 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2107114399 Jul 23 06:48:35 PM PDT 24 Jul 23 06:48:43 PM PDT 24 53162800 ps
T813 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1247345413 Jul 23 06:48:25 PM PDT 24 Jul 23 06:48:35 PM PDT 24 16733891 ps
T76 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3023354973 Jul 23 06:48:37 PM PDT 24 Jul 23 06:48:45 PM PDT 24 22048928 ps
T814 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3440117266 Jul 23 06:48:59 PM PDT 24 Jul 23 06:49:02 PM PDT 24 10941167 ps
T815 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3268334211 Jul 23 06:48:46 PM PDT 24 Jul 23 06:48:51 PM PDT 24 39278530 ps
T816 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2338894047 Jul 23 06:48:57 PM PDT 24 Jul 23 06:49:01 PM PDT 24 36541441 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2964255216 Jul 23 06:48:33 PM PDT 24 Jul 23 06:48:41 PM PDT 24 55848948 ps
T818 /workspace/coverage/cover_reg_top/34.gpio_intr_test.492548797 Jul 23 06:48:57 PM PDT 24 Jul 23 06:49:01 PM PDT 24 19748032 ps
T819 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2539246841 Jul 23 06:48:50 PM PDT 24 Jul 23 06:48:57 PM PDT 24 191795133 ps
T820 /workspace/coverage/cover_reg_top/5.gpio_intr_test.162923519 Jul 23 06:48:35 PM PDT 24 Jul 23 06:48:43 PM PDT 24 31831025 ps
T821 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3290207897 Jul 23 06:48:43 PM PDT 24 Jul 23 06:48:49 PM PDT 24 181221256 ps
T822 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3272487993 Jul 23 06:48:48 PM PDT 24 Jul 23 06:48:53 PM PDT 24 43926249 ps
T823 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3852558781 Jul 23 06:48:24 PM PDT 24 Jul 23 06:48:36 PM PDT 24 385109053 ps
T824 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2262239228 Jul 23 06:48:36 PM PDT 24 Jul 23 06:48:44 PM PDT 24 51213285 ps
T825 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4138677266 Jul 23 06:48:24 PM PDT 24 Jul 23 06:48:34 PM PDT 24 301315661 ps
T826 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3248429350 Jul 23 06:48:58 PM PDT 24 Jul 23 06:49:02 PM PDT 24 30337673 ps
T827 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3969489348 Jul 23 06:48:48 PM PDT 24 Jul 23 06:48:54 PM PDT 24 388365099 ps
T828 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3895002772 Jul 23 06:48:32 PM PDT 24 Jul 23 06:48:41 PM PDT 24 30435904 ps
T829 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.528397878 Jul 23 06:48:22 PM PDT 24 Jul 23 06:48:32 PM PDT 24 94127901 ps
T830 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1545681531 Jul 23 06:48:33 PM PDT 24 Jul 23 06:48:41 PM PDT 24 38942549 ps
T831 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.808249746 Jul 23 06:48:37 PM PDT 24 Jul 23 06:48:45 PM PDT 24 27766160 ps
T832 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2689972562 Jul 23 06:48:38 PM PDT 24 Jul 23 06:48:46 PM PDT 24 91693606 ps
T833 /workspace/coverage/cover_reg_top/14.gpio_intr_test.2453649547 Jul 23 06:48:53 PM PDT 24 Jul 23 06:48:58 PM PDT 24 15447962 ps
T834 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2934830186 Jul 23 06:48:49 PM PDT 24 Jul 23 06:48:55 PM PDT 24 19953342 ps
T835 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1963346582 Jul 23 06:48:33 PM PDT 24 Jul 23 06:48:41 PM PDT 24 13273236 ps
T836 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2053675696 Jul 23 06:48:23 PM PDT 24 Jul 23 06:48:32 PM PDT 24 31291123 ps
T837 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1756073734 Jul 23 06:48:49 PM PDT 24 Jul 23 06:48:55 PM PDT 24 133087443 ps
T838 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3180508569 Jul 23 06:48:52 PM PDT 24 Jul 23 06:48:57 PM PDT 24 60636510 ps
T839 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3321502677 Jul 23 06:48:33 PM PDT 24 Jul 23 06:48:41 PM PDT 24 24474659 ps
T840 /workspace/coverage/cover_reg_top/48.gpio_intr_test.301765987 Jul 23 06:48:49 PM PDT 24 Jul 23 06:48:55 PM PDT 24 85164506 ps
T841 /workspace/coverage/cover_reg_top/45.gpio_intr_test.577266418 Jul 23 06:48:48 PM PDT 24 Jul 23 06:48:54 PM PDT 24 50926654 ps
T842 /workspace/coverage/cover_reg_top/44.gpio_intr_test.3764763030 Jul 23 06:48:51 PM PDT 24 Jul 23 06:48:56 PM PDT 24 40177364 ps
T843 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3305842647 Jul 23 06:48:36 PM PDT 24 Jul 23 06:48:46 PM PDT 24 290815020 ps
T844 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3975459668 Jul 23 06:49:44 PM PDT 24 Jul 23 06:49:46 PM PDT 24 182515253 ps
T845 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3430314906 Jul 23 06:50:13 PM PDT 24 Jul 23 06:50:15 PM PDT 24 36259944 ps
T846 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3716896824 Jul 23 06:49:39 PM PDT 24 Jul 23 06:49:40 PM PDT 24 1106268243 ps
T847 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4052053246 Jul 23 06:49:39 PM PDT 24 Jul 23 06:49:41 PM PDT 24 36003307 ps
T848 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1967820389 Jul 23 06:50:16 PM PDT 24 Jul 23 06:50:18 PM PDT 24 354833208 ps
T849 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2724582200 Jul 23 06:50:08 PM PDT 24 Jul 23 06:50:10 PM PDT 24 49262914 ps
T850 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3476690272 Jul 23 06:50:13 PM PDT 24 Jul 23 06:50:16 PM PDT 24 167298694 ps
T851 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.153386174 Jul 23 06:50:12 PM PDT 24 Jul 23 06:50:13 PM PDT 24 29260729 ps
T852 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3824516212 Jul 23 06:49:48 PM PDT 24 Jul 23 06:49:51 PM PDT 24 368667473 ps
T853 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1750548350 Jul 23 06:50:13 PM PDT 24 Jul 23 06:50:16 PM PDT 24 161441342 ps
T854 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2901993243 Jul 23 06:50:13 PM PDT 24 Jul 23 06:50:15 PM PDT 24 44243104 ps
T855 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.904113791 Jul 23 06:49:48 PM PDT 24 Jul 23 06:49:49 PM PDT 24 131301189 ps
T856 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.540987203 Jul 23 06:49:44 PM PDT 24 Jul 23 06:49:46 PM PDT 24 257543755 ps
T857 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4232823865 Jul 23 06:49:46 PM PDT 24 Jul 23 06:49:49 PM PDT 24 47578624 ps
T858 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3136039479 Jul 23 06:49:59 PM PDT 24 Jul 23 06:50:01 PM PDT 24 59111820 ps
T859 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2100180044 Jul 23 06:49:39 PM PDT 24 Jul 23 06:49:41 PM PDT 24 72275403 ps
T860 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3453608534 Jul 23 06:50:13 PM PDT 24 Jul 23 06:50:16 PM PDT 24 112731097 ps
T861 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3685575849 Jul 23 06:49:48 PM PDT 24 Jul 23 06:49:50 PM PDT 24 203416725 ps
T862 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3562086536 Jul 23 06:50:08 PM PDT 24 Jul 23 06:50:09 PM PDT 24 29280453 ps
T863 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.538583943 Jul 23 06:49:41 PM PDT 24 Jul 23 06:49:43 PM PDT 24 57246707 ps
T864 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1785246334 Jul 23 06:49:46 PM PDT 24 Jul 23 06:49:49 PM PDT 24 43894168 ps
T865 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.439933397 Jul 23 06:49:48 PM PDT 24 Jul 23 06:49:51 PM PDT 24 289175903 ps
T866 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3147804193 Jul 23 06:49:58 PM PDT 24 Jul 23 06:50:00 PM PDT 24 270160859 ps
T867 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.434989012 Jul 23 06:49:44 PM PDT 24 Jul 23 06:49:47 PM PDT 24 352600643 ps
T868 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4078616498 Jul 23 06:49:43 PM PDT 24 Jul 23 06:49:45 PM PDT 24 176373561 ps
T869 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1163165075 Jul 23 06:50:09 PM PDT 24 Jul 23 06:50:12 PM PDT 24 232990673 ps
T870 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.830575927 Jul 23 06:49:42 PM PDT 24 Jul 23 06:49:44 PM PDT 24 43388318 ps
T871 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.835053535 Jul 23 06:49:53 PM PDT 24 Jul 23 06:49:55 PM PDT 24 152561430 ps
T872 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1872357997 Jul 23 06:49:40 PM PDT 24 Jul 23 06:49:42 PM PDT 24 121156857 ps
T873 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.426992967 Jul 23 06:49:34 PM PDT 24 Jul 23 06:49:35 PM PDT 24 130211557 ps
T874 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1290085685 Jul 23 06:49:48 PM PDT 24 Jul 23 06:49:51 PM PDT 24 230350757 ps
T875 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3313429546 Jul 23 06:49:59 PM PDT 24 Jul 23 06:50:01 PM PDT 24 198998456 ps
T876 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1816930980 Jul 23 06:50:02 PM PDT 24 Jul 23 06:50:03 PM PDT 24 202496588 ps
T877 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1786969005 Jul 23 06:50:05 PM PDT 24 Jul 23 06:50:07 PM PDT 24 141450712 ps
T878 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1438711543 Jul 23 06:50:09 PM PDT 24 Jul 23 06:50:12 PM PDT 24 65422794 ps
T879 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1412534974 Jul 23 06:50:05 PM PDT 24 Jul 23 06:50:07 PM PDT 24 254303891 ps
T880 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3183461014 Jul 23 06:49:43 PM PDT 24 Jul 23 06:49:46 PM PDT 24 41472463 ps
T881 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4207563169 Jul 23 06:50:12 PM PDT 24 Jul 23 06:50:15 PM PDT 24 491788686 ps
T882 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1633411687 Jul 23 06:50:13 PM PDT 24 Jul 23 06:50:15 PM PDT 24 108452743 ps
T883 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1645556280 Jul 23 06:49:48 PM PDT 24 Jul 23 06:49:50 PM PDT 24 119581201 ps
T884 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1603789394 Jul 23 06:49:58 PM PDT 24 Jul 23 06:50:00 PM PDT 24 228372296 ps
T885 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.29796407 Jul 23 06:49:51 PM PDT 24 Jul 23 06:49:53 PM PDT 24 67702336 ps
T886 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.672225048 Jul 23 06:49:58 PM PDT 24 Jul 23 06:50:00 PM PDT 24 295007909 ps
T887 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2710853464 Jul 23 06:49:48 PM PDT 24 Jul 23 06:49:50 PM PDT 24 40069513 ps
T888 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.411759534 Jul 23 06:50:12 PM PDT 24 Jul 23 06:50:14 PM PDT 24 83895044 ps
T889 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3148882773 Jul 23 06:49:34 PM PDT 24 Jul 23 06:49:35 PM PDT 24 38030983 ps
T890 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1089904756 Jul 23 06:49:33 PM PDT 24 Jul 23 06:49:35 PM PDT 24 46633835 ps
T891 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.990645995 Jul 23 06:50:00 PM PDT 24 Jul 23 06:50:02 PM PDT 24 117190232 ps
T892 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1517491958 Jul 23 06:49:58 PM PDT 24 Jul 23 06:50:00 PM PDT 24 54148128 ps
T893 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2934800973 Jul 23 06:50:05 PM PDT 24 Jul 23 06:50:07 PM PDT 24 41281829 ps
T894 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.859691532 Jul 23 06:49:41 PM PDT 24 Jul 23 06:49:44 PM PDT 24 67642525 ps
T895 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3132414330 Jul 23 06:49:45 PM PDT 24 Jul 23 06:49:48 PM PDT 24 167336327 ps
T896 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1628288708 Jul 23 06:50:05 PM PDT 24 Jul 23 06:50:07 PM PDT 24 154771677 ps
T897 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2285089836 Jul 23 06:50:04 PM PDT 24 Jul 23 06:50:05 PM PDT 24 64913953 ps
T898 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4003036537 Jul 23 06:50:09 PM PDT 24 Jul 23 06:50:11 PM PDT 24 30008869 ps
T899 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2583275788 Jul 23 06:49:47 PM PDT 24 Jul 23 06:49:49 PM PDT 24 49860447 ps
T900 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2573257045 Jul 23 06:50:08 PM PDT 24 Jul 23 06:50:10 PM PDT 24 85498642 ps
T901 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.861042238 Jul 23 06:50:01 PM PDT 24 Jul 23 06:50:03 PM PDT 24 146596328 ps
T902 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.387714592 Jul 23 06:50:11 PM PDT 24 Jul 23 06:50:13 PM PDT 24 187980638 ps
T903 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2049871809 Jul 23 06:49:54 PM PDT 24 Jul 23 06:49:56 PM PDT 24 122749238 ps
T904 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1165604428 Jul 23 06:49:50 PM PDT 24 Jul 23 06:49:52 PM PDT 24 82386180 ps
T905 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3065555650 Jul 23 06:50:15 PM PDT 24 Jul 23 06:50:17 PM PDT 24 52368056 ps
T906 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2217534045 Jul 23 06:50:08 PM PDT 24 Jul 23 06:50:10 PM PDT 24 58352259 ps
T907 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4069533324 Jul 23 06:49:37 PM PDT 24 Jul 23 06:49:39 PM PDT 24 308816304 ps
T908 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2128183665 Jul 23 06:49:41 PM PDT 24 Jul 23 06:49:42 PM PDT 24 42909837 ps
T909 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4026406658 Jul 23 06:49:40 PM PDT 24 Jul 23 06:49:43 PM PDT 24 67323960 ps
T910 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4094824988 Jul 23 06:49:49 PM PDT 24 Jul 23 06:49:51 PM PDT 24 1148351364 ps
T911 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2645239165 Jul 23 06:50:13 PM PDT 24 Jul 23 06:50:15 PM PDT 24 162532125 ps
T912 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3322989994 Jul 23 06:49:44 PM PDT 24 Jul 23 06:49:46 PM PDT 24 81976525 ps
T913 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.446437043 Jul 23 06:50:09 PM PDT 24 Jul 23 06:50:11 PM PDT 24 119286233 ps
T914 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.679781817 Jul 23 06:50:08 PM PDT 24 Jul 23 06:50:10 PM PDT 24 191424260 ps
T915 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.504881376 Jul 23 06:50:02 PM PDT 24 Jul 23 06:50:03 PM PDT 24 36449020 ps
T916 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1494571484 Jul 23 06:50:11 PM PDT 24 Jul 23 06:50:12 PM PDT 24 33798712 ps
T917 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2194770865 Jul 23 06:49:48 PM PDT 24 Jul 23 06:49:50 PM PDT 24 173252924 ps
T918 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1348036771 Jul 23 06:50:15 PM PDT 24 Jul 23 06:50:17 PM PDT 24 79167717 ps
T919 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.913355223 Jul 23 06:50:08 PM PDT 24 Jul 23 06:50:10 PM PDT 24 330326125 ps
T920 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.9911778 Jul 23 06:50:03 PM PDT 24 Jul 23 06:50:05 PM PDT 24 508940079 ps
T921 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.525346498 Jul 23 06:49:49 PM PDT 24 Jul 23 06:49:52 PM PDT 24 115545940 ps
T922 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.554262222 Jul 23 06:50:17 PM PDT 24 Jul 23 06:50:19 PM PDT 24 374479669 ps
T923 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1553521720 Jul 23 06:49:50 PM PDT 24 Jul 23 06:49:53 PM PDT 24 244807907 ps
T924 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.796009444 Jul 23 06:49:43 PM PDT 24 Jul 23 06:49:46 PM PDT 24 108525645 ps
T925 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.118205759 Jul 23 06:49:58 PM PDT 24 Jul 23 06:50:00 PM PDT 24 796411119 ps
T926 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1239386335 Jul 23 06:49:43 PM PDT 24 Jul 23 06:49:45 PM PDT 24 240396222 ps
T927 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.499741149 Jul 23 06:49:44 PM PDT 24 Jul 23 06:49:47 PM PDT 24 241554117 ps
T928 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3759073924 Jul 23 06:50:00 PM PDT 24 Jul 23 06:50:02 PM PDT 24 36586895 ps
T929 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3069613518 Jul 23 06:49:49 PM PDT 24 Jul 23 06:49:51 PM PDT 24 35669357 ps
T930 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2831600466 Jul 23 06:49:58 PM PDT 24 Jul 23 06:50:00 PM PDT 24 83643790 ps
T931 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2718085343 Jul 23 06:50:03 PM PDT 24 Jul 23 06:50:05 PM PDT 24 165472993 ps
T932 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1098519807 Jul 23 06:50:09 PM PDT 24 Jul 23 06:50:11 PM PDT 24 425521725 ps
T933 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3415940759 Jul 23 06:49:35 PM PDT 24 Jul 23 06:49:37 PM PDT 24 120198394 ps
T934 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1878373706 Jul 23 06:49:52 PM PDT 24 Jul 23 06:49:54 PM PDT 24 63113129 ps
T935 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3000147565 Jul 23 06:49:50 PM PDT 24 Jul 23 06:49:52 PM PDT 24 42284119 ps
T936 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2984920539 Jul 23 06:49:43 PM PDT 24 Jul 23 06:49:46 PM PDT 24 48956994 ps
T937 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3837673154 Jul 23 06:49:50 PM PDT 24 Jul 23 06:49:52 PM PDT 24 129317770 ps
T938 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2246065003 Jul 23 06:49:50 PM PDT 24 Jul 23 06:49:52 PM PDT 24 64821665 ps
T939 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4189757246 Jul 23 06:49:54 PM PDT 24 Jul 23 06:49:55 PM PDT 24 30907786 ps
T940 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1854741636 Jul 23 06:50:24 PM PDT 24 Jul 23 06:50:28 PM PDT 24 27458231 ps
T941 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.110436426 Jul 23 06:50:05 PM PDT 24 Jul 23 06:50:07 PM PDT 24 95458429 ps
T942 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.194908930 Jul 23 06:49:50 PM PDT 24 Jul 23 06:49:52 PM PDT 24 265656116 ps
T943 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1684461341 Jul 23 06:49:58 PM PDT 24 Jul 23 06:50:00 PM PDT 24 226898425 ps

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3732914500
Short name T2
Test name
Test status
Simulation time 214834070 ps
CPU time 2.73 seconds
Started Jul 23 06:01:43 PM PDT 24
Finished Jul 23 06:01:46 PM PDT 24
Peak memory 198476 kb
Host smart-4b52a779-512f-413d-a808-c06865f91f55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732914500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3732914500
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.4002008634
Short name T16
Test name
Test status
Simulation time 59255920 ps
CPU time 2.34 seconds
Started Jul 23 06:03:36 PM PDT 24
Finished Jul 23 06:03:39 PM PDT 24
Peak memory 198712 kb
Host smart-38bbfacb-9700-433d-87a1-4a228e065b06
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002008634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.4002008634
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2816660094
Short name T28
Test name
Test status
Simulation time 26116326795 ps
CPU time 654.22 seconds
Started Jul 23 06:03:21 PM PDT 24
Finished Jul 23 06:14:17 PM PDT 24
Peak memory 198784 kb
Host smart-a23cb696-6f9f-4f43-9047-657930bb8164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2816660094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2816660094
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3643755445
Short name T33
Test name
Test status
Simulation time 149803535 ps
CPU time 0.94 seconds
Started Jul 23 06:01:20 PM PDT 24
Finished Jul 23 06:01:21 PM PDT 24
Peak memory 215552 kb
Host smart-2addf560-86c0-4e5e-af90-6947284d6cc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643755445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3643755445
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.370039095
Short name T62
Test name
Test status
Simulation time 53543854 ps
CPU time 0.66 seconds
Started Jul 23 06:48:25 PM PDT 24
Finished Jul 23 06:48:35 PM PDT 24
Peak memory 194792 kb
Host smart-fe6bbcec-a244-4e97-8510-aed96766218d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370039095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.370039095
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1304980144
Short name T30
Test name
Test status
Simulation time 139724488 ps
CPU time 1.17 seconds
Started Jul 23 06:48:25 PM PDT 24
Finished Jul 23 06:48:36 PM PDT 24
Peak memory 198424 kb
Host smart-10237dad-4d7b-447e-91b7-7b0820ac356b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304980144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1304980144
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2046529524
Short name T117
Test name
Test status
Simulation time 11628440 ps
CPU time 0.6 seconds
Started Jul 23 06:02:02 PM PDT 24
Finished Jul 23 06:02:04 PM PDT 24
Peak memory 194440 kb
Host smart-d9d6ce54-d50c-4722-9e22-8f693315401b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046529524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2046529524
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2812847055
Short name T73
Test name
Test status
Simulation time 15567247 ps
CPU time 0.64 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:36 PM PDT 24
Peak memory 194824 kb
Host smart-fdfad1c5-7d4a-4ba4-9b27-ff0dfbc58b5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812847055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2812847055
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3581965781
Short name T83
Test name
Test status
Simulation time 171952950 ps
CPU time 0.94 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 198440 kb
Host smart-611b90df-32dd-4c4d-b793-32c4c2b2b275
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581965781 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3581965781
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1689425885
Short name T37
Test name
Test status
Simulation time 299957385 ps
CPU time 1.42 seconds
Started Jul 23 06:48:31 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 198392 kb
Host smart-0d183075-7a57-4f75-93d3-f55c655a329d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689425885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1689425885
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.497450347
Short name T728
Test name
Test status
Simulation time 296995138 ps
CPU time 0.73 seconds
Started Jul 23 06:48:30 PM PDT 24
Finished Jul 23 06:48:40 PM PDT 24
Peak memory 195728 kb
Host smart-84dd4550-aa50-4907-afe0-4dde1bd595d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497450347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.497450347
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2611772480
Short name T775
Test name
Test status
Simulation time 363284592 ps
CPU time 1.45 seconds
Started Jul 23 06:48:31 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 197052 kb
Host smart-d37b1a85-b4f4-4c32-91ca-6008f1beba67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611772480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2611772480
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3427742843
Short name T74
Test name
Test status
Simulation time 16935761 ps
CPU time 0.63 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 195476 kb
Host smart-7b4383b9-a251-4d9c-8b3c-3a9d12d6afa9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427742843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3427742843
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2010611078
Short name T740
Test name
Test status
Simulation time 119923676 ps
CPU time 1.5 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:34 PM PDT 24
Peak memory 198416 kb
Host smart-8a91b277-70fa-47be-baa6-77748aa6486c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010611078 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2010611078
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.622152436
Short name T795
Test name
Test status
Simulation time 44474419 ps
CPU time 0.62 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:29 PM PDT 24
Peak memory 195124 kb
Host smart-92b4e847-1b09-4b0c-a08c-f312e334fcad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622152436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.622152436
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3282528091
Short name T715
Test name
Test status
Simulation time 47827726 ps
CPU time 0.62 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:37 PM PDT 24
Peak memory 194848 kb
Host smart-d6a41b3c-6d1d-4ec2-b753-8c2153c08381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282528091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3282528091
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1247345413
Short name T813
Test name
Test status
Simulation time 16733891 ps
CPU time 0.75 seconds
Started Jul 23 06:48:25 PM PDT 24
Finished Jul 23 06:48:35 PM PDT 24
Peak memory 197228 kb
Host smart-3c98bbde-41d3-455c-a9f5-7c25187c8884
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247345413 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1247345413
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.513838227
Short name T802
Test name
Test status
Simulation time 530507632 ps
CPU time 2.87 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:35 PM PDT 24
Peak memory 198584 kb
Host smart-077a8a88-063c-4d06-90d2-559a78a09ade
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513838227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.513838227
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2304750247
Short name T97
Test name
Test status
Simulation time 1042590906 ps
CPU time 3.24 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:36 PM PDT 24
Peak memory 197480 kb
Host smart-0f70b5bc-ff66-4093-9ae9-47f5f5cf95d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304750247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2304750247
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2053675696
Short name T836
Test name
Test status
Simulation time 31291123 ps
CPU time 0.69 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 195632 kb
Host smart-2eec6a00-7396-4b36-b036-4b4f58c663c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053675696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2053675696
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2868755072
Short name T729
Test name
Test status
Simulation time 28371744 ps
CPU time 0.81 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:34 PM PDT 24
Peak memory 198280 kb
Host smart-1f754921-e713-47d6-84b1-acb3a424309c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868755072 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2868755072
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.4275274939
Short name T811
Test name
Test status
Simulation time 119779293 ps
CPU time 0.6 seconds
Started Jul 23 06:48:31 PM PDT 24
Finished Jul 23 06:48:40 PM PDT 24
Peak memory 194688 kb
Host smart-e17d5db3-a735-46fc-89a3-bab01d3238e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275274939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.4275274939
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2351851956
Short name T780
Test name
Test status
Simulation time 27481342 ps
CPU time 0.77 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 196688 kb
Host smart-c9a9458a-f89c-4c14-a0a0-15ee334efa95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351851956 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2351851956
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.528397878
Short name T829
Test name
Test status
Simulation time 94127901 ps
CPU time 2.72 seconds
Started Jul 23 06:48:22 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 198392 kb
Host smart-80f64770-ca8f-4627-a3c2-2882659771ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528397878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.528397878
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.275483474
Short name T38
Test name
Test status
Simulation time 83681049 ps
CPU time 1.18 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:35 PM PDT 24
Peak memory 198392 kb
Host smart-23ed9d20-b01a-490c-9b4d-974b96f80eed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275483474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.275483474
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.109481798
Short name T803
Test name
Test status
Simulation time 229169331 ps
CPU time 0.99 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 198288 kb
Host smart-32acf290-31d7-4f2e-834b-fa7b95288cc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109481798 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.109481798
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.108216122
Short name T742
Test name
Test status
Simulation time 58245812 ps
CPU time 0.57 seconds
Started Jul 23 06:48:50 PM PDT 24
Finished Jul 23 06:48:56 PM PDT 24
Peak memory 193652 kb
Host smart-0aa3f07f-b43e-41c3-bb6f-3119d53fb103
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108216122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.108216122
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3097069230
Short name T747
Test name
Test status
Simulation time 55944326 ps
CPU time 0.64 seconds
Started Jul 23 06:48:42 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 194728 kb
Host smart-ec8f272c-6181-48b6-8908-ceb38cd12bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097069230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3097069230
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.448303166
Short name T762
Test name
Test status
Simulation time 93988559 ps
CPU time 1.34 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 197972 kb
Host smart-746f8ca1-ce76-489d-88b2-fcd2f8c95657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448303166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.448303166
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1268590941
Short name T39
Test name
Test status
Simulation time 51076415 ps
CPU time 0.91 seconds
Started Jul 23 06:48:38 PM PDT 24
Finished Jul 23 06:48:46 PM PDT 24
Peak memory 198188 kb
Host smart-f79fa54d-37ac-4b01-be07-97d5023a6b53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268590941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1268590941
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2936871285
Short name T723
Test name
Test status
Simulation time 54163886 ps
CPU time 0.85 seconds
Started Jul 23 06:48:40 PM PDT 24
Finished Jul 23 06:48:47 PM PDT 24
Peak memory 198276 kb
Host smart-0d93a6c1-ee39-400d-9912-2eef7f47d303
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936871285 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2936871285
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2765063240
Short name T70
Test name
Test status
Simulation time 14147597 ps
CPU time 0.61 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:50 PM PDT 24
Peak memory 194820 kb
Host smart-db0dc4a8-f4eb-4ab7-972a-4116342eff92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765063240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2765063240
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.4049902765
Short name T733
Test name
Test status
Simulation time 69028025 ps
CPU time 0.63 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 194168 kb
Host smart-0a5aae95-d546-43d2-959c-def2e607b5c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049902765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.4049902765
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1735591514
Short name T798
Test name
Test status
Simulation time 39567335 ps
CPU time 0.82 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 196764 kb
Host smart-8925a3d9-69da-4120-80cf-11c2e58b4372
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735591514 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1735591514
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3290207897
Short name T821
Test name
Test status
Simulation time 181221256 ps
CPU time 1.25 seconds
Started Jul 23 06:48:43 PM PDT 24
Finished Jul 23 06:48:49 PM PDT 24
Peak memory 198344 kb
Host smart-a5ccce12-970a-4385-bd5f-6d8ee19c054f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290207897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3290207897
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2171305089
Short name T778
Test name
Test status
Simulation time 174409233 ps
CPU time 0.84 seconds
Started Jul 23 06:48:35 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 197312 kb
Host smart-7ad3cb36-1a28-4900-aa5a-d8a540a0dcfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171305089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2171305089
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3104500167
Short name T741
Test name
Test status
Simulation time 151229565 ps
CPU time 0.73 seconds
Started Jul 23 06:48:44 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 198268 kb
Host smart-f17220a5-1907-4bc8-9b25-e4ea6886e28c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104500167 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3104500167
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1344790762
Short name T71
Test name
Test status
Simulation time 16516894 ps
CPU time 0.62 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:54 PM PDT 24
Peak memory 194948 kb
Host smart-e3b0c533-ea7a-46ac-91a8-38d9d2a07dc6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344790762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1344790762
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1863367350
Short name T781
Test name
Test status
Simulation time 41057551 ps
CPU time 0.58 seconds
Started Jul 23 06:48:38 PM PDT 24
Finished Jul 23 06:48:45 PM PDT 24
Peak memory 194052 kb
Host smart-20119407-362b-4dec-81ca-85d673068656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863367350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1863367350
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2543774465
Short name T77
Test name
Test status
Simulation time 31170770 ps
CPU time 0.77 seconds
Started Jul 23 06:48:51 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 196580 kb
Host smart-e8678154-50e9-4142-984e-3cf37ce1cd35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543774465 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2543774465
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2904854257
Short name T753
Test name
Test status
Simulation time 276906355 ps
CPU time 1.95 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 198384 kb
Host smart-f11c3311-a373-4ee5-a879-ad6c0911ab28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904854257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2904854257
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2539246841
Short name T819
Test name
Test status
Simulation time 191795133 ps
CPU time 1.42 seconds
Started Jul 23 06:48:50 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 198420 kb
Host smart-50152402-c287-4e7b-b210-28a3b24319de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539246841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2539246841
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3967914515
Short name T734
Test name
Test status
Simulation time 65370286 ps
CPU time 0.88 seconds
Started Jul 23 06:48:53 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 198268 kb
Host smart-37925fe2-da58-4f6a-ac4a-4019046f4135
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967914515 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3967914515
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2842858610
Short name T72
Test name
Test status
Simulation time 13230579 ps
CPU time 0.64 seconds
Started Jul 23 06:48:55 PM PDT 24
Finished Jul 23 06:48:59 PM PDT 24
Peak memory 194924 kb
Host smart-d10ad82f-0e88-43d7-a4e8-179f7d7f0174
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842858610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2842858610
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1269737525
Short name T783
Test name
Test status
Simulation time 71812303 ps
CPU time 0.62 seconds
Started Jul 23 06:48:51 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 193956 kb
Host smart-e13d2cbd-4296-4b28-9e4e-79a1d6b706b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269737525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1269737525
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3894979475
Short name T81
Test name
Test status
Simulation time 34329353 ps
CPU time 0.74 seconds
Started Jul 23 06:48:44 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 195084 kb
Host smart-34a8d35d-ba07-4fe7-afba-2ce0e6af6dc9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894979475 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3894979475
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.4217396769
Short name T800
Test name
Test status
Simulation time 76925715 ps
CPU time 2 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 198388 kb
Host smart-f762b8b9-8609-4563-bc2d-f2898781afed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217396769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.4217396769
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3059197770
Short name T40
Test name
Test status
Simulation time 847270541 ps
CPU time 1.2 seconds
Started Jul 23 06:48:42 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 198352 kb
Host smart-577b79e7-aa43-4199-b1c9-22a9d32e7346
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059197770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3059197770
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2689972562
Short name T832
Test name
Test status
Simulation time 91693606 ps
CPU time 0.75 seconds
Started Jul 23 06:48:38 PM PDT 24
Finished Jul 23 06:48:46 PM PDT 24
Peak memory 198196 kb
Host smart-24da3afa-ed99-4ad5-b9ca-93f2351cbb8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689972562 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2689972562
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.808249746
Short name T831
Test name
Test status
Simulation time 27766160 ps
CPU time 0.6 seconds
Started Jul 23 06:48:37 PM PDT 24
Finished Jul 23 06:48:45 PM PDT 24
Peak memory 194760 kb
Host smart-4342be51-cc91-4e11-a446-4b89043f00da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808249746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.808249746
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2453649547
Short name T833
Test name
Test status
Simulation time 15447962 ps
CPU time 0.59 seconds
Started Jul 23 06:48:53 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 194028 kb
Host smart-1d6e8afa-a47c-4034-9400-0908eb855bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453649547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2453649547
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.339062059
Short name T67
Test name
Test status
Simulation time 58436502 ps
CPU time 0.91 seconds
Started Jul 23 06:48:42 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 196784 kb
Host smart-77a95a87-35b3-4912-860d-869f7fa1fe6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339062059 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.339062059
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2385732687
Short name T750
Test name
Test status
Simulation time 87561115 ps
CPU time 1.16 seconds
Started Jul 23 06:48:38 PM PDT 24
Finished Jul 23 06:48:46 PM PDT 24
Peak memory 198384 kb
Host smart-f7fe625f-f5ef-4e4f-9e8f-d15ce39276ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385732687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2385732687
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1756073734
Short name T837
Test name
Test status
Simulation time 133087443 ps
CPU time 1.49 seconds
Started Jul 23 06:48:49 PM PDT 24
Finished Jul 23 06:48:55 PM PDT 24
Peak memory 198232 kb
Host smart-7138b27a-45b7-4856-93aa-fc9f47cb7052
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756073734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1756073734
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.669047053
Short name T787
Test name
Test status
Simulation time 41609490 ps
CPU time 1.08 seconds
Started Jul 23 06:48:45 PM PDT 24
Finished Jul 23 06:48:49 PM PDT 24
Peak memory 198284 kb
Host smart-aec2a796-c33b-41e6-b762-aacb2242895b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669047053 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.669047053
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1933097180
Short name T65
Test name
Test status
Simulation time 13397051 ps
CPU time 0.63 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 195328 kb
Host smart-dc8c9d0b-a798-48dd-8e23-f5e25eba4fa1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933097180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1933097180
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.211164326
Short name T727
Test name
Test status
Simulation time 15747043 ps
CPU time 0.63 seconds
Started Jul 23 06:48:38 PM PDT 24
Finished Jul 23 06:48:45 PM PDT 24
Peak memory 194156 kb
Host smart-d8939392-a8c2-44c3-8ec9-3b0b6ed278ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211164326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.211164326
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1337952730
Short name T80
Test name
Test status
Simulation time 16362909 ps
CPU time 0.7 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:54 PM PDT 24
Peak memory 195136 kb
Host smart-9ce3d5e8-59f9-4e54-9f62-752e4d2a26d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337952730 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1337952730
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.453415875
Short name T736
Test name
Test status
Simulation time 22355968 ps
CPU time 1.11 seconds
Started Jul 23 06:48:44 PM PDT 24
Finished Jul 23 06:48:49 PM PDT 24
Peak memory 198348 kb
Host smart-44c7f7a8-5457-407d-9e23-a01ebf525c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453415875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.453415875
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.614900182
Short name T31
Test name
Test status
Simulation time 89466329 ps
CPU time 1.19 seconds
Started Jul 23 06:48:42 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 198348 kb
Host smart-eb6b780c-f791-44f4-9c1d-7bb06da9cccd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614900182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.614900182
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1001015723
Short name T791
Test name
Test status
Simulation time 39342128 ps
CPU time 0.98 seconds
Started Jul 23 06:48:55 PM PDT 24
Finished Jul 23 06:48:59 PM PDT 24
Peak memory 198264 kb
Host smart-c323ef6e-9950-44f4-af3a-3f7405bfe10c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001015723 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1001015723
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1093924840
Short name T808
Test name
Test status
Simulation time 65871073 ps
CPU time 0.6 seconds
Started Jul 23 06:48:53 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 194948 kb
Host smart-3ac60d26-2574-4634-aaa0-45226242eb6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093924840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1093924840
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1261682243
Short name T766
Test name
Test status
Simulation time 18011234 ps
CPU time 0.6 seconds
Started Jul 23 06:48:41 PM PDT 24
Finished Jul 23 06:48:47 PM PDT 24
Peak memory 194160 kb
Host smart-d572d794-03f7-4336-a6bb-43a918ba8cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261682243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1261682243
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2510773437
Short name T792
Test name
Test status
Simulation time 18756855 ps
CPU time 0.75 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 196960 kb
Host smart-2ab46626-880c-4542-aa7b-5081bcc7d439
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510773437 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2510773437
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2926653914
Short name T755
Test name
Test status
Simulation time 21680120 ps
CPU time 1.13 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:50 PM PDT 24
Peak memory 198404 kb
Host smart-dde493d1-e74d-4a83-a1c7-7ca0f4651f61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926653914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2926653914
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.544863119
Short name T774
Test name
Test status
Simulation time 164090136 ps
CPU time 1.15 seconds
Started Jul 23 06:48:52 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 198372 kb
Host smart-49ebed24-7b37-4803-ac53-848999706b00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544863119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.544863119
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2262239228
Short name T824
Test name
Test status
Simulation time 51213285 ps
CPU time 0.88 seconds
Started Jul 23 06:48:36 PM PDT 24
Finished Jul 23 06:48:44 PM PDT 24
Peak memory 198272 kb
Host smart-99274564-8acb-4c01-9a65-9091dcb02d6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262239228 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2262239228
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.710845889
Short name T746
Test name
Test status
Simulation time 15148491 ps
CPU time 0.62 seconds
Started Jul 23 06:48:52 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 195184 kb
Host smart-ddf1df75-df97-47d3-9605-cce2440f912f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710845889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.710845889
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3950419363
Short name T714
Test name
Test status
Simulation time 50422186 ps
CPU time 0.66 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 194108 kb
Host smart-6bb6fafb-a844-45dc-94bb-4840cfdaadf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950419363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3950419363
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1491857985
Short name T85
Test name
Test status
Simulation time 36997078 ps
CPU time 0.89 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:50 PM PDT 24
Peak memory 198228 kb
Host smart-030ade98-653a-4579-879d-570afa651a96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491857985 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1491857985
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2486465057
Short name T779
Test name
Test status
Simulation time 329997894 ps
CPU time 2.83 seconds
Started Jul 23 06:48:49 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 198356 kb
Host smart-bf1a5d68-ad3c-43b8-844e-74cecd902433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486465057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2486465057
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1819321015
Short name T809
Test name
Test status
Simulation time 181244292 ps
CPU time 0.93 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 198216 kb
Host smart-ddff036a-bc2f-47b0-8e74-3655da0f6fcd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819321015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1819321015
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3171793042
Short name T788
Test name
Test status
Simulation time 29943683 ps
CPU time 1.41 seconds
Started Jul 23 06:48:41 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 198444 kb
Host smart-7d9a6200-d0e4-4226-b8fc-03bd3ca83feb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171793042 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3171793042
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3507377
Short name T721
Test name
Test status
Simulation time 149784696 ps
CPU time 0.64 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 195240 kb
Host smart-ba5b169c-f85f-4019-b073-7ac82037078d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ
=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_c
sr_rw.3507377
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3614635686
Short name T763
Test name
Test status
Simulation time 16151177 ps
CPU time 0.58 seconds
Started Jul 23 06:48:52 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 194088 kb
Host smart-31831a39-2738-4bd5-8828-437dd3718252
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614635686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3614635686
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3268334211
Short name T815
Test name
Test status
Simulation time 39278530 ps
CPU time 0.85 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 196772 kb
Host smart-a6ba9c69-f9c4-4a93-84a5-07fc63b52e2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268334211 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3268334211
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3087556273
Short name T726
Test name
Test status
Simulation time 523772407 ps
CPU time 1.88 seconds
Started Jul 23 06:48:51 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 198392 kb
Host smart-082bb0bd-40d3-40cc-a5ac-523673d5e6c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087556273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3087556273
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2555834076
Short name T793
Test name
Test status
Simulation time 69715504 ps
CPU time 1.15 seconds
Started Jul 23 06:49:02 PM PDT 24
Finished Jul 23 06:49:04 PM PDT 24
Peak memory 198380 kb
Host smart-1aae418e-3fcd-4ee9-80e5-f644ba211b75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555834076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2555834076
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2338894047
Short name T816
Test name
Test status
Simulation time 36541441 ps
CPU time 1.48 seconds
Started Jul 23 06:48:57 PM PDT 24
Finished Jul 23 06:49:01 PM PDT 24
Peak memory 198444 kb
Host smart-3f6aadce-8865-433d-ba56-ad5cc78c6f34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338894047 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2338894047
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3272487993
Short name T822
Test name
Test status
Simulation time 43926249 ps
CPU time 0.64 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 195316 kb
Host smart-6e8a7e35-99a2-4409-94ee-685edd6775f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272487993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3272487993
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3140488831
Short name T786
Test name
Test status
Simulation time 58523790 ps
CPU time 0.64 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:52 PM PDT 24
Peak memory 194152 kb
Host smart-484a63ea-da85-4eaa-a973-8a306ecc647f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140488831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3140488831
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3552530658
Short name T78
Test name
Test status
Simulation time 375250472 ps
CPU time 0.77 seconds
Started Jul 23 06:48:52 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 197192 kb
Host smart-0c1c99e2-7499-47e0-ad2c-84ca8772fb26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552530658 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3552530658
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3248429350
Short name T826
Test name
Test status
Simulation time 30337673 ps
CPU time 1.63 seconds
Started Jul 23 06:48:58 PM PDT 24
Finished Jul 23 06:49:02 PM PDT 24
Peak memory 198384 kb
Host smart-41bd6473-f733-4a5b-b246-46acc007c79a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248429350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3248429350
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1396576443
Short name T794
Test name
Test status
Simulation time 191971036 ps
CPU time 0.87 seconds
Started Jul 23 06:48:46 PM PDT 24
Finished Jul 23 06:48:50 PM PDT 24
Peak memory 197440 kb
Host smart-928a7952-bd60-4379-9066-e253422f16dc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396576443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1396576443
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.306748886
Short name T797
Test name
Test status
Simulation time 36134711 ps
CPU time 0.85 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:37 PM PDT 24
Peak memory 196832 kb
Host smart-19f7b998-e140-437f-8a39-159d29cce729
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306748886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.306748886
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.873304755
Short name T63
Test name
Test status
Simulation time 1310606634 ps
CPU time 3.53 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:39 PM PDT 24
Peak memory 198364 kb
Host smart-ac48a30e-8da2-4c7e-8ec0-ea7d04510bc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873304755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.873304755
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1619109366
Short name T760
Test name
Test status
Simulation time 20806341 ps
CPU time 0.64 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 195276 kb
Host smart-0f4a2f7f-311d-4e65-8549-7829f84f5c99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619109366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1619109366
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.3227630913
Short name T732
Test name
Test status
Simulation time 22016879 ps
CPU time 0.98 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:37 PM PDT 24
Peak memory 198320 kb
Host smart-080a856a-e102-4987-90d0-07844e95b433
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227630913 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.3227630913
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.219005120
Short name T761
Test name
Test status
Simulation time 22502726 ps
CPU time 0.6 seconds
Started Jul 23 06:48:25 PM PDT 24
Finished Jul 23 06:48:35 PM PDT 24
Peak memory 195732 kb
Host smart-18b202ec-79a4-4ed9-abf6-3bcd1e3c82da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219005120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.219005120
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2179299502
Short name T719
Test name
Test status
Simulation time 16152307 ps
CPU time 0.6 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:37 PM PDT 24
Peak memory 194128 kb
Host smart-e3f82558-a994-4337-b387-dbbe28660b6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179299502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2179299502
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2554591769
Short name T757
Test name
Test status
Simulation time 34396163 ps
CPU time 0.78 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 196656 kb
Host smart-ccb93c85-79c8-458a-b783-6fa374aee982
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554591769 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2554591769
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3225488425
Short name T716
Test name
Test status
Simulation time 38710429 ps
CPU time 2.02 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:35 PM PDT 24
Peak memory 198452 kb
Host smart-9b10ec4d-87f5-4443-971c-51909c62f4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225488425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3225488425
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.4138677266
Short name T825
Test name
Test status
Simulation time 301315661 ps
CPU time 1.14 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:34 PM PDT 24
Peak memory 198436 kb
Host smart-e1bb835b-641e-4ccf-b668-3fb46959bd75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138677266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.4138677266
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1810275760
Short name T759
Test name
Test status
Simulation time 83240645 ps
CPU time 0.62 seconds
Started Jul 23 06:48:54 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 194656 kb
Host smart-ab31ad6e-9d5f-4223-a51a-0e17a57bd633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810275760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1810275760
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2934830186
Short name T834
Test name
Test status
Simulation time 19953342 ps
CPU time 0.68 seconds
Started Jul 23 06:48:49 PM PDT 24
Finished Jul 23 06:48:55 PM PDT 24
Peak memory 194188 kb
Host smart-05d089bc-ceac-4e1a-b8a7-74c96fc8707f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934830186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2934830186
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.3219707130
Short name T799
Test name
Test status
Simulation time 40067713 ps
CPU time 0.59 seconds
Started Jul 23 06:48:58 PM PDT 24
Finished Jul 23 06:49:01 PM PDT 24
Peak memory 194668 kb
Host smart-2a7c05de-5c37-42f7-89ea-12f7e4e5eab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219707130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.3219707130
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2637238461
Short name T756
Test name
Test status
Simulation time 24669697 ps
CPU time 0.64 seconds
Started Jul 23 06:48:53 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 194096 kb
Host smart-74f13ff2-e418-4a9d-8c48-7fe75cabb4f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637238461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2637238461
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2632043651
Short name T735
Test name
Test status
Simulation time 44088078 ps
CPU time 0.59 seconds
Started Jul 23 06:48:51 PM PDT 24
Finished Jul 23 06:48:56 PM PDT 24
Peak memory 194076 kb
Host smart-a7e6799a-31a4-4cdd-973f-689fec3992b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632043651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2632043651
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3265708759
Short name T713
Test name
Test status
Simulation time 38482203 ps
CPU time 0.59 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 194068 kb
Host smart-3b4fa255-5f7a-4f79-9aa2-0fc4076b8063
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265708759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3265708759
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3157451673
Short name T748
Test name
Test status
Simulation time 22235020 ps
CPU time 0.59 seconds
Started Jul 23 06:48:50 PM PDT 24
Finished Jul 23 06:48:56 PM PDT 24
Peak memory 193980 kb
Host smart-c2d20469-07c2-4304-a525-137ba62d562a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157451673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3157451673
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.221540922
Short name T784
Test name
Test status
Simulation time 12780639 ps
CPU time 0.59 seconds
Started Jul 23 06:48:57 PM PDT 24
Finished Jul 23 06:49:00 PM PDT 24
Peak memory 194052 kb
Host smart-df25ac39-d8b2-441d-b641-1b0173475997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221540922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.221540922
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1975465784
Short name T724
Test name
Test status
Simulation time 16489147 ps
CPU time 0.64 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:52 PM PDT 24
Peak memory 194164 kb
Host smart-bae850be-14f1-465d-a853-664d1e89cf0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975465784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1975465784
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.4266778353
Short name T772
Test name
Test status
Simulation time 20642037 ps
CPU time 0.59 seconds
Started Jul 23 06:48:54 PM PDT 24
Finished Jul 23 06:48:59 PM PDT 24
Peak memory 194020 kb
Host smart-2eadef42-200c-4e2a-8601-55ce9d1beb87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266778353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.4266778353
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.369147920
Short name T752
Test name
Test status
Simulation time 115587649 ps
CPU time 0.87 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 196400 kb
Host smart-9e89036d-a329-49eb-8dea-defd8d0909c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369147920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.369147920
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2122195043
Short name T68
Test name
Test status
Simulation time 343001171 ps
CPU time 2.99 seconds
Started Jul 23 06:48:30 PM PDT 24
Finished Jul 23 06:48:42 PM PDT 24
Peak memory 198384 kb
Host smart-6ce1e11e-3cb0-4086-8e10-fb1a1d9d1541
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122195043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2122195043
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1495288398
Short name T725
Test name
Test status
Simulation time 26958756 ps
CPU time 0.64 seconds
Started Jul 23 06:48:23 PM PDT 24
Finished Jul 23 06:48:32 PM PDT 24
Peak memory 195264 kb
Host smart-3b7618c3-caab-4f04-a473-71217995c357
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495288398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1495288398
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1062314094
Short name T771
Test name
Test status
Simulation time 61779540 ps
CPU time 0.67 seconds
Started Jul 23 06:48:37 PM PDT 24
Finished Jul 23 06:48:44 PM PDT 24
Peak memory 197672 kb
Host smart-b209c34b-f907-4154-a7e7-7c0715e71344
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062314094 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1062314094
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2242740421
Short name T66
Test name
Test status
Simulation time 20150298 ps
CPU time 0.61 seconds
Started Jul 23 06:48:25 PM PDT 24
Finished Jul 23 06:48:35 PM PDT 24
Peak memory 195420 kb
Host smart-16cb96cd-c16d-49e1-bf0e-41846dd6ab1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242740421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2242740421
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.4157495877
Short name T789
Test name
Test status
Simulation time 18726005 ps
CPU time 0.6 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:33 PM PDT 24
Peak memory 194184 kb
Host smart-de08c6f0-2468-4140-bb6f-702760ae1494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157495877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.4157495877
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.391602095
Short name T84
Test name
Test status
Simulation time 32748422 ps
CPU time 0.87 seconds
Started Jul 23 06:48:26 PM PDT 24
Finished Jul 23 06:48:37 PM PDT 24
Peak memory 196748 kb
Host smart-72887a88-c269-4d48-9bf7-1f6b34db4d86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391602095 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.391602095
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3852558781
Short name T823
Test name
Test status
Simulation time 385109053 ps
CPU time 2.36 seconds
Started Jul 23 06:48:24 PM PDT 24
Finished Jul 23 06:48:36 PM PDT 24
Peak memory 198344 kb
Host smart-cb41ce7c-6580-4b7d-8a7f-f555ef0c4601
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852558781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3852558781
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1142047107
Short name T804
Test name
Test status
Simulation time 12267107 ps
CPU time 0.6 seconds
Started Jul 23 06:48:57 PM PDT 24
Finished Jul 23 06:49:01 PM PDT 24
Peak memory 194260 kb
Host smart-83c61da7-0fcd-490c-a52f-124ff3771b7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142047107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1142047107
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3792849111
Short name T739
Test name
Test status
Simulation time 64101069 ps
CPU time 0.64 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:52 PM PDT 24
Peak memory 194116 kb
Host smart-3402864d-2a31-4c21-882f-7b7672597a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792849111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3792849111
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1582585756
Short name T776
Test name
Test status
Simulation time 27423081 ps
CPU time 0.64 seconds
Started Jul 23 06:48:49 PM PDT 24
Finished Jul 23 06:48:54 PM PDT 24
Peak memory 194748 kb
Host smart-b17985be-62f6-4538-b71c-be6d8645bc6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582585756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1582585756
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3347278599
Short name T767
Test name
Test status
Simulation time 52031120 ps
CPU time 0.61 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 194132 kb
Host smart-36e4c5d8-8198-46a6-836d-fc679b5b6220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347278599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3347278599
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.492548797
Short name T818
Test name
Test status
Simulation time 19748032 ps
CPU time 0.59 seconds
Started Jul 23 06:48:57 PM PDT 24
Finished Jul 23 06:49:01 PM PDT 24
Peak memory 194088 kb
Host smart-d3e1bf85-0616-4927-8e5c-188c148ae857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492548797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.492548797
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1641659221
Short name T777
Test name
Test status
Simulation time 15131449 ps
CPU time 0.61 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:52 PM PDT 24
Peak memory 194076 kb
Host smart-53d4cc27-0280-4b6c-9264-808d8a8563da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641659221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1641659221
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1870961133
Short name T731
Test name
Test status
Simulation time 13186384 ps
CPU time 0.6 seconds
Started Jul 23 06:49:08 PM PDT 24
Finished Jul 23 06:49:10 PM PDT 24
Peak memory 194720 kb
Host smart-ca50ecb4-9968-495d-a204-790147ceb5ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870961133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1870961133
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1704214978
Short name T770
Test name
Test status
Simulation time 14061022 ps
CPU time 0.6 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 194044 kb
Host smart-1e1522a2-f913-4aac-839b-190a7f7d168b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704214978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1704214978
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.4081188318
Short name T720
Test name
Test status
Simulation time 14902958 ps
CPU time 0.6 seconds
Started Jul 23 06:48:53 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 194072 kb
Host smart-36338fd9-8977-46c1-921e-a6bf89b73a09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081188318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.4081188318
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1085633650
Short name T743
Test name
Test status
Simulation time 48515773 ps
CPU time 0.61 seconds
Started Jul 23 06:48:56 PM PDT 24
Finished Jul 23 06:49:00 PM PDT 24
Peak memory 194144 kb
Host smart-e8123d57-3175-4c5d-a50c-f495fe064871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085633650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1085633650
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3023354973
Short name T76
Test name
Test status
Simulation time 22048928 ps
CPU time 0.71 seconds
Started Jul 23 06:48:37 PM PDT 24
Finished Jul 23 06:48:45 PM PDT 24
Peak memory 195036 kb
Host smart-72373a3d-c93f-425b-9cbe-c750f241e157
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023354973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3023354973
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1283437931
Short name T75
Test name
Test status
Simulation time 766457382 ps
CPU time 3.37 seconds
Started Jul 23 06:48:32 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 197248 kb
Host smart-b122079a-b2db-40c9-b120-29c59a9317eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283437931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1283437931
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2218211278
Short name T722
Test name
Test status
Simulation time 30889305 ps
CPU time 0.58 seconds
Started Jul 23 06:48:30 PM PDT 24
Finished Jul 23 06:48:40 PM PDT 24
Peak memory 194552 kb
Host smart-891a3564-31c0-47c8-ad88-bdaeefe8c915
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218211278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2218211278
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3146958932
Short name T745
Test name
Test status
Simulation time 33892636 ps
CPU time 0.88 seconds
Started Jul 23 06:48:31 PM PDT 24
Finished Jul 23 06:48:40 PM PDT 24
Peak memory 198248 kb
Host smart-8e5fbf42-6e17-4304-816a-a24d8a3a090f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146958932 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3146958932
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1545681531
Short name T830
Test name
Test status
Simulation time 38942549 ps
CPU time 0.57 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 194356 kb
Host smart-945f15a5-f415-48b2-bf37-737f06529d31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545681531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1545681531
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1247034339
Short name T754
Test name
Test status
Simulation time 17229009 ps
CPU time 0.63 seconds
Started Jul 23 06:48:54 PM PDT 24
Finished Jul 23 06:48:59 PM PDT 24
Peak memory 194208 kb
Host smart-59726c30-333c-42f8-93f8-747d13c446ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247034339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1247034339
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2964255216
Short name T817
Test name
Test status
Simulation time 55848948 ps
CPU time 0.82 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 196632 kb
Host smart-f314d7c7-9e3e-4cfe-8e47-bb07da76e455
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964255216 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2964255216
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1712683834
Short name T744
Test name
Test status
Simulation time 19528373 ps
CPU time 1.07 seconds
Started Jul 23 06:48:34 PM PDT 24
Finished Jul 23 06:48:42 PM PDT 24
Peak memory 198220 kb
Host smart-68a8a340-74ad-46c5-bf49-beaeea9e1acb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712683834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1712683834
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.4284900847
Short name T801
Test name
Test status
Simulation time 161247335 ps
CPU time 0.87 seconds
Started Jul 23 06:48:30 PM PDT 24
Finished Jul 23 06:48:40 PM PDT 24
Peak memory 198132 kb
Host smart-56f1946a-a5a7-497a-abf0-83c24c3e505e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284900847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.4284900847
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2958018094
Short name T738
Test name
Test status
Simulation time 23194803 ps
CPU time 0.62 seconds
Started Jul 23 06:48:47 PM PDT 24
Finished Jul 23 06:48:52 PM PDT 24
Peak memory 194184 kb
Host smart-a8c3d01f-e28d-45d1-bf1d-6ca95dce5717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958018094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2958018094
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.978836010
Short name T737
Test name
Test status
Simulation time 35334019 ps
CPU time 0.64 seconds
Started Jul 23 06:48:58 PM PDT 24
Finished Jul 23 06:49:01 PM PDT 24
Peak memory 194780 kb
Host smart-0edf52b1-eff8-4981-a720-aa7c91b80258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978836010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.978836010
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2356813986
Short name T718
Test name
Test status
Simulation time 14425147 ps
CPU time 0.63 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 194756 kb
Host smart-4cfda0a9-e1c1-4b3f-894a-0f2d35490295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356813986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2356813986
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4223892523
Short name T768
Test name
Test status
Simulation time 12660750 ps
CPU time 0.62 seconds
Started Jul 23 06:48:49 PM PDT 24
Finished Jul 23 06:48:54 PM PDT 24
Peak memory 194080 kb
Host smart-cf1c2644-884f-49d6-a1a0-2b0370e47677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223892523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4223892523
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.3764763030
Short name T842
Test name
Test status
Simulation time 40177364 ps
CPU time 0.6 seconds
Started Jul 23 06:48:51 PM PDT 24
Finished Jul 23 06:48:56 PM PDT 24
Peak memory 194736 kb
Host smart-e053f778-4527-40d3-8170-2f6c6807933c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764763030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.3764763030
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.577266418
Short name T841
Test name
Test status
Simulation time 50926654 ps
CPU time 0.62 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:54 PM PDT 24
Peak memory 194784 kb
Host smart-b72fe1e0-2744-42cc-92d0-9ac74d5b8801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577266418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.577266418
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.774861394
Short name T796
Test name
Test status
Simulation time 50549050 ps
CPU time 0.63 seconds
Started Jul 23 06:48:55 PM PDT 24
Finished Jul 23 06:49:00 PM PDT 24
Peak memory 194104 kb
Host smart-1fd665dc-cb7e-4959-935b-f1e8f971ca04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774861394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.774861394
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2990287821
Short name T782
Test name
Test status
Simulation time 22403968 ps
CPU time 0.62 seconds
Started Jul 23 06:49:00 PM PDT 24
Finished Jul 23 06:49:02 PM PDT 24
Peak memory 194060 kb
Host smart-5fcccd60-f80a-412f-ac6b-4c15b536dfdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990287821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2990287821
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.301765987
Short name T840
Test name
Test status
Simulation time 85164506 ps
CPU time 0.61 seconds
Started Jul 23 06:48:49 PM PDT 24
Finished Jul 23 06:48:55 PM PDT 24
Peak memory 194668 kb
Host smart-99000183-417d-41be-b01f-12265b0f5221
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301765987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.301765987
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3315421645
Short name T730
Test name
Test status
Simulation time 18843703 ps
CPU time 0.66 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:53 PM PDT 24
Peak memory 194160 kb
Host smart-3cae2315-3b8c-4c89-9d64-38ab92b6c046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315421645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3315421645
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.773045017
Short name T773
Test name
Test status
Simulation time 24863864 ps
CPU time 1.05 seconds
Started Jul 23 06:48:36 PM PDT 24
Finished Jul 23 06:48:44 PM PDT 24
Peak memory 198476 kb
Host smart-139a7bd2-b278-4a51-94d4-0bc6825a1064
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773045017 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.773045017
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2070827838
Short name T807
Test name
Test status
Simulation time 23921757 ps
CPU time 0.61 seconds
Started Jul 23 06:48:32 PM PDT 24
Finished Jul 23 06:48:44 PM PDT 24
Peak memory 194744 kb
Host smart-21a6e5c9-804b-446a-8460-1ce24da5f94b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070827838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2070827838
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.162923519
Short name T820
Test name
Test status
Simulation time 31831025 ps
CPU time 0.59 seconds
Started Jul 23 06:48:35 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 194144 kb
Host smart-fc5c9f07-cf0d-41b9-b16f-4b7fa9509660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162923519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.162923519
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3674024595
Short name T79
Test name
Test status
Simulation time 19131395 ps
CPU time 0.84 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:42 PM PDT 24
Peak memory 196800 kb
Host smart-3b9f9eee-1a4e-4814-a0ca-39b361b8b620
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674024595 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3674024595
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3969489348
Short name T827
Test name
Test status
Simulation time 388365099 ps
CPU time 1.84 seconds
Started Jul 23 06:48:48 PM PDT 24
Finished Jul 23 06:48:54 PM PDT 24
Peak memory 198392 kb
Host smart-fbbb79f0-f01b-4295-b19a-577826bc0ec9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969489348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3969489348
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.818683558
Short name T32
Test name
Test status
Simulation time 157892663 ps
CPU time 1.18 seconds
Started Jul 23 06:48:40 PM PDT 24
Finished Jul 23 06:48:47 PM PDT 24
Peak memory 198348 kb
Host smart-39318727-7a6c-438f-9f10-19e64f074af3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818683558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.818683558
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1556591543
Short name T758
Test name
Test status
Simulation time 288938019 ps
CPU time 1.61 seconds
Started Jul 23 06:48:51 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 198464 kb
Host smart-190c6567-8cec-4d74-88f9-9676562d3ebb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556591543 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1556591543
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2557366039
Short name T64
Test name
Test status
Simulation time 16921234 ps
CPU time 0.62 seconds
Started Jul 23 06:48:32 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 196296 kb
Host smart-019be6b6-3974-495e-bb23-c153c31b1702
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557366039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2557366039
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2107114399
Short name T812
Test name
Test status
Simulation time 53162800 ps
CPU time 0.56 seconds
Started Jul 23 06:48:35 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 194068 kb
Host smart-6647c43b-0fe5-4e50-827b-e43d666fbc5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107114399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2107114399
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3321502677
Short name T839
Test name
Test status
Simulation time 24474659 ps
CPU time 0.62 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 195036 kb
Host smart-1e79e297-5185-4d5c-8b95-49d6799cdff1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321502677 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3321502677
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2244506680
Short name T717
Test name
Test status
Simulation time 206200249 ps
CPU time 2.75 seconds
Started Jul 23 06:48:44 PM PDT 24
Finished Jul 23 06:48:51 PM PDT 24
Peak memory 198432 kb
Host smart-792d187c-cd0b-4e2c-86b5-e68bb2aef740
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244506680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2244506680
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2136768785
Short name T764
Test name
Test status
Simulation time 70465046 ps
CPU time 0.85 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:42 PM PDT 24
Peak memory 197992 kb
Host smart-da7469c1-c573-4f84-aa3a-94fe7b88fa94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136768785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2136768785
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.379072205
Short name T749
Test name
Test status
Simulation time 88071353 ps
CPU time 1.23 seconds
Started Jul 23 06:48:51 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 198388 kb
Host smart-786f69d0-a907-471d-8c5c-1f1ca7d7468a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379072205 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.379072205
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2030552312
Short name T790
Test name
Test status
Simulation time 20941022 ps
CPU time 0.6 seconds
Started Jul 23 06:48:42 PM PDT 24
Finished Jul 23 06:48:47 PM PDT 24
Peak memory 195116 kb
Host smart-ddbcf14d-8673-44cf-8fae-f6abd16e6dea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030552312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2030552312
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1963346582
Short name T835
Test name
Test status
Simulation time 13273236 ps
CPU time 0.58 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 194044 kb
Host smart-984b7c4d-cf36-4645-8989-e9df915d9b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963346582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1963346582
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.3895002772
Short name T828
Test name
Test status
Simulation time 30435904 ps
CPU time 0.92 seconds
Started Jul 23 06:48:32 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 196556 kb
Host smart-688006b6-f446-4369-be24-38cbf833a44c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895002772 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.3895002772
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2983784665
Short name T765
Test name
Test status
Simulation time 129266478 ps
CPU time 1.13 seconds
Started Jul 23 06:48:38 PM PDT 24
Finished Jul 23 06:48:46 PM PDT 24
Peak memory 198228 kb
Host smart-f1b1e8e8-8cb2-4401-8671-8473586be735
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983784665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2983784665
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4205303293
Short name T810
Test name
Test status
Simulation time 44679102 ps
CPU time 0.89 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:42 PM PDT 24
Peak memory 198052 kb
Host smart-62f5eda6-4988-4854-b7a4-02f8053da3c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205303293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4205303293
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3180508569
Short name T838
Test name
Test status
Simulation time 60636510 ps
CPU time 0.69 seconds
Started Jul 23 06:48:52 PM PDT 24
Finished Jul 23 06:48:57 PM PDT 24
Peak memory 197344 kb
Host smart-a5dc2905-7168-4144-a3c7-be9cf03ed649
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180508569 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3180508569
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1257658400
Short name T69
Test name
Test status
Simulation time 67295166 ps
CPU time 0.63 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 195300 kb
Host smart-0bbcbf36-7a32-46ed-8fee-ee6010434659
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257658400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1257658400
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.559166201
Short name T769
Test name
Test status
Simulation time 42482014 ps
CPU time 0.69 seconds
Started Jul 23 06:48:52 PM PDT 24
Finished Jul 23 06:48:58 PM PDT 24
Peak memory 194124 kb
Host smart-89ded3ac-5594-4f1f-84fc-5d99f4da0241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559166201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.559166201
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.253686795
Short name T82
Test name
Test status
Simulation time 114062356 ps
CPU time 0.86 seconds
Started Jul 23 06:48:34 PM PDT 24
Finished Jul 23 06:48:42 PM PDT 24
Peak memory 196608 kb
Host smart-be180151-c6b6-407a-a42e-29d75f492179
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253686795 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.253686795
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2265269719
Short name T805
Test name
Test status
Simulation time 168677270 ps
CPU time 1.94 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:43 PM PDT 24
Peak memory 198452 kb
Host smart-b2fb19ce-7086-4753-8cdd-504d0d550734
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265269719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2265269719
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2817544608
Short name T41
Test name
Test status
Simulation time 281942448 ps
CPU time 1.17 seconds
Started Jul 23 06:48:35 PM PDT 24
Finished Jul 23 06:48:44 PM PDT 24
Peak memory 198372 kb
Host smart-6242e9b8-4157-4bed-99b3-38279496c2f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817544608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2817544608
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1971371910
Short name T751
Test name
Test status
Simulation time 22416559 ps
CPU time 0.79 seconds
Started Jul 23 06:48:49 PM PDT 24
Finished Jul 23 06:48:55 PM PDT 24
Peak memory 198236 kb
Host smart-4a17bce9-4cca-4433-b1cc-3478bf70c7ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971371910 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1971371910
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.17891421
Short name T96
Test name
Test status
Simulation time 14656692 ps
CPU time 0.65 seconds
Started Jul 23 06:48:33 PM PDT 24
Finished Jul 23 06:48:41 PM PDT 24
Peak memory 195088 kb
Host smart-7c4d2846-6b19-4473-89a2-d7f03ff9c905
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17891421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_c
sr_rw.17891421
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3440117266
Short name T814
Test name
Test status
Simulation time 10941167 ps
CPU time 0.63 seconds
Started Jul 23 06:48:59 PM PDT 24
Finished Jul 23 06:49:02 PM PDT 24
Peak memory 194012 kb
Host smart-ee2af1ae-689f-423c-a465-90b002ce9223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440117266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3440117266
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2870347588
Short name T785
Test name
Test status
Simulation time 35972415 ps
CPU time 0.65 seconds
Started Jul 23 06:48:42 PM PDT 24
Finished Jul 23 06:48:48 PM PDT 24
Peak memory 195276 kb
Host smart-fd69f182-3db3-4789-a2b6-26f27bc1aba0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870347588 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2870347588
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3305842647
Short name T843
Test name
Test status
Simulation time 290815020 ps
CPU time 2.45 seconds
Started Jul 23 06:48:36 PM PDT 24
Finished Jul 23 06:48:46 PM PDT 24
Peak memory 198420 kb
Host smart-d9012fe1-a593-4502-b032-a568c5296f38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305842647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3305842647
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.252506004
Short name T806
Test name
Test status
Simulation time 277172611 ps
CPU time 1.12 seconds
Started Jul 23 06:48:37 PM PDT 24
Finished Jul 23 06:48:45 PM PDT 24
Peak memory 198428 kb
Host smart-898f4aaf-123b-420a-b82c-a5a07f256095
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252506004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.252506004
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3037796774
Short name T543
Test name
Test status
Simulation time 16409771 ps
CPU time 0.6 seconds
Started Jul 23 06:01:09 PM PDT 24
Finished Jul 23 06:01:10 PM PDT 24
Peak memory 194464 kb
Host smart-9a27af5b-fc9b-422d-8a30-58322439e4f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037796774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3037796774
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2035404545
Short name T349
Test name
Test status
Simulation time 81928770 ps
CPU time 0.91 seconds
Started Jul 23 06:01:15 PM PDT 24
Finished Jul 23 06:01:17 PM PDT 24
Peak memory 196508 kb
Host smart-3166eb91-3ee9-4c83-b188-a8b458cbc08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035404545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2035404545
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1026505875
Short name T547
Test name
Test status
Simulation time 457246301 ps
CPU time 12.52 seconds
Started Jul 23 06:01:12 PM PDT 24
Finished Jul 23 06:01:25 PM PDT 24
Peak memory 197380 kb
Host smart-61c46e5c-94de-483b-bf68-5f6750fc31af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026505875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1026505875
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3397473088
Short name T331
Test name
Test status
Simulation time 86851452 ps
CPU time 0.61 seconds
Started Jul 23 06:01:21 PM PDT 24
Finished Jul 23 06:01:28 PM PDT 24
Peak memory 194776 kb
Host smart-ee8bdbb4-72ec-45ac-bea6-cbc3b374819f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397473088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3397473088
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1471194558
Short name T417
Test name
Test status
Simulation time 43948824 ps
CPU time 0.83 seconds
Started Jul 23 06:01:09 PM PDT 24
Finished Jul 23 06:01:11 PM PDT 24
Peak memory 196060 kb
Host smart-1c118d7a-1289-4e22-a447-1cfdb3bd169b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471194558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1471194558
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3309653222
Short name T316
Test name
Test status
Simulation time 191945703 ps
CPU time 2.53 seconds
Started Jul 23 06:01:09 PM PDT 24
Finished Jul 23 06:01:12 PM PDT 24
Peak memory 197024 kb
Host smart-3ac31fe1-b5a6-4cca-9b55-6371ddb12bcd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309653222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3309653222
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1610738183
Short name T511
Test name
Test status
Simulation time 116185141 ps
CPU time 1.93 seconds
Started Jul 23 06:01:15 PM PDT 24
Finished Jul 23 06:01:17 PM PDT 24
Peak memory 197264 kb
Host smart-03a98ea3-9ed1-41e5-a364-3c67640d25ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610738183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1610738183
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3867705635
Short name T294
Test name
Test status
Simulation time 27434372 ps
CPU time 0.8 seconds
Started Jul 23 06:01:14 PM PDT 24
Finished Jul 23 06:01:15 PM PDT 24
Peak memory 196040 kb
Host smart-472e9dc4-9fe8-4fb8-8938-1eaf2b02850a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867705635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3867705635
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.887611251
Short name T326
Test name
Test status
Simulation time 234478619 ps
CPU time 1.28 seconds
Started Jul 23 06:01:13 PM PDT 24
Finished Jul 23 06:01:14 PM PDT 24
Peak memory 197644 kb
Host smart-31e8a076-4b9c-4185-a875-e32abf2dfa02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887611251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup_
pulldown.887611251
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2554532061
Short name T562
Test name
Test status
Simulation time 168852950 ps
CPU time 1.93 seconds
Started Jul 23 06:01:08 PM PDT 24
Finished Jul 23 06:01:10 PM PDT 24
Peak memory 198512 kb
Host smart-7f7bf6c0-b593-4b44-bd7c-ba5483a9b311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554532061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2554532061
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1810761093
Short name T43
Test name
Test status
Simulation time 136238515 ps
CPU time 0.79 seconds
Started Jul 23 06:01:16 PM PDT 24
Finished Jul 23 06:01:17 PM PDT 24
Peak memory 214256 kb
Host smart-84fe76c4-e93d-408f-b8f2-981d55ef810f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810761093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1810761093
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2902658922
Short name T478
Test name
Test status
Simulation time 608952661 ps
CPU time 0.99 seconds
Started Jul 23 06:01:20 PM PDT 24
Finished Jul 23 06:01:21 PM PDT 24
Peak memory 196796 kb
Host smart-05292bb7-b209-4c24-b97a-1f0b01924e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902658922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2902658922
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3013724362
Short name T253
Test name
Test status
Simulation time 298527347 ps
CPU time 1.27 seconds
Started Jul 23 06:01:20 PM PDT 24
Finished Jul 23 06:01:22 PM PDT 24
Peak memory 198568 kb
Host smart-b1572121-fc5e-4cec-b0a6-cb8c8b0b9f8a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013724362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3013724362
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1569157128
Short name T225
Test name
Test status
Simulation time 16569824320 ps
CPU time 220.56 seconds
Started Jul 23 06:01:15 PM PDT 24
Finished Jul 23 06:04:56 PM PDT 24
Peak memory 198596 kb
Host smart-20704293-05e7-4763-8855-f7d6c82ea154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569157128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1569157128
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.554773212
Short name T354
Test name
Test status
Simulation time 33678033 ps
CPU time 0.56 seconds
Started Jul 23 06:01:18 PM PDT 24
Finished Jul 23 06:01:19 PM PDT 24
Peak memory 194448 kb
Host smart-09855c30-3ef5-4cd3-a7e9-13d7316ef406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554773212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.554773212
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3677378144
Short name T271
Test name
Test status
Simulation time 20494444 ps
CPU time 0.68 seconds
Started Jul 23 06:01:25 PM PDT 24
Finished Jul 23 06:01:26 PM PDT 24
Peak memory 194596 kb
Host smart-022511c0-1b1e-4a85-bdf0-386b7c783d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677378144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3677378144
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2014734583
Short name T284
Test name
Test status
Simulation time 1812400638 ps
CPU time 21.56 seconds
Started Jul 23 06:01:26 PM PDT 24
Finished Jul 23 06:01:49 PM PDT 24
Peak memory 197324 kb
Host smart-0b6122f9-c3e7-4313-9a42-c5be2ee6cb3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014734583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2014734583
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.26830960
Short name T301
Test name
Test status
Simulation time 357079676 ps
CPU time 1.15 seconds
Started Jul 23 06:01:21 PM PDT 24
Finished Jul 23 06:01:22 PM PDT 24
Peak memory 198608 kb
Host smart-307d238f-eb61-4b70-8316-daa1a6a118e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26830960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.26830960
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2427788216
Short name T25
Test name
Test status
Simulation time 59834061 ps
CPU time 0.85 seconds
Started Jul 23 06:01:24 PM PDT 24
Finished Jul 23 06:01:26 PM PDT 24
Peak memory 196768 kb
Host smart-06031f44-111e-4582-9094-e02c653b45e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427788216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2427788216
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2844152766
Short name T460
Test name
Test status
Simulation time 29775787 ps
CPU time 1.2 seconds
Started Jul 23 06:01:26 PM PDT 24
Finished Jul 23 06:01:28 PM PDT 24
Peak memory 198492 kb
Host smart-dfda936f-72bf-4d7e-9068-e9027dfccb4e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844152766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2844152766
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.578736968
Short name T142
Test name
Test status
Simulation time 56770668 ps
CPU time 1.37 seconds
Started Jul 23 06:01:28 PM PDT 24
Finished Jul 23 06:01:31 PM PDT 24
Peak memory 197312 kb
Host smart-94e5d8af-be71-4947-95a1-3ccad04a9b38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578736968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.578736968
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1684596734
Short name T241
Test name
Test status
Simulation time 124376719 ps
CPU time 1.2 seconds
Started Jul 23 06:01:13 PM PDT 24
Finished Jul 23 06:01:15 PM PDT 24
Peak memory 197512 kb
Host smart-64f8eb35-fc2a-438a-aba9-86827add95af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684596734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1684596734
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1550813498
Short name T147
Test name
Test status
Simulation time 36888561 ps
CPU time 1.23 seconds
Started Jul 23 06:01:22 PM PDT 24
Finished Jul 23 06:01:24 PM PDT 24
Peak memory 198540 kb
Host smart-ffdbcce2-dc61-493f-835b-ab7939ae19f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550813498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1550813498
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2508904394
Short name T325
Test name
Test status
Simulation time 501777267 ps
CPU time 3.16 seconds
Started Jul 23 06:01:20 PM PDT 24
Finished Jul 23 06:01:24 PM PDT 24
Peak memory 198368 kb
Host smart-a25dcd7b-4472-430c-8b52-5b1d15c653a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508904394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2508904394
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2799872277
Short name T34
Test name
Test status
Simulation time 351295374 ps
CPU time 0.94 seconds
Started Jul 23 06:01:23 PM PDT 24
Finished Jul 23 06:01:24 PM PDT 24
Peak memory 214488 kb
Host smart-9803cfbe-aeda-4cb1-a0d4-e976c91d9ed5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799872277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2799872277
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2190238263
Short name T677
Test name
Test status
Simulation time 26359211 ps
CPU time 0.82 seconds
Started Jul 23 06:01:15 PM PDT 24
Finished Jul 23 06:01:16 PM PDT 24
Peak memory 195720 kb
Host smart-c68c3208-f6b8-4643-b182-45bc2d830b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190238263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2190238263
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1473439402
Short name T124
Test name
Test status
Simulation time 435028259 ps
CPU time 1.33 seconds
Started Jul 23 06:01:16 PM PDT 24
Finished Jul 23 06:01:18 PM PDT 24
Peak memory 196732 kb
Host smart-991b2ae9-2fcf-43a7-9f1f-ec1306165a2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473439402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1473439402
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2314479294
Short name T212
Test name
Test status
Simulation time 41120308363 ps
CPU time 125.14 seconds
Started Jul 23 06:01:26 PM PDT 24
Finished Jul 23 06:03:32 PM PDT 24
Peak memory 198864 kb
Host smart-ed42dbfa-7581-49ff-8d76-f8da3ec34b65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314479294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2314479294
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1975533766
Short name T548
Test name
Test status
Simulation time 20289282 ps
CPU time 0.58 seconds
Started Jul 23 06:01:56 PM PDT 24
Finished Jul 23 06:01:58 PM PDT 24
Peak memory 195084 kb
Host smart-bec37447-8090-491d-ae99-3fe856fa7778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975533766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1975533766
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2388636729
Short name T472
Test name
Test status
Simulation time 35448882 ps
CPU time 0.84 seconds
Started Jul 23 06:01:53 PM PDT 24
Finished Jul 23 06:01:54 PM PDT 24
Peak memory 195744 kb
Host smart-d68ce995-8b61-455a-9a95-e995cf96fa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388636729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2388636729
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2261242089
Short name T704
Test name
Test status
Simulation time 2599038511 ps
CPU time 17.52 seconds
Started Jul 23 06:01:59 PM PDT 24
Finished Jul 23 06:02:18 PM PDT 24
Peak memory 197560 kb
Host smart-a63a2145-f648-4405-ab79-ba4f845c6b86
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261242089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2261242089
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.2622694899
Short name T393
Test name
Test status
Simulation time 211129800 ps
CPU time 0.76 seconds
Started Jul 23 06:01:47 PM PDT 24
Finished Jul 23 06:01:48 PM PDT 24
Peak memory 196448 kb
Host smart-19ff988c-7e1b-4cd2-8f11-260fe6b27b33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622694899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.2622694899
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.746775048
Short name T468
Test name
Test status
Simulation time 58887126 ps
CPU time 0.7 seconds
Started Jul 23 06:01:49 PM PDT 24
Finished Jul 23 06:01:51 PM PDT 24
Peak memory 194820 kb
Host smart-0a9706f4-84d9-4ec2-ba1d-1635cd9931f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746775048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.746775048
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2643571122
Short name T406
Test name
Test status
Simulation time 86829760 ps
CPU time 3.16 seconds
Started Jul 23 06:01:56 PM PDT 24
Finished Jul 23 06:02:00 PM PDT 24
Peak memory 198660 kb
Host smart-0cdc062e-aa99-4788-908b-395aacb259dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643571122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2643571122
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2708123825
Short name T21
Test name
Test status
Simulation time 141750092 ps
CPU time 2.98 seconds
Started Jul 23 06:02:02 PM PDT 24
Finished Jul 23 06:02:05 PM PDT 24
Peak memory 198612 kb
Host smart-a49006aa-cbc7-42e1-bd2a-0d00883b9f99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708123825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2708123825
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1180795118
Short name T440
Test name
Test status
Simulation time 124417604 ps
CPU time 1.24 seconds
Started Jul 23 06:01:59 PM PDT 24
Finished Jul 23 06:02:01 PM PDT 24
Peak memory 197288 kb
Host smart-99936dc7-a9c3-4640-99a6-77c5fe7616c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180795118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1180795118
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.921501404
Short name T656
Test name
Test status
Simulation time 204547927 ps
CPU time 0.88 seconds
Started Jul 23 06:01:42 PM PDT 24
Finished Jul 23 06:01:44 PM PDT 24
Peak memory 197816 kb
Host smart-97c83c90-8811-4371-885d-9dad2c0eb8de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921501404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.921501404
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.694777792
Short name T194
Test name
Test status
Simulation time 109081031 ps
CPU time 1.51 seconds
Started Jul 23 06:01:50 PM PDT 24
Finished Jul 23 06:01:52 PM PDT 24
Peak memory 198440 kb
Host smart-1a0f2dba-d9da-4903-83ac-26a4c8b935e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694777792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.694777792
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2508356673
Short name T555
Test name
Test status
Simulation time 20694154 ps
CPU time 0.67 seconds
Started Jul 23 06:01:43 PM PDT 24
Finished Jul 23 06:01:45 PM PDT 24
Peak memory 195336 kb
Host smart-ac729142-9b1d-4bed-9f65-1dcc71d4cb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508356673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2508356673
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.386084228
Short name T426
Test name
Test status
Simulation time 158544735 ps
CPU time 1.2 seconds
Started Jul 23 06:01:48 PM PDT 24
Finished Jul 23 06:01:50 PM PDT 24
Peak memory 197020 kb
Host smart-775f49a6-f8fa-4a59-a0a0-f5d314af7a2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386084228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.386084228
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2615511750
Short name T578
Test name
Test status
Simulation time 7100576822 ps
CPU time 82.52 seconds
Started Jul 23 06:02:09 PM PDT 24
Finished Jul 23 06:03:32 PM PDT 24
Peak memory 198588 kb
Host smart-5c64cdee-13b2-46ca-8976-9c20c79e7acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615511750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2615511750
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.1308240931
Short name T130
Test name
Test status
Simulation time 21575892 ps
CPU time 0.64 seconds
Started Jul 23 06:01:55 PM PDT 24
Finished Jul 23 06:01:56 PM PDT 24
Peak memory 194596 kb
Host smart-13a1f9ea-3ed2-4dcc-8651-be4dcc199267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308240931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.1308240931
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2071537566
Short name T438
Test name
Test status
Simulation time 1583004651 ps
CPU time 10.84 seconds
Started Jul 23 06:01:59 PM PDT 24
Finished Jul 23 06:02:11 PM PDT 24
Peak memory 197384 kb
Host smart-3102968c-220d-48c3-894a-3ad2715c081c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071537566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2071537566
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.69267255
Short name T565
Test name
Test status
Simulation time 341696876 ps
CPU time 0.88 seconds
Started Jul 23 06:02:01 PM PDT 24
Finished Jul 23 06:02:03 PM PDT 24
Peak memory 196368 kb
Host smart-9929405a-4529-49a1-81c7-5b5dd5067940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69267255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.69267255
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2082555780
Short name T118
Test name
Test status
Simulation time 172762172 ps
CPU time 1.32 seconds
Started Jul 23 06:01:56 PM PDT 24
Finished Jul 23 06:01:58 PM PDT 24
Peak memory 196496 kb
Host smart-ee7a382b-9dd2-4e28-910a-a6d063d430cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082555780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2082555780
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1481926643
Short name T342
Test name
Test status
Simulation time 43103379 ps
CPU time 1.75 seconds
Started Jul 23 06:01:56 PM PDT 24
Finished Jul 23 06:01:58 PM PDT 24
Peak memory 198568 kb
Host smart-0441d5f0-efee-4c2e-a594-406817faace9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481926643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1481926643
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4060250584
Short name T650
Test name
Test status
Simulation time 97113852 ps
CPU time 2.86 seconds
Started Jul 23 06:02:03 PM PDT 24
Finished Jul 23 06:02:08 PM PDT 24
Peak memory 198604 kb
Host smart-c9723d7b-a8fa-4316-964c-44a4cc82d01a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060250584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4060250584
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1234190522
Short name T268
Test name
Test status
Simulation time 254986189 ps
CPU time 1.38 seconds
Started Jul 23 06:01:49 PM PDT 24
Finished Jul 23 06:01:51 PM PDT 24
Peak memory 198540 kb
Host smart-c705d78a-1ce4-42fd-a09c-7329e0905af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234190522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1234190522
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3191375725
Short name T101
Test name
Test status
Simulation time 79839122 ps
CPU time 0.74 seconds
Started Jul 23 06:02:08 PM PDT 24
Finished Jul 23 06:02:09 PM PDT 24
Peak memory 195892 kb
Host smart-3c278112-796c-4725-84cc-762464f0d5df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191375725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3191375725
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3474563147
Short name T606
Test name
Test status
Simulation time 369965516 ps
CPU time 3.12 seconds
Started Jul 23 06:02:03 PM PDT 24
Finished Jul 23 06:02:07 PM PDT 24
Peak memory 198288 kb
Host smart-4df3c411-a1c5-4a72-9db2-8d1d6c63b806
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474563147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3474563147
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1822367630
Short name T243
Test name
Test status
Simulation time 235751470 ps
CPU time 1.08 seconds
Started Jul 23 06:02:04 PM PDT 24
Finished Jul 23 06:02:06 PM PDT 24
Peak memory 195992 kb
Host smart-8e46ca7f-7a1c-4ac6-8432-63aee2831a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822367630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1822367630
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3398843992
Short name T367
Test name
Test status
Simulation time 274850527 ps
CPU time 1.19 seconds
Started Jul 23 06:01:47 PM PDT 24
Finished Jul 23 06:01:49 PM PDT 24
Peak memory 196272 kb
Host smart-1af13c58-e5eb-4967-8d8c-40022238631b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398843992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3398843992
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.393345270
Short name T702
Test name
Test status
Simulation time 6814415002 ps
CPU time 170.98 seconds
Started Jul 23 06:01:55 PM PDT 24
Finished Jul 23 06:04:47 PM PDT 24
Peak memory 198620 kb
Host smart-87ff36e7-ad1f-4ce0-9586-1b6b381a3887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393345270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.393345270
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2978965051
Short name T249
Test name
Test status
Simulation time 13027297 ps
CPU time 0.57 seconds
Started Jul 23 06:02:02 PM PDT 24
Finished Jul 23 06:02:05 PM PDT 24
Peak memory 195140 kb
Host smart-06a79ad8-eaad-410d-847f-2cf1f8c01c1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978965051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2978965051
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2809924661
Short name T490
Test name
Test status
Simulation time 89219263 ps
CPU time 0.76 seconds
Started Jul 23 06:02:01 PM PDT 24
Finished Jul 23 06:02:03 PM PDT 24
Peak memory 195336 kb
Host smart-2ac3fa4b-d2d8-4deb-9620-b5c1ef369b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809924661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2809924661
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1724670613
Short name T131
Test name
Test status
Simulation time 1000073278 ps
CPU time 28.15 seconds
Started Jul 23 06:02:00 PM PDT 24
Finished Jul 23 06:02:29 PM PDT 24
Peak memory 197528 kb
Host smart-8f9ee586-0b86-4a13-bf31-d6c63d2fa111
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724670613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1724670613
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2191203625
Short name T554
Test name
Test status
Simulation time 228819432 ps
CPU time 0.96 seconds
Started Jul 23 06:02:01 PM PDT 24
Finished Jul 23 06:02:03 PM PDT 24
Peak memory 196916 kb
Host smart-4d1929ff-e30f-4266-ab2d-9fa11a8feded
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191203625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2191203625
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2666932608
Short name T364
Test name
Test status
Simulation time 88354737 ps
CPU time 1 seconds
Started Jul 23 06:01:58 PM PDT 24
Finished Jul 23 06:02:00 PM PDT 24
Peak memory 196516 kb
Host smart-7c2b597c-b786-4781-8f7f-d7eebe1a573b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666932608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2666932608
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3129902964
Short name T94
Test name
Test status
Simulation time 71413341 ps
CPU time 2.77 seconds
Started Jul 23 06:02:09 PM PDT 24
Finished Jul 23 06:02:13 PM PDT 24
Peak memory 198580 kb
Host smart-17c1087c-de2e-4770-b927-27e1bad3560f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129902964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3129902964
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2560412466
Short name T370
Test name
Test status
Simulation time 135971433 ps
CPU time 1.28 seconds
Started Jul 23 06:02:14 PM PDT 24
Finished Jul 23 06:02:16 PM PDT 24
Peak memory 196600 kb
Host smart-3d97b815-a3fb-4460-90bc-b2c6c6778947
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560412466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2560412466
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3980953256
Short name T546
Test name
Test status
Simulation time 63031504 ps
CPU time 0.64 seconds
Started Jul 23 06:01:56 PM PDT 24
Finished Jul 23 06:01:57 PM PDT 24
Peak memory 194704 kb
Host smart-8e8c724e-8141-446a-9a04-2d6cf1255fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980953256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3980953256
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.36832668
Short name T210
Test name
Test status
Simulation time 23338143 ps
CPU time 0.67 seconds
Started Jul 23 06:01:57 PM PDT 24
Finished Jul 23 06:01:59 PM PDT 24
Peak memory 194860 kb
Host smart-62904a73-dfd7-4ae9-9d8a-efcfae70215f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36832668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup_
pulldown.36832668
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1448555070
Short name T351
Test name
Test status
Simulation time 527508889 ps
CPU time 5.88 seconds
Started Jul 23 06:01:57 PM PDT 24
Finished Jul 23 06:02:04 PM PDT 24
Peak memory 198452 kb
Host smart-024e4fa8-0e3e-463f-a852-1877827acd60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448555070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1448555070
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.794153842
Short name T323
Test name
Test status
Simulation time 287724926 ps
CPU time 1.32 seconds
Started Jul 23 06:01:55 PM PDT 24
Finished Jul 23 06:01:57 PM PDT 24
Peak memory 197252 kb
Host smart-e3df1b06-77f8-40d2-b9df-bd7d161dc632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794153842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.794153842
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2073230690
Short name T686
Test name
Test status
Simulation time 112979468 ps
CPU time 1.16 seconds
Started Jul 23 06:02:00 PM PDT 24
Finished Jul 23 06:02:03 PM PDT 24
Peak memory 196096 kb
Host smart-fddcf2d8-12e1-4212-b350-cbb60f15cdc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073230690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2073230690
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4043869626
Short name T215
Test name
Test status
Simulation time 48180842723 ps
CPU time 141.45 seconds
Started Jul 23 06:02:11 PM PDT 24
Finished Jul 23 06:04:33 PM PDT 24
Peak memory 198648 kb
Host smart-62a75b96-28b2-448c-a8a3-36d69676995a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043869626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4043869626
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1050436088
Short name T447
Test name
Test status
Simulation time 43871723690 ps
CPU time 435.24 seconds
Started Jul 23 06:02:20 PM PDT 24
Finished Jul 23 06:09:37 PM PDT 24
Peak memory 198700 kb
Host smart-7ecf4d60-bed5-45f3-8229-1694e292b80f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1050436088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1050436088
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3664238194
Short name T624
Test name
Test status
Simulation time 13561473 ps
CPU time 0.58 seconds
Started Jul 23 06:02:03 PM PDT 24
Finished Jul 23 06:02:05 PM PDT 24
Peak memory 194580 kb
Host smart-7fef33eb-73c2-403c-94a8-703c3daae304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664238194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3664238194
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4003423634
Short name T203
Test name
Test status
Simulation time 23385756 ps
CPU time 0.71 seconds
Started Jul 23 06:02:03 PM PDT 24
Finished Jul 23 06:02:05 PM PDT 24
Peak memory 194596 kb
Host smart-7489c430-9890-479d-ab3b-755b06fd3b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003423634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4003423634
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.879675629
Short name T337
Test name
Test status
Simulation time 2722371378 ps
CPU time 8.11 seconds
Started Jul 23 06:02:13 PM PDT 24
Finished Jul 23 06:02:22 PM PDT 24
Peak memory 197112 kb
Host smart-2a7e1e89-3361-4cae-bf84-09033b4129d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879675629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.879675629
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2814566763
Short name T357
Test name
Test status
Simulation time 157335647 ps
CPU time 0.8 seconds
Started Jul 23 06:02:10 PM PDT 24
Finished Jul 23 06:02:12 PM PDT 24
Peak memory 196444 kb
Host smart-1cdbf5d2-cd8f-473c-b69c-c1eff8083b4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814566763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2814566763
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1396301714
Short name T524
Test name
Test status
Simulation time 1052211500 ps
CPU time 1.08 seconds
Started Jul 23 06:02:17 PM PDT 24
Finished Jul 23 06:02:19 PM PDT 24
Peak memory 196480 kb
Host smart-076fa07d-28b5-43a6-b237-1dd0146312be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396301714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1396301714
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2811509936
Short name T474
Test name
Test status
Simulation time 52711091 ps
CPU time 2.03 seconds
Started Jul 23 06:02:22 PM PDT 24
Finished Jul 23 06:02:25 PM PDT 24
Peak memory 198592 kb
Host smart-6a02fc46-abd3-4035-8cfc-fcaaf511438c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811509936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2811509936
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3352772013
Short name T701
Test name
Test status
Simulation time 70949417 ps
CPU time 2.2 seconds
Started Jul 23 06:02:02 PM PDT 24
Finished Jul 23 06:02:06 PM PDT 24
Peak memory 197416 kb
Host smart-e9d90b37-c1fc-400b-82d7-6693e19227a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352772013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3352772013
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2644996593
Short name T262
Test name
Test status
Simulation time 729298845 ps
CPU time 1.02 seconds
Started Jul 23 06:02:03 PM PDT 24
Finished Jul 23 06:02:10 PM PDT 24
Peak memory 196468 kb
Host smart-202d9133-0366-44e1-900d-07429bf258e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644996593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2644996593
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.648508432
Short name T601
Test name
Test status
Simulation time 30170983 ps
CPU time 0.77 seconds
Started Jul 23 06:02:17 PM PDT 24
Finished Jul 23 06:02:18 PM PDT 24
Peak memory 196184 kb
Host smart-4fcad1c9-3279-4fdb-8316-f461689a68e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648508432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.648508432
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3223035306
Short name T512
Test name
Test status
Simulation time 122137121 ps
CPU time 2.26 seconds
Started Jul 23 06:02:13 PM PDT 24
Finished Jul 23 06:02:16 PM PDT 24
Peak memory 198476 kb
Host smart-307a6ff0-d95b-4fe3-87fe-ab1679c71be4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223035306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3223035306
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3403373419
Short name T90
Test name
Test status
Simulation time 76200588 ps
CPU time 1.32 seconds
Started Jul 23 06:02:08 PM PDT 24
Finished Jul 23 06:02:10 PM PDT 24
Peak memory 198528 kb
Host smart-3d15ab81-36e4-4c9d-a466-5f970409bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403373419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3403373419
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3503980598
Short name T49
Test name
Test status
Simulation time 77495235 ps
CPU time 1.01 seconds
Started Jul 23 06:02:20 PM PDT 24
Finished Jul 23 06:02:21 PM PDT 24
Peak memory 197060 kb
Host smart-f4e20336-d76a-423e-97c8-fd8c19d6b2c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503980598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3503980598
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2326151431
Short name T10
Test name
Test status
Simulation time 15415050577 ps
CPU time 84.14 seconds
Started Jul 23 06:02:20 PM PDT 24
Finished Jul 23 06:03:45 PM PDT 24
Peak memory 198644 kb
Host smart-e23d3196-d89b-4a25-9fd2-3be1b2d14e39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326151431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2326151431
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.4049333288
Short name T58
Test name
Test status
Simulation time 113614882548 ps
CPU time 2094.3 seconds
Started Jul 23 06:02:18 PM PDT 24
Finished Jul 23 06:37:13 PM PDT 24
Peak memory 198708 kb
Host smart-4a6b9a30-3a6b-441b-a987-3fda8cfa2659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4049333288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.4049333288
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2691587965
Short name T604
Test name
Test status
Simulation time 17969999 ps
CPU time 0.6 seconds
Started Jul 23 06:02:13 PM PDT 24
Finished Jul 23 06:02:14 PM PDT 24
Peak memory 194632 kb
Host smart-0d087d18-9c61-4f85-8a8b-e5c37bdee844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691587965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2691587965
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3212624473
Short name T541
Test name
Test status
Simulation time 61331153 ps
CPU time 0.71 seconds
Started Jul 23 06:02:03 PM PDT 24
Finished Jul 23 06:02:05 PM PDT 24
Peak memory 196496 kb
Host smart-0fbbc7b3-7a1e-4e13-b45a-6d154adbe8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212624473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3212624473
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2650612547
Short name T368
Test name
Test status
Simulation time 1868038888 ps
CPU time 17.03 seconds
Started Jul 23 06:02:22 PM PDT 24
Finished Jul 23 06:02:41 PM PDT 24
Peak memory 196800 kb
Host smart-2906d872-f9f4-4f83-b24d-fc3c54375555
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650612547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2650612547
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.152196996
Short name T8
Test name
Test status
Simulation time 74605190 ps
CPU time 0.98 seconds
Started Jul 23 06:02:20 PM PDT 24
Finished Jul 23 06:02:22 PM PDT 24
Peak memory 197716 kb
Host smart-3339bbc4-3d9b-4412-ad18-d0fd9e9594fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152196996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.152196996
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1788424563
Short name T612
Test name
Test status
Simulation time 71156404 ps
CPU time 0.66 seconds
Started Jul 23 06:02:02 PM PDT 24
Finished Jul 23 06:02:04 PM PDT 24
Peak memory 194800 kb
Host smart-22771a59-24e1-4248-ba10-6213c469b2a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788424563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1788424563
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3868880147
Short name T181
Test name
Test status
Simulation time 56363807 ps
CPU time 1.5 seconds
Started Jul 23 06:02:22 PM PDT 24
Finished Jul 23 06:02:25 PM PDT 24
Peak memory 198552 kb
Host smart-914d2ddb-15a7-4648-9ca8-db6815ad7b44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868880147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3868880147
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1376727083
Short name T280
Test name
Test status
Simulation time 134096171 ps
CPU time 1.51 seconds
Started Jul 23 06:02:16 PM PDT 24
Finished Jul 23 06:02:18 PM PDT 24
Peak memory 196308 kb
Host smart-13aa03e7-947b-4efa-9fde-8181a091fa12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376727083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1376727083
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1715975003
Short name T552
Test name
Test status
Simulation time 25662301 ps
CPU time 0.76 seconds
Started Jul 23 06:02:20 PM PDT 24
Finished Jul 23 06:02:21 PM PDT 24
Peak memory 196028 kb
Host smart-30020a84-a2ba-4bac-9fbc-91286b9680c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715975003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1715975003
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1606501724
Short name T494
Test name
Test status
Simulation time 56229242 ps
CPU time 1.18 seconds
Started Jul 23 06:02:20 PM PDT 24
Finished Jul 23 06:02:22 PM PDT 24
Peak memory 197204 kb
Host smart-d3b9a4f4-cf4e-4d15-aeaa-d9b6f02a6d96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606501724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1606501724
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2117094396
Short name T186
Test name
Test status
Simulation time 60754226 ps
CPU time 1.23 seconds
Started Jul 23 06:02:22 PM PDT 24
Finished Jul 23 06:02:25 PM PDT 24
Peak memory 198448 kb
Host smart-bb0b8103-c1d0-4421-84a2-4a7ae6008cb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117094396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2117094396
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3680385626
Short name T453
Test name
Test status
Simulation time 46849143 ps
CPU time 0.89 seconds
Started Jul 23 06:02:23 PM PDT 24
Finished Jul 23 06:02:26 PM PDT 24
Peak memory 195828 kb
Host smart-f88c8aac-078e-409b-81ef-6ffc353e879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680385626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3680385626
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3448791410
Short name T676
Test name
Test status
Simulation time 68072236 ps
CPU time 1.11 seconds
Started Jul 23 06:02:10 PM PDT 24
Finished Jul 23 06:02:12 PM PDT 24
Peak memory 196244 kb
Host smart-7e16b646-5492-4c90-ae76-aa1962644415
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448791410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3448791410
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3176283561
Short name T297
Test name
Test status
Simulation time 20674054971 ps
CPU time 78.6 seconds
Started Jul 23 06:02:16 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 198668 kb
Host smart-a8910e3e-4ad8-4762-bfce-f192e7e94f78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176283561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3176283561
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.701884690
Short name T456
Test name
Test status
Simulation time 36114063902 ps
CPU time 122.66 seconds
Started Jul 23 06:02:20 PM PDT 24
Finished Jul 23 06:04:23 PM PDT 24
Peak memory 198716 kb
Host smart-452d3f84-5177-44c1-a02a-41da9ec38d73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=701884690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.701884690
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2547830423
Short name T455
Test name
Test status
Simulation time 44662521 ps
CPU time 0.55 seconds
Started Jul 23 06:02:25 PM PDT 24
Finished Jul 23 06:02:27 PM PDT 24
Peak memory 194456 kb
Host smart-5a83d653-fbf3-43bc-b167-a3cb6f8cca44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547830423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2547830423
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1639803795
Short name T135
Test name
Test status
Simulation time 133094475 ps
CPU time 0.81 seconds
Started Jul 23 06:02:19 PM PDT 24
Finished Jul 23 06:02:20 PM PDT 24
Peak memory 197000 kb
Host smart-c6252a6d-3d56-42d4-9411-db10e59b5ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639803795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1639803795
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2350107640
Short name T309
Test name
Test status
Simulation time 325338938 ps
CPU time 7.66 seconds
Started Jul 23 06:02:17 PM PDT 24
Finished Jul 23 06:02:25 PM PDT 24
Peak memory 196048 kb
Host smart-4c18107e-0055-407c-b7f9-aacdca0a050d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350107640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2350107640
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1846069667
Short name T549
Test name
Test status
Simulation time 432751799 ps
CPU time 0.88 seconds
Started Jul 23 06:02:25 PM PDT 24
Finished Jul 23 06:02:27 PM PDT 24
Peak memory 197480 kb
Host smart-ab831490-aa98-45b8-bc4b-ad5c283e1aaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846069667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1846069667
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.828476586
Short name T561
Test name
Test status
Simulation time 20974282 ps
CPU time 0.79 seconds
Started Jul 23 06:02:14 PM PDT 24
Finished Jul 23 06:02:16 PM PDT 24
Peak memory 196020 kb
Host smart-8fbafd0e-324b-4724-93a3-b45c2f64836f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828476586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.828476586
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3648959242
Short name T580
Test name
Test status
Simulation time 50604685 ps
CPU time 1.89 seconds
Started Jul 23 06:02:13 PM PDT 24
Finished Jul 23 06:02:16 PM PDT 24
Peak memory 198648 kb
Host smart-5782ab26-e6ba-4a0f-b983-ba50d73dd969
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648959242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3648959242
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3691270295
Short name T102
Test name
Test status
Simulation time 43168561 ps
CPU time 1.22 seconds
Started Jul 23 06:02:21 PM PDT 24
Finished Jul 23 06:02:23 PM PDT 24
Peak memory 195936 kb
Host smart-cb982df6-cf5c-4df3-b840-b1745ca03cc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691270295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3691270295
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.327051821
Short name T237
Test name
Test status
Simulation time 161935180 ps
CPU time 0.99 seconds
Started Jul 23 06:02:28 PM PDT 24
Finished Jul 23 06:02:30 PM PDT 24
Peak memory 196544 kb
Host smart-d08d20ea-611a-46e8-9ce2-817b7361b054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327051821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.327051821
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3618296433
Short name T466
Test name
Test status
Simulation time 102979363 ps
CPU time 1.15 seconds
Started Jul 23 06:02:12 PM PDT 24
Finished Jul 23 06:02:14 PM PDT 24
Peak memory 196616 kb
Host smart-faa949b8-ce19-4b54-aa21-deeb04bf4ae2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618296433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3618296433
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2154881709
Short name T285
Test name
Test status
Simulation time 877942744 ps
CPU time 2.68 seconds
Started Jul 23 06:02:15 PM PDT 24
Finished Jul 23 06:02:19 PM PDT 24
Peak memory 198528 kb
Host smart-ece4f548-86d8-450e-a935-554479836657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154881709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2154881709
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.960759038
Short name T144
Test name
Test status
Simulation time 45899495 ps
CPU time 1.15 seconds
Started Jul 23 06:02:19 PM PDT 24
Finished Jul 23 06:02:21 PM PDT 24
Peak memory 196084 kb
Host smart-690ca890-1f7d-4676-8a69-7322f73f38ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960759038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.960759038
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3128301973
Short name T513
Test name
Test status
Simulation time 417945012 ps
CPU time 0.84 seconds
Started Jul 23 06:02:23 PM PDT 24
Finished Jul 23 06:02:26 PM PDT 24
Peak memory 195856 kb
Host smart-1ba5ff8b-bdf0-4b51-859c-41915519b1cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128301973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3128301973
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2489931496
Short name T233
Test name
Test status
Simulation time 7889195074 ps
CPU time 106.98 seconds
Started Jul 23 06:02:18 PM PDT 24
Finished Jul 23 06:04:05 PM PDT 24
Peak memory 198588 kb
Host smart-d8e20244-fbda-4ed7-89a5-23af2c19b8cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489931496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2489931496
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.453883021
Short name T654
Test name
Test status
Simulation time 109037631 ps
CPU time 0.59 seconds
Started Jul 23 06:02:26 PM PDT 24
Finished Jul 23 06:02:28 PM PDT 24
Peak memory 194444 kb
Host smart-71ec0b33-1751-4eca-af74-37ffb2891f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453883021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.453883021
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.332002629
Short name T470
Test name
Test status
Simulation time 179934982 ps
CPU time 0.92 seconds
Started Jul 23 06:02:21 PM PDT 24
Finished Jul 23 06:02:23 PM PDT 24
Peak memory 197268 kb
Host smart-f7bd6e6d-20f3-4487-9583-d2935efa7647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332002629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.332002629
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3323365353
Short name T452
Test name
Test status
Simulation time 201695807 ps
CPU time 10.77 seconds
Started Jul 23 06:02:22 PM PDT 24
Finished Jul 23 06:02:35 PM PDT 24
Peak memory 196096 kb
Host smart-750dae13-7e6b-4c90-9af8-3cf7449dfa48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323365353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3323365353
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1371514226
Short name T197
Test name
Test status
Simulation time 210917272 ps
CPU time 0.8 seconds
Started Jul 23 06:02:28 PM PDT 24
Finished Jul 23 06:02:29 PM PDT 24
Peak memory 196368 kb
Host smart-9ff0d91c-9e22-44eb-bdfa-c632b62513cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371514226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1371514226
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2795342774
Short name T449
Test name
Test status
Simulation time 65051919 ps
CPU time 0.73 seconds
Started Jul 23 06:02:22 PM PDT 24
Finished Jul 23 06:02:25 PM PDT 24
Peak memory 196652 kb
Host smart-0197e1a8-671c-41c3-890c-c54c518c873e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795342774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2795342774
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.911496069
Short name T178
Test name
Test status
Simulation time 80756318 ps
CPU time 2.98 seconds
Started Jul 23 06:02:27 PM PDT 24
Finished Jul 23 06:02:31 PM PDT 24
Peak memory 197740 kb
Host smart-54cacbb1-7abe-4803-ac13-647f8bd6de18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911496069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.911496069
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.4245439290
Short name T670
Test name
Test status
Simulation time 99089197 ps
CPU time 2.74 seconds
Started Jul 23 06:02:23 PM PDT 24
Finished Jul 23 06:02:28 PM PDT 24
Peak memory 197632 kb
Host smart-fe7c2f73-77d9-4093-9356-a1cd7abbb5f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245439290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.4245439290
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3810895851
Short name T634
Test name
Test status
Simulation time 80618685 ps
CPU time 1.08 seconds
Started Jul 23 06:02:18 PM PDT 24
Finished Jul 23 06:02:20 PM PDT 24
Peak memory 196324 kb
Host smart-a88861e8-ca0e-454a-8692-7db6b404e67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810895851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3810895851
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2660986194
Short name T22
Test name
Test status
Simulation time 204847696 ps
CPU time 1.2 seconds
Started Jul 23 06:02:19 PM PDT 24
Finished Jul 23 06:02:21 PM PDT 24
Peak memory 197140 kb
Host smart-a7b8630d-17e2-4b97-aa5f-93d57c5516b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660986194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2660986194
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1745561617
Short name T479
Test name
Test status
Simulation time 356695311 ps
CPU time 1.94 seconds
Started Jul 23 06:02:43 PM PDT 24
Finished Jul 23 06:02:46 PM PDT 24
Peak memory 198464 kb
Host smart-1f2b736b-034e-4317-a504-31782db47643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745561617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1745561617
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2943342224
Short name T100
Test name
Test status
Simulation time 94193729 ps
CPU time 1 seconds
Started Jul 23 06:02:12 PM PDT 24
Finished Jul 23 06:02:14 PM PDT 24
Peak memory 196080 kb
Host smart-45aaeab1-f9d0-4be9-b4e6-80cea306b31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943342224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2943342224
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.2717853696
Short name T110
Test name
Test status
Simulation time 206423773 ps
CPU time 1.23 seconds
Started Jul 23 06:02:14 PM PDT 24
Finished Jul 23 06:02:16 PM PDT 24
Peak memory 197064 kb
Host smart-58296c07-3d51-42d1-8512-e4b7eb848502
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717853696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.2717853696
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1304847408
Short name T531
Test name
Test status
Simulation time 123616049860 ps
CPU time 170.45 seconds
Started Jul 23 06:02:29 PM PDT 24
Finished Jul 23 06:05:20 PM PDT 24
Peak memory 198680 kb
Host smart-8c3b7241-8536-485c-9694-e0ec835a3a69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304847408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1304847408
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3879860502
Short name T441
Test name
Test status
Simulation time 18790404 ps
CPU time 0.57 seconds
Started Jul 23 06:02:34 PM PDT 24
Finished Jul 23 06:02:35 PM PDT 24
Peak memory 194464 kb
Host smart-a24a6595-667b-4fc2-867b-32a36211b211
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879860502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3879860502
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2969151871
Short name T502
Test name
Test status
Simulation time 22175183 ps
CPU time 0.72 seconds
Started Jul 23 06:02:22 PM PDT 24
Finished Jul 23 06:02:24 PM PDT 24
Peak memory 194760 kb
Host smart-3c9fa8a9-43bc-4bae-a8dc-fbc20fd506e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969151871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2969151871
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.820170819
Short name T525
Test name
Test status
Simulation time 599835823 ps
CPU time 3.98 seconds
Started Jul 23 06:02:25 PM PDT 24
Finished Jul 23 06:02:31 PM PDT 24
Peak memory 196396 kb
Host smart-8bd950af-69a8-4768-b32a-d70ee038e388
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820170819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.820170819
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.949505185
Short name T639
Test name
Test status
Simulation time 107504873 ps
CPU time 0.69 seconds
Started Jul 23 06:02:23 PM PDT 24
Finished Jul 23 06:02:26 PM PDT 24
Peak memory 195008 kb
Host smart-26482f90-765d-4348-91a0-aedfc10b2e57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949505185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.949505185
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1276989654
Short name T141
Test name
Test status
Simulation time 70988614 ps
CPU time 0.81 seconds
Started Jul 23 06:02:24 PM PDT 24
Finished Jul 23 06:02:27 PM PDT 24
Peak memory 196084 kb
Host smart-8e0fa2ed-1041-4dba-a8dc-fd0fe4b6cf90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276989654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1276989654
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2810657866
Short name T378
Test name
Test status
Simulation time 28376000 ps
CPU time 1.2 seconds
Started Jul 23 06:02:20 PM PDT 24
Finished Jul 23 06:02:32 PM PDT 24
Peak memory 197860 kb
Host smart-3e4a8e24-2602-4666-bc89-e31dee1dbbc8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810657866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2810657866
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1239514267
Short name T306
Test name
Test status
Simulation time 2948043183 ps
CPU time 3.5 seconds
Started Jul 23 06:02:27 PM PDT 24
Finished Jul 23 06:02:32 PM PDT 24
Peak memory 198576 kb
Host smart-216371fd-9992-42b1-8f00-cce296d8f17c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239514267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1239514267
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3179485413
Short name T514
Test name
Test status
Simulation time 159102341 ps
CPU time 1.06 seconds
Started Jul 23 06:02:25 PM PDT 24
Finished Jul 23 06:02:28 PM PDT 24
Peak memory 197032 kb
Host smart-a5f901d3-1f72-4391-8995-5d4fae47e8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179485413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3179485413
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3553694098
Short name T711
Test name
Test status
Simulation time 48336726 ps
CPU time 1.15 seconds
Started Jul 23 06:02:29 PM PDT 24
Finished Jul 23 06:02:31 PM PDT 24
Peak memory 196272 kb
Host smart-5f57640f-c463-403b-a395-54936b960b87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553694098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3553694098
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3196717611
Short name T645
Test name
Test status
Simulation time 231976437 ps
CPU time 1.49 seconds
Started Jul 23 06:02:36 PM PDT 24
Finished Jul 23 06:02:39 PM PDT 24
Peak memory 198500 kb
Host smart-fc48913e-14d7-47b9-ad62-5284ad75f74c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196717611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3196717611
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2098728127
Short name T44
Test name
Test status
Simulation time 136184268 ps
CPU time 1.07 seconds
Started Jul 23 06:02:21 PM PDT 24
Finished Jul 23 06:02:24 PM PDT 24
Peak memory 196960 kb
Host smart-0f6a233a-00d9-4faa-9a84-67ed9934d15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098728127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2098728127
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3759792216
Short name T429
Test name
Test status
Simulation time 69944061 ps
CPU time 1.25 seconds
Started Jul 23 06:02:21 PM PDT 24
Finished Jul 23 06:02:23 PM PDT 24
Peak memory 198420 kb
Host smart-d2519426-92a7-4929-b862-1b5a61cf0949
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759792216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3759792216
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3592766489
Short name T499
Test name
Test status
Simulation time 7554646376 ps
CPU time 48.09 seconds
Started Jul 23 06:02:22 PM PDT 24
Finished Jul 23 06:03:12 PM PDT 24
Peak memory 198556 kb
Host smart-b8f161c8-eb71-46ba-b698-5c38926d1fe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592766489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3592766489
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.231005356
Short name T182
Test name
Test status
Simulation time 26007447 ps
CPU time 0.62 seconds
Started Jul 23 06:02:31 PM PDT 24
Finished Jul 23 06:02:33 PM PDT 24
Peak memory 195344 kb
Host smart-13dddf54-f6b1-4197-b081-b245f0fa6fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231005356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.231005356
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3475427092
Short name T275
Test name
Test status
Simulation time 21635728 ps
CPU time 0.69 seconds
Started Jul 23 06:02:37 PM PDT 24
Finished Jul 23 06:02:38 PM PDT 24
Peak memory 195336 kb
Host smart-35782a40-5122-4573-a090-42e6e5402624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475427092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3475427092
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.852889694
Short name T153
Test name
Test status
Simulation time 1111353404 ps
CPU time 8.84 seconds
Started Jul 23 06:02:36 PM PDT 24
Finished Jul 23 06:02:45 PM PDT 24
Peak memory 197396 kb
Host smart-58117609-74f9-43c8-8be8-963bb03593da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852889694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.852889694
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3669736913
Short name T599
Test name
Test status
Simulation time 394767703 ps
CPU time 0.76 seconds
Started Jul 23 06:02:46 PM PDT 24
Finished Jul 23 06:02:47 PM PDT 24
Peak memory 196412 kb
Host smart-02ca285a-cf8f-4ac4-bbd0-76fc98797995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669736913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3669736913
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2157697445
Short name T263
Test name
Test status
Simulation time 185891678 ps
CPU time 1.38 seconds
Started Jul 23 06:02:28 PM PDT 24
Finished Jul 23 06:02:31 PM PDT 24
Peak memory 196372 kb
Host smart-6d3d504c-c038-4e86-b0b9-9027da19ce84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157697445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2157697445
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1218170316
Short name T176
Test name
Test status
Simulation time 45410619 ps
CPU time 1.7 seconds
Started Jul 23 06:02:28 PM PDT 24
Finished Jul 23 06:02:31 PM PDT 24
Peak memory 198636 kb
Host smart-9beb4872-fb5a-4c69-9189-973480b0e427
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218170316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1218170316
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1671511059
Short name T563
Test name
Test status
Simulation time 1251261508 ps
CPU time 2.41 seconds
Started Jul 23 06:02:35 PM PDT 24
Finished Jul 23 06:02:38 PM PDT 24
Peak memory 197596 kb
Host smart-439c22c5-44fd-44d7-85c8-3d8901aee80b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671511059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1671511059
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3144948589
Short name T415
Test name
Test status
Simulation time 72948954 ps
CPU time 1.3 seconds
Started Jul 23 06:02:26 PM PDT 24
Finished Jul 23 06:02:29 PM PDT 24
Peak memory 197392 kb
Host smart-4ac09298-10b0-47a2-b0dd-f5de4406fa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144948589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3144948589
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.671978638
Short name T217
Test name
Test status
Simulation time 46810667 ps
CPU time 1.03 seconds
Started Jul 23 06:02:27 PM PDT 24
Finished Jul 23 06:02:29 PM PDT 24
Peak memory 196560 kb
Host smart-a592d833-0d0e-43f2-b789-65941f79ba10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671978638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.671978638
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1693468484
Short name T395
Test name
Test status
Simulation time 179317837 ps
CPU time 2.37 seconds
Started Jul 23 06:02:31 PM PDT 24
Finished Jul 23 06:02:34 PM PDT 24
Peak memory 198468 kb
Host smart-d1667989-1886-44e6-bd36-89b1fbf3b3df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693468484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1693468484
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.341487516
Short name T319
Test name
Test status
Simulation time 131748522 ps
CPU time 1.16 seconds
Started Jul 23 06:02:24 PM PDT 24
Finished Jul 23 06:02:27 PM PDT 24
Peak memory 197016 kb
Host smart-6ecd4e34-fcac-4abf-9bf9-ecd7fcd271f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341487516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.341487516
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2690126270
Short name T146
Test name
Test status
Simulation time 111917036 ps
CPU time 1.18 seconds
Started Jul 23 06:02:29 PM PDT 24
Finished Jul 23 06:02:31 PM PDT 24
Peak memory 196260 kb
Host smart-3ce57958-c6f0-4b62-b855-1e6cc9816f55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690126270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2690126270
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3831585020
Short name T112
Test name
Test status
Simulation time 3310659201 ps
CPU time 87.99 seconds
Started Jul 23 06:02:31 PM PDT 24
Finished Jul 23 06:04:00 PM PDT 24
Peak memory 198584 kb
Host smart-d3b0fe7b-83cd-4971-b7f1-f3fb4541466e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831585020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3831585020
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.109274037
Short name T386
Test name
Test status
Simulation time 77656051 ps
CPU time 0.59 seconds
Started Jul 23 06:02:54 PM PDT 24
Finished Jul 23 06:02:56 PM PDT 24
Peak memory 194584 kb
Host smart-849c44f9-cfd4-4e0c-9e81-941f1b1332ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109274037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.109274037
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1908018198
Short name T437
Test name
Test status
Simulation time 108587734 ps
CPU time 0.8 seconds
Started Jul 23 06:02:27 PM PDT 24
Finished Jul 23 06:02:29 PM PDT 24
Peak memory 195848 kb
Host smart-9a355e3b-96d7-443e-bc5c-1ba373e6190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908018198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1908018198
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3853488685
Short name T566
Test name
Test status
Simulation time 868938655 ps
CPU time 23.35 seconds
Started Jul 23 06:02:38 PM PDT 24
Finished Jul 23 06:03:02 PM PDT 24
Peak memory 196984 kb
Host smart-0b955cb5-fe7f-4afe-beab-a190059f8a70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853488685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3853488685
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2108629219
Short name T258
Test name
Test status
Simulation time 388768018 ps
CPU time 0.81 seconds
Started Jul 23 06:02:47 PM PDT 24
Finished Jul 23 06:02:49 PM PDT 24
Peak memory 196260 kb
Host smart-1a74807a-ec51-49ae-8c9c-81a7b5e4777f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108629219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2108629219
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.4252580109
Short name T359
Test name
Test status
Simulation time 32200074 ps
CPU time 0.74 seconds
Started Jul 23 06:02:30 PM PDT 24
Finished Jul 23 06:02:32 PM PDT 24
Peak memory 196720 kb
Host smart-157d5074-0117-46eb-b9c1-1e6210c16097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252580109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.4252580109
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1014753623
Short name T282
Test name
Test status
Simulation time 320857254 ps
CPU time 3.33 seconds
Started Jul 23 06:02:45 PM PDT 24
Finished Jul 23 06:02:49 PM PDT 24
Peak memory 198712 kb
Host smart-e4ed0cff-e064-498d-8aaf-d09b2d9900b5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014753623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1014753623
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3659928191
Short name T567
Test name
Test status
Simulation time 148009623 ps
CPU time 1.84 seconds
Started Jul 23 06:02:29 PM PDT 24
Finished Jul 23 06:02:32 PM PDT 24
Peak memory 196348 kb
Host smart-80537042-fe00-4a88-89e7-55ac04a46398
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659928191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3659928191
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.301961726
Short name T311
Test name
Test status
Simulation time 56740724 ps
CPU time 1.13 seconds
Started Jul 23 06:02:57 PM PDT 24
Finished Jul 23 06:02:59 PM PDT 24
Peak memory 196608 kb
Host smart-09a22b86-8e9e-4fd1-823b-018779d072a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301961726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.301961726
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.723405785
Short name T154
Test name
Test status
Simulation time 68282433 ps
CPU time 1.19 seconds
Started Jul 23 06:02:44 PM PDT 24
Finished Jul 23 06:02:46 PM PDT 24
Peak memory 197552 kb
Host smart-bf96000e-9fa0-47fa-b4cb-ea7840f2a853
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723405785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.723405785
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1380842985
Short name T226
Test name
Test status
Simulation time 2267307028 ps
CPU time 3.45 seconds
Started Jul 23 06:02:29 PM PDT 24
Finished Jul 23 06:02:33 PM PDT 24
Peak memory 198488 kb
Host smart-ddd9d9a1-7fa0-4c5d-9a35-e69bfa95129f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380842985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1380842985
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1118496308
Short name T327
Test name
Test status
Simulation time 292793183 ps
CPU time 1.32 seconds
Started Jul 23 06:02:51 PM PDT 24
Finished Jul 23 06:02:53 PM PDT 24
Peak memory 197240 kb
Host smart-27b4fdd5-9c99-426b-8df6-8dbb5b857d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118496308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1118496308
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2577137485
Short name T92
Test name
Test status
Simulation time 257646397 ps
CPU time 1.18 seconds
Started Jul 23 06:02:29 PM PDT 24
Finished Jul 23 06:02:31 PM PDT 24
Peak memory 196256 kb
Host smart-15a07c8f-1f66-4c73-b063-8df96c00b422
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577137485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2577137485
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1945559963
Short name T299
Test name
Test status
Simulation time 18901802691 ps
CPU time 63.87 seconds
Started Jul 23 06:02:28 PM PDT 24
Finished Jul 23 06:03:33 PM PDT 24
Peak memory 198620 kb
Host smart-1e4389f8-014e-4412-93ee-8f59c802b6fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945559963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1945559963
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1725606233
Short name T52
Test name
Test status
Simulation time 62174123348 ps
CPU time 235.71 seconds
Started Jul 23 06:02:48 PM PDT 24
Finished Jul 23 06:06:45 PM PDT 24
Peak memory 198688 kb
Host smart-35da4698-c52b-4409-a8d2-4913340ff541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1725606233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1725606233
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.4121223358
Short name T420
Test name
Test status
Simulation time 12747846 ps
CPU time 0.58 seconds
Started Jul 23 06:01:24 PM PDT 24
Finished Jul 23 06:01:25 PM PDT 24
Peak memory 194456 kb
Host smart-19c790b6-9f77-42c2-8b8f-21297367c21d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121223358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.4121223358
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1570536044
Short name T587
Test name
Test status
Simulation time 61182385 ps
CPU time 0.82 seconds
Started Jul 23 06:01:28 PM PDT 24
Finished Jul 23 06:01:29 PM PDT 24
Peak memory 195888 kb
Host smart-c06fd1b8-51fb-45ae-babf-ef96c338a03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570536044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1570536044
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.354878900
Short name T26
Test name
Test status
Simulation time 692161276 ps
CPU time 19.36 seconds
Started Jul 23 06:01:28 PM PDT 24
Finished Jul 23 06:01:49 PM PDT 24
Peak memory 197408 kb
Host smart-3df7884c-9e99-4ded-813c-d080ec87585b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354878900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.354878900
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1302020042
Short name T300
Test name
Test status
Simulation time 62481254 ps
CPU time 0.6 seconds
Started Jul 23 06:01:27 PM PDT 24
Finished Jul 23 06:01:28 PM PDT 24
Peak memory 194940 kb
Host smart-cd427c76-a999-4d72-8f6a-e3b4252af669
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302020042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1302020042
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2375856238
Short name T609
Test name
Test status
Simulation time 305871846 ps
CPU time 1.37 seconds
Started Jul 23 06:01:26 PM PDT 24
Finished Jul 23 06:01:28 PM PDT 24
Peak memory 197304 kb
Host smart-2357cf5b-efdf-4426-b9b2-9e97abdb6749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375856238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2375856238
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1652940261
Short name T569
Test name
Test status
Simulation time 354340099 ps
CPU time 1.48 seconds
Started Jul 23 06:01:29 PM PDT 24
Finished Jul 23 06:01:31 PM PDT 24
Peak memory 197380 kb
Host smart-2ac1e565-8f7e-4846-baa6-8439313ea2de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652940261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1652940261
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1398488137
Short name T392
Test name
Test status
Simulation time 76211344 ps
CPU time 1.49 seconds
Started Jul 23 06:01:31 PM PDT 24
Finished Jul 23 06:01:34 PM PDT 24
Peak memory 196364 kb
Host smart-58c0b0a2-dc65-4d3c-ba53-02e418edc63a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398488137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1398488137
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2521234203
Short name T544
Test name
Test status
Simulation time 54275619 ps
CPU time 1.13 seconds
Started Jul 23 06:01:23 PM PDT 24
Finished Jul 23 06:01:25 PM PDT 24
Peak memory 196364 kb
Host smart-18c413b6-05ff-46e0-9ad4-1aa62b1e338f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521234203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2521234203
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1405584865
Short name T688
Test name
Test status
Simulation time 70106149 ps
CPU time 1.43 seconds
Started Jul 23 06:01:23 PM PDT 24
Finished Jul 23 06:01:25 PM PDT 24
Peak memory 197468 kb
Host smart-18902fb1-467e-4a2f-a9d8-63d9244a191b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405584865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1405584865
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.491942367
Short name T169
Test name
Test status
Simulation time 1920893757 ps
CPU time 5.05 seconds
Started Jul 23 06:01:36 PM PDT 24
Finished Jul 23 06:01:42 PM PDT 24
Peak memory 198544 kb
Host smart-fcb240fb-e82e-4d11-8bb7-11274c75fe28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491942367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.491942367
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.563705312
Short name T105
Test name
Test status
Simulation time 133123390 ps
CPU time 1.01 seconds
Started Jul 23 06:01:27 PM PDT 24
Finished Jul 23 06:01:29 PM PDT 24
Peak memory 196216 kb
Host smart-31a10830-9db5-4a4a-995c-1c54bfd83a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563705312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.563705312
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2312738419
Short name T407
Test name
Test status
Simulation time 44754400 ps
CPU time 1.01 seconds
Started Jul 23 06:01:17 PM PDT 24
Finished Jul 23 06:01:19 PM PDT 24
Peak memory 197032 kb
Host smart-cb8b60c3-3e35-43f6-9239-7aa4532e75e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312738419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2312738419
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1314690559
Short name T286
Test name
Test status
Simulation time 4622233016 ps
CPU time 44.41 seconds
Started Jul 23 06:01:36 PM PDT 24
Finished Jul 23 06:02:22 PM PDT 24
Peak memory 198680 kb
Host smart-94d98220-ad67-4aa8-b651-dcb96c386895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314690559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1314690559
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.2387825579
Short name T86
Test name
Test status
Simulation time 26822162662 ps
CPU time 747.89 seconds
Started Jul 23 06:01:22 PM PDT 24
Finished Jul 23 06:13:51 PM PDT 24
Peak memory 198772 kb
Host smart-5e0ccac8-6cab-4ff0-b355-48412ef9523e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2387825579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.2387825579
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1028890988
Short name T224
Test name
Test status
Simulation time 24049929 ps
CPU time 0.57 seconds
Started Jul 23 06:02:34 PM PDT 24
Finished Jul 23 06:02:36 PM PDT 24
Peak memory 194460 kb
Host smart-3c9ce6b8-e46f-44a8-a6d0-7d8934ac6b17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028890988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1028890988
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.798318339
Short name T292
Test name
Test status
Simulation time 43512820 ps
CPU time 0.87 seconds
Started Jul 23 06:02:45 PM PDT 24
Finished Jul 23 06:02:46 PM PDT 24
Peak memory 196728 kb
Host smart-bd640509-6f87-4494-89ab-3e36def82fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798318339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.798318339
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.147719312
Short name T469
Test name
Test status
Simulation time 503485728 ps
CPU time 26.87 seconds
Started Jul 23 06:02:30 PM PDT 24
Finished Jul 23 06:02:58 PM PDT 24
Peak memory 197452 kb
Host smart-25b65c5b-61a2-4eec-b757-2304278c649a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147719312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.147719312
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1234049528
Short name T422
Test name
Test status
Simulation time 67828836 ps
CPU time 0.92 seconds
Started Jul 23 06:02:43 PM PDT 24
Finished Jul 23 06:02:45 PM PDT 24
Peak memory 197684 kb
Host smart-c37dd4ee-4714-4ebc-9e10-26ab6151c8af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234049528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1234049528
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1836719661
Short name T458
Test name
Test status
Simulation time 167034193 ps
CPU time 0.89 seconds
Started Jul 23 06:02:34 PM PDT 24
Finished Jul 23 06:02:36 PM PDT 24
Peak memory 197968 kb
Host smart-c038f8ff-5555-4518-9be3-4cef38732bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836719661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1836719661
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.4090917352
Short name T560
Test name
Test status
Simulation time 21430220 ps
CPU time 0.96 seconds
Started Jul 23 06:02:49 PM PDT 24
Finished Jul 23 06:02:51 PM PDT 24
Peak memory 196724 kb
Host smart-71848044-3656-479a-b103-d5e45d810837
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090917352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.4090917352
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.2643824682
Short name T288
Test name
Test status
Simulation time 273431502 ps
CPU time 2.13 seconds
Started Jul 23 06:02:49 PM PDT 24
Finished Jul 23 06:02:52 PM PDT 24
Peak memory 196292 kb
Host smart-37a7066e-898d-4c75-92a1-e4e958db3513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643824682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.2643824682
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1135985302
Short name T244
Test name
Test status
Simulation time 53620802 ps
CPU time 1.12 seconds
Started Jul 23 06:02:26 PM PDT 24
Finished Jul 23 06:02:28 PM PDT 24
Peak memory 197360 kb
Host smart-24616cc3-858e-4081-ae17-fd46cfe3361d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135985302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1135985302
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.4186828655
Short name T504
Test name
Test status
Simulation time 45914789 ps
CPU time 1.06 seconds
Started Jul 23 06:02:43 PM PDT 24
Finished Jul 23 06:02:55 PM PDT 24
Peak memory 196536 kb
Host smart-e6bd81b9-3c88-4e10-9eee-52f45f4560a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186828655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.4186828655
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.639652722
Short name T496
Test name
Test status
Simulation time 313184131 ps
CPU time 1.98 seconds
Started Jul 23 06:02:47 PM PDT 24
Finished Jul 23 06:02:50 PM PDT 24
Peak memory 198524 kb
Host smart-005db4ad-d72b-461e-8866-726a7c75a4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639652722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.639652722
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1680240860
Short name T661
Test name
Test status
Simulation time 89890229 ps
CPU time 1.03 seconds
Started Jul 23 06:02:26 PM PDT 24
Finished Jul 23 06:02:28 PM PDT 24
Peak memory 197796 kb
Host smart-6a125103-87c4-4bec-ab33-834eddfa2945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680240860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1680240860
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2160258578
Short name T577
Test name
Test status
Simulation time 94742458 ps
CPU time 1 seconds
Started Jul 23 06:02:40 PM PDT 24
Finished Jul 23 06:02:41 PM PDT 24
Peak memory 196104 kb
Host smart-027729ac-a904-4bc5-868e-408a6e51ab77
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160258578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2160258578
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.4032809647
Short name T696
Test name
Test status
Simulation time 9872569919 ps
CPU time 133.79 seconds
Started Jul 23 06:02:48 PM PDT 24
Finished Jul 23 06:05:03 PM PDT 24
Peak memory 198620 kb
Host smart-1b07bb1b-3d9e-44d6-8880-2a9e9539798d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032809647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.4032809647
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1901373081
Short name T195
Test name
Test status
Simulation time 13366042 ps
CPU time 0.58 seconds
Started Jul 23 06:02:46 PM PDT 24
Finished Jul 23 06:02:47 PM PDT 24
Peak memory 194648 kb
Host smart-2212138b-b0d6-4990-997d-ce647930886d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901373081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1901373081
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3708558340
Short name T435
Test name
Test status
Simulation time 36987891 ps
CPU time 0.8 seconds
Started Jul 23 06:02:41 PM PDT 24
Finished Jul 23 06:02:42 PM PDT 24
Peak memory 195764 kb
Host smart-692b8511-919b-4a38-a0ed-85707c482d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708558340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3708558340
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.4036802786
Short name T333
Test name
Test status
Simulation time 7715977553 ps
CPU time 23.37 seconds
Started Jul 23 06:02:41 PM PDT 24
Finished Jul 23 06:03:10 PM PDT 24
Peak memory 198504 kb
Host smart-e6b9e397-26e9-4802-a250-0320d2776816
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036802786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.4036802786
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3610823007
Short name T174
Test name
Test status
Simulation time 51018783 ps
CPU time 0.79 seconds
Started Jul 23 06:02:53 PM PDT 24
Finished Jul 23 06:02:54 PM PDT 24
Peak memory 196344 kb
Host smart-a39a56eb-2826-4d80-84da-6c0d6ad681bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610823007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3610823007
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2928904133
Short name T418
Test name
Test status
Simulation time 28371389 ps
CPU time 0.96 seconds
Started Jul 23 06:02:43 PM PDT 24
Finished Jul 23 06:02:45 PM PDT 24
Peak memory 196424 kb
Host smart-02cd33f5-5fc1-418d-890f-1e3489b0f2eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928904133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2928904133
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3944412770
Short name T589
Test name
Test status
Simulation time 39499968 ps
CPU time 1.45 seconds
Started Jul 23 06:02:55 PM PDT 24
Finished Jul 23 06:02:57 PM PDT 24
Peak memory 197128 kb
Host smart-1d2848b0-8391-4265-be29-91ac93ec8da4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944412770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3944412770
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3278425316
Short name T261
Test name
Test status
Simulation time 54380240 ps
CPU time 1.12 seconds
Started Jul 23 06:02:43 PM PDT 24
Finished Jul 23 06:02:44 PM PDT 24
Peak memory 196136 kb
Host smart-d5c302fb-023c-430a-9e6a-2dcd6fc3dff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278425316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3278425316
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.33678726
Short name T132
Test name
Test status
Simulation time 21187483 ps
CPU time 0.75 seconds
Started Jul 23 06:02:43 PM PDT 24
Finished Jul 23 06:02:45 PM PDT 24
Peak memory 196048 kb
Host smart-28424087-e2b2-4ef0-87a3-b85a0579636b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33678726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.33678726
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.4186519974
Short name T121
Test name
Test status
Simulation time 109263460 ps
CPU time 1.37 seconds
Started Jul 23 06:02:47 PM PDT 24
Finished Jul 23 06:02:49 PM PDT 24
Peak memory 197432 kb
Host smart-600742e1-3b88-4426-8931-7c33e89d404b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186519974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.4186519974
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3428895183
Short name T9
Test name
Test status
Simulation time 192724780 ps
CPU time 2.42 seconds
Started Jul 23 06:02:44 PM PDT 24
Finished Jul 23 06:02:47 PM PDT 24
Peak memory 198304 kb
Host smart-75deb67f-d3d0-40d6-9a0e-aa55aaecba66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428895183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3428895183
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2618891445
Short name T633
Test name
Test status
Simulation time 138753227 ps
CPU time 1.14 seconds
Started Jul 23 06:02:56 PM PDT 24
Finished Jul 23 06:02:59 PM PDT 24
Peak memory 196376 kb
Host smart-b58d6054-3008-473a-a96b-eb5e7d84843b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618891445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2618891445
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.717024138
Short name T598
Test name
Test status
Simulation time 257624758 ps
CPU time 1.08 seconds
Started Jul 23 06:02:31 PM PDT 24
Finished Jul 23 06:02:32 PM PDT 24
Peak memory 196056 kb
Host smart-f48b658a-310b-4c41-9c22-ecd9dc313f56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717024138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.717024138
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3278267986
Short name T3
Test name
Test status
Simulation time 17545704423 ps
CPU time 45.12 seconds
Started Jul 23 06:02:52 PM PDT 24
Finished Jul 23 06:03:37 PM PDT 24
Peak memory 198608 kb
Host smart-c9136c0b-a09a-4b04-b7da-63cbcf8aaf41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278267986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3278267986
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.694225763
Short name T434
Test name
Test status
Simulation time 43484764 ps
CPU time 0.55 seconds
Started Jul 23 06:02:44 PM PDT 24
Finished Jul 23 06:02:46 PM PDT 24
Peak memory 195076 kb
Host smart-2a14c092-3ba6-46e3-840f-ad073999590d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694225763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.694225763
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1748322107
Short name T338
Test name
Test status
Simulation time 21786774 ps
CPU time 0.7 seconds
Started Jul 23 06:02:52 PM PDT 24
Finished Jul 23 06:02:53 PM PDT 24
Peak memory 194596 kb
Host smart-5266c3f0-5acb-4f75-97a8-c05ef0de8704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748322107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1748322107
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3345279339
Short name T250
Test name
Test status
Simulation time 5701156897 ps
CPU time 15.23 seconds
Started Jul 23 06:02:45 PM PDT 24
Finished Jul 23 06:03:01 PM PDT 24
Peak memory 197096 kb
Host smart-658d2c56-e206-46f0-b737-ef0cc257ea7d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345279339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3345279339
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3761180798
Short name T681
Test name
Test status
Simulation time 131839764 ps
CPU time 0.75 seconds
Started Jul 23 06:02:43 PM PDT 24
Finished Jul 23 06:02:45 PM PDT 24
Peak memory 195968 kb
Host smart-a70cb449-0a72-463f-8a52-02f1ae5f7a56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761180798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3761180798
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1294454166
Short name T47
Test name
Test status
Simulation time 216465332 ps
CPU time 1.36 seconds
Started Jul 23 06:02:54 PM PDT 24
Finished Jul 23 06:02:57 PM PDT 24
Peak memory 196304 kb
Host smart-45d236ad-0c63-43a6-8909-c65d5804a411
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294454166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1294454166
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.246286501
Short name T200
Test name
Test status
Simulation time 58713226 ps
CPU time 2.33 seconds
Started Jul 23 06:02:49 PM PDT 24
Finished Jul 23 06:02:58 PM PDT 24
Peak memory 198472 kb
Host smart-afd69928-c95b-4626-ac86-c2062bad82a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246286501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.246286501
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3407602458
Short name T655
Test name
Test status
Simulation time 119817090 ps
CPU time 3.44 seconds
Started Jul 23 06:02:54 PM PDT 24
Finished Jul 23 06:03:03 PM PDT 24
Peak memory 197596 kb
Host smart-9a7ee154-5bc3-462c-a827-8c9ab99e978a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407602458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3407602458
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.69239788
Short name T88
Test name
Test status
Simulation time 31772913 ps
CPU time 1.12 seconds
Started Jul 23 06:02:54 PM PDT 24
Finished Jul 23 06:02:56 PM PDT 24
Peak memory 196356 kb
Host smart-1015edea-2e73-474a-a7ed-41b7a8285998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69239788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.69239788
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.4082743704
Short name T119
Test name
Test status
Simulation time 104438619 ps
CPU time 1.01 seconds
Started Jul 23 06:02:55 PM PDT 24
Finished Jul 23 06:02:57 PM PDT 24
Peak memory 196480 kb
Host smart-f4666c58-3396-4a6f-8dc4-9e7504703dae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082743704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.4082743704
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3774208646
Short name T179
Test name
Test status
Simulation time 392292432 ps
CPU time 4.93 seconds
Started Jul 23 06:03:00 PM PDT 24
Finished Jul 23 06:03:06 PM PDT 24
Peak memory 198456 kb
Host smart-b3b7c7c8-2526-4934-bff5-0fa6c0757c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774208646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3774208646
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1936695964
Short name T189
Test name
Test status
Simulation time 361850671 ps
CPU time 1.48 seconds
Started Jul 23 06:02:51 PM PDT 24
Finished Jul 23 06:02:53 PM PDT 24
Peak memory 196084 kb
Host smart-5ce8ad7c-9893-4916-b206-b38aba7d1082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936695964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1936695964
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2954413497
Short name T493
Test name
Test status
Simulation time 54917367 ps
CPU time 1.16 seconds
Started Jul 23 06:02:44 PM PDT 24
Finished Jul 23 06:02:46 PM PDT 24
Peak memory 196108 kb
Host smart-d2fb39e9-fab1-4d44-b866-1afa2cc46b97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954413497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2954413497
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.952152105
Short name T138
Test name
Test status
Simulation time 3262627613 ps
CPU time 82.66 seconds
Started Jul 23 06:02:56 PM PDT 24
Finished Jul 23 06:04:19 PM PDT 24
Peak memory 198608 kb
Host smart-eb4123b2-fdb2-4fe1-8a74-46e16201788f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952152105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.952152105
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.996489578
Short name T658
Test name
Test status
Simulation time 46099227958 ps
CPU time 1271.46 seconds
Started Jul 23 06:02:50 PM PDT 24
Finished Jul 23 06:24:02 PM PDT 24
Peak memory 198820 kb
Host smart-b3625257-bcde-48a2-adc4-a11cd974cffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=996489578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.996489578
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2887329718
Short name T372
Test name
Test status
Simulation time 13520182 ps
CPU time 0.59 seconds
Started Jul 23 06:02:57 PM PDT 24
Finished Jul 23 06:02:58 PM PDT 24
Peak memory 194648 kb
Host smart-d88f820c-ccac-4599-b847-c42f98f775aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887329718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2887329718
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2734605858
Short name T322
Test name
Test status
Simulation time 45879205 ps
CPU time 0.77 seconds
Started Jul 23 06:03:02 PM PDT 24
Finished Jul 23 06:03:04 PM PDT 24
Peak memory 196508 kb
Host smart-1a0d0017-c8df-41de-bde9-2e113d3c85bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734605858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2734605858
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2760284357
Short name T444
Test name
Test status
Simulation time 1577977960 ps
CPU time 23.79 seconds
Started Jul 23 06:02:54 PM PDT 24
Finished Jul 23 06:03:24 PM PDT 24
Peak memory 196824 kb
Host smart-d02b1e73-5598-4d73-8c03-4aff0f8fe329
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760284357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2760284357
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1086532030
Short name T318
Test name
Test status
Simulation time 66082740 ps
CPU time 0.93 seconds
Started Jul 23 06:03:12 PM PDT 24
Finished Jul 23 06:03:19 PM PDT 24
Peak memory 197508 kb
Host smart-26030afd-08ed-4652-9a9f-93da34e19a87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086532030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1086532030
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2094756397
Short name T506
Test name
Test status
Simulation time 81462701 ps
CPU time 1.22 seconds
Started Jul 23 06:03:02 PM PDT 24
Finished Jul 23 06:03:04 PM PDT 24
Peak memory 197356 kb
Host smart-be3e8210-21c8-4e39-97fb-0f2d0fab88fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094756397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2094756397
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2610528977
Short name T491
Test name
Test status
Simulation time 74646833 ps
CPU time 2.97 seconds
Started Jul 23 06:03:00 PM PDT 24
Finished Jul 23 06:03:04 PM PDT 24
Peak memory 197004 kb
Host smart-51acedda-074b-4651-9d3c-a400036cd60a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610528977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2610528977
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1036877213
Short name T208
Test name
Test status
Simulation time 74536332 ps
CPU time 1.74 seconds
Started Jul 23 06:03:03 PM PDT 24
Finished Jul 23 06:03:07 PM PDT 24
Peak memory 197120 kb
Host smart-015d2d13-ebfb-4000-a44f-13a3051506c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036877213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1036877213
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.973126550
Short name T573
Test name
Test status
Simulation time 147068184 ps
CPU time 1.01 seconds
Started Jul 23 06:03:00 PM PDT 24
Finished Jul 23 06:03:02 PM PDT 24
Peak memory 196540 kb
Host smart-bb567cd9-da2a-42eb-9644-7698caee2ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973126550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.973126550
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4103131958
Short name T302
Test name
Test status
Simulation time 267168609 ps
CPU time 1.41 seconds
Started Jul 23 06:02:53 PM PDT 24
Finished Jul 23 06:02:55 PM PDT 24
Peak memory 197488 kb
Host smart-1ee53de0-4200-4893-a155-74eb78e1b44b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103131958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.4103131958
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2193070243
Short name T575
Test name
Test status
Simulation time 3133579282 ps
CPU time 3.97 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:22 PM PDT 24
Peak memory 198584 kb
Host smart-eccbc5f5-081b-4c50-a1d4-87e3c2d95757
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193070243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2193070243
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3218980740
Short name T277
Test name
Test status
Simulation time 73387967 ps
CPU time 1.26 seconds
Started Jul 23 06:02:43 PM PDT 24
Finished Jul 23 06:02:45 PM PDT 24
Peak memory 196264 kb
Host smart-ba94a60d-71b5-49ac-bb17-fe5f2a7f0f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218980740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3218980740
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.4281449169
Short name T427
Test name
Test status
Simulation time 96939512 ps
CPU time 1.51 seconds
Started Jul 23 06:02:46 PM PDT 24
Finished Jul 23 06:02:49 PM PDT 24
Peak memory 197244 kb
Host smart-e70a810c-e183-424b-bd42-6407897799c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281449169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.4281449169
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3410220451
Short name T4
Test name
Test status
Simulation time 24230427996 ps
CPU time 141.15 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:05:35 PM PDT 24
Peak memory 198640 kb
Host smart-876f8ad2-0938-456b-b52f-058d204ff6d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410220451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3410220451
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1127355810
Short name T53
Test name
Test status
Simulation time 29026801209 ps
CPU time 431.03 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:10:28 PM PDT 24
Peak memory 198792 kb
Host smart-1c494255-12ab-48c2-b97f-e74f81421bff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1127355810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1127355810
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.4212513582
Short name T638
Test name
Test status
Simulation time 15013073 ps
CPU time 0.59 seconds
Started Jul 23 06:03:10 PM PDT 24
Finished Jul 23 06:03:12 PM PDT 24
Peak memory 194660 kb
Host smart-24700e59-9323-47db-8aa7-a6f3116a9659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212513582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4212513582
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.625330324
Short name T363
Test name
Test status
Simulation time 91129665 ps
CPU time 0.93 seconds
Started Jul 23 06:03:04 PM PDT 24
Finished Jul 23 06:03:07 PM PDT 24
Peak memory 196980 kb
Host smart-fec65257-f651-43d1-8f7c-951a67d416b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625330324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.625330324
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2192168508
Short name T568
Test name
Test status
Simulation time 1924490705 ps
CPU time 24.21 seconds
Started Jul 23 06:03:10 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 197288 kb
Host smart-e6de39b2-5c5a-46ce-9ca3-d12cd7deda5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192168508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2192168508
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3718071324
Short name T559
Test name
Test status
Simulation time 423087503 ps
CPU time 0.93 seconds
Started Jul 23 06:03:14 PM PDT 24
Finished Jul 23 06:03:16 PM PDT 24
Peak memory 198308 kb
Host smart-911b1bea-cf67-4310-aaac-dde27b743f5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718071324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3718071324
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1734377439
Short name T687
Test name
Test status
Simulation time 71773039 ps
CPU time 1.25 seconds
Started Jul 23 06:03:02 PM PDT 24
Finished Jul 23 06:03:05 PM PDT 24
Peak memory 196356 kb
Host smart-c56bc3bc-45a4-41aa-9dc4-39059038b076
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734377439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1734377439
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.192432258
Short name T679
Test name
Test status
Simulation time 290968119 ps
CPU time 3.34 seconds
Started Jul 23 06:03:05 PM PDT 24
Finished Jul 23 06:03:10 PM PDT 24
Peak memory 197188 kb
Host smart-9e449ee9-7e17-4080-ae42-ef381949c425
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192432258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.192432258
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.4068987557
Short name T413
Test name
Test status
Simulation time 94922670 ps
CPU time 1.47 seconds
Started Jul 23 06:03:05 PM PDT 24
Finished Jul 23 06:03:08 PM PDT 24
Peak memory 196332 kb
Host smart-a2c5ed35-90cc-4fb1-9feb-d51cdd46f21e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068987557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.4068987557
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2401299519
Short name T50
Test name
Test status
Simulation time 131592980 ps
CPU time 1.17 seconds
Started Jul 23 06:03:17 PM PDT 24
Finished Jul 23 06:03:20 PM PDT 24
Peak memory 197852 kb
Host smart-c9781e66-4c92-4179-800e-072010df66b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401299519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2401299519
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.3576880435
Short name T255
Test name
Test status
Simulation time 84195230 ps
CPU time 0.95 seconds
Started Jul 23 06:03:14 PM PDT 24
Finished Jul 23 06:03:15 PM PDT 24
Peak memory 197288 kb
Host smart-56d89f4b-f469-4af9-b883-f35cafcc7d29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576880435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.3576880435
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4220853810
Short name T509
Test name
Test status
Simulation time 203029101 ps
CPU time 2.41 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:03:16 PM PDT 24
Peak memory 198516 kb
Host smart-4bd7c5bf-6fcd-4f41-805f-f3a2513661c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220853810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4220853810
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1222604948
Short name T343
Test name
Test status
Simulation time 55217953 ps
CPU time 0.72 seconds
Started Jul 23 06:03:03 PM PDT 24
Finished Jul 23 06:03:05 PM PDT 24
Peak memory 195392 kb
Host smart-5552044b-aea3-4af7-b657-7806657cf996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222604948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1222604948
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1835616435
Short name T207
Test name
Test status
Simulation time 288084958 ps
CPU time 1.19 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:18 PM PDT 24
Peak memory 196304 kb
Host smart-4e205be1-9e91-4f0a-911d-db770d74be57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835616435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1835616435
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2576051979
Short name T384
Test name
Test status
Simulation time 11401823004 ps
CPU time 28.94 seconds
Started Jul 23 06:03:06 PM PDT 24
Finished Jul 23 06:03:36 PM PDT 24
Peak memory 198636 kb
Host smart-980f1548-afd7-4664-8dc3-475f02b6cd68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576051979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2576051979
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1773302599
Short name T576
Test name
Test status
Simulation time 14918734 ps
CPU time 0.58 seconds
Started Jul 23 06:03:10 PM PDT 24
Finished Jul 23 06:03:12 PM PDT 24
Peak memory 195140 kb
Host smart-b17c7f10-ca8e-4500-b447-862fe101d884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773302599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1773302599
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.996246129
Short name T402
Test name
Test status
Simulation time 16707367 ps
CPU time 0.68 seconds
Started Jul 23 06:03:02 PM PDT 24
Finished Jul 23 06:03:04 PM PDT 24
Peak memory 195296 kb
Host smart-c8e8d500-4a71-438d-9a00-c29605cbdc51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996246129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.996246129
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3969479197
Short name T664
Test name
Test status
Simulation time 912976002 ps
CPU time 7.57 seconds
Started Jul 23 06:03:15 PM PDT 24
Finished Jul 23 06:03:24 PM PDT 24
Peak memory 198516 kb
Host smart-48034986-46ec-45fc-9a4c-207e3bb7bd87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969479197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3969479197
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2498728687
Short name T649
Test name
Test status
Simulation time 80220289 ps
CPU time 0.76 seconds
Started Jul 23 06:03:10 PM PDT 24
Finished Jul 23 06:03:11 PM PDT 24
Peak memory 196500 kb
Host smart-936edaaf-a847-409e-8a3c-065d4531524f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498728687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2498728687
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2219811772
Short name T329
Test name
Test status
Simulation time 54523944 ps
CPU time 1.31 seconds
Started Jul 23 06:03:12 PM PDT 24
Finished Jul 23 06:03:14 PM PDT 24
Peak memory 197608 kb
Host smart-5a3d7205-cc67-48da-b52c-c07cf0bc6549
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219811772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2219811772
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2056354714
Short name T519
Test name
Test status
Simulation time 170203450 ps
CPU time 3.62 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:21 PM PDT 24
Peak memory 198632 kb
Host smart-e2bf23f6-ec45-4e3e-a70d-c26fe40c94aa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056354714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2056354714
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.132815064
Short name T482
Test name
Test status
Simulation time 371940432 ps
CPU time 3.11 seconds
Started Jul 23 06:03:14 PM PDT 24
Finished Jul 23 06:03:18 PM PDT 24
Peak memory 197676 kb
Host smart-e66bd805-5500-4e18-a99f-69e1f5beb657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132815064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
132815064
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.100187413
Short name T291
Test name
Test status
Simulation time 23528104 ps
CPU time 0.71 seconds
Started Jul 23 06:03:18 PM PDT 24
Finished Jul 23 06:03:20 PM PDT 24
Peak memory 194796 kb
Host smart-050a54f2-af8f-44e0-a588-f0d16bc5fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100187413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.100187413
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.965253688
Short name T232
Test name
Test status
Simulation time 22480923 ps
CPU time 0.8 seconds
Started Jul 23 06:03:15 PM PDT 24
Finished Jul 23 06:03:17 PM PDT 24
Peak memory 197148 kb
Host smart-fcbba411-433c-4578-8738-9a7dbe97416e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965253688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.965253688
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3267482050
Short name T106
Test name
Test status
Simulation time 255113727 ps
CPU time 2.32 seconds
Started Jul 23 06:03:09 PM PDT 24
Finished Jul 23 06:03:12 PM PDT 24
Peak memory 198508 kb
Host smart-b30cf95b-df8c-4019-a243-64e6750062f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267482050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3267482050
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2730070690
Short name T213
Test name
Test status
Simulation time 163037587 ps
CPU time 1.31 seconds
Started Jul 23 06:03:05 PM PDT 24
Finished Jul 23 06:03:08 PM PDT 24
Peak memory 197260 kb
Host smart-c761bb4c-371a-445f-aca9-16f4a4314daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730070690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2730070690
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2666961776
Short name T556
Test name
Test status
Simulation time 61163348 ps
CPU time 1.19 seconds
Started Jul 23 06:03:05 PM PDT 24
Finished Jul 23 06:03:08 PM PDT 24
Peak memory 195944 kb
Host smart-2700cd0e-6380-4ead-9d42-21e5c616eb34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666961776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2666961776
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3234492893
Short name T487
Test name
Test status
Simulation time 3152082940 ps
CPU time 91.37 seconds
Started Jul 23 06:03:08 PM PDT 24
Finished Jul 23 06:04:40 PM PDT 24
Peak memory 198672 kb
Host smart-62347d63-8c8a-4046-96d8-b2997916126f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234492893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3234492893
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2283648947
Short name T430
Test name
Test status
Simulation time 58853056422 ps
CPU time 658.11 seconds
Started Jul 23 06:03:12 PM PDT 24
Finished Jul 23 06:14:11 PM PDT 24
Peak memory 198740 kb
Host smart-4dffdbe1-284b-4b0d-a7db-0a2787823f77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2283648947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2283648947
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.205995129
Short name T313
Test name
Test status
Simulation time 14239472 ps
CPU time 0.58 seconds
Started Jul 23 06:03:17 PM PDT 24
Finished Jul 23 06:03:19 PM PDT 24
Peak memory 194452 kb
Host smart-d42fcb08-ee4d-4bf8-861b-a5fff6bbf249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205995129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.205995129
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.209981720
Short name T310
Test name
Test status
Simulation time 241465429 ps
CPU time 0.85 seconds
Started Jul 23 06:03:11 PM PDT 24
Finished Jul 23 06:03:12 PM PDT 24
Peak memory 195824 kb
Host smart-f03c2857-81ae-4485-84ae-dbc0e9478069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209981720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.209981720
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1585773722
Short name T520
Test name
Test status
Simulation time 1020128576 ps
CPU time 7.25 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:25 PM PDT 24
Peak memory 197532 kb
Host smart-a1d40fbc-f583-4c28-b645-ba5ff924a767
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585773722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1585773722
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.154438143
Short name T371
Test name
Test status
Simulation time 140670274 ps
CPU time 0.79 seconds
Started Jul 23 06:03:17 PM PDT 24
Finished Jul 23 06:03:20 PM PDT 24
Peak memory 196660 kb
Host smart-4414db2b-b879-4686-9ec7-3485dc70f78e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154438143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.154438143
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3259809297
Short name T475
Test name
Test status
Simulation time 261210952 ps
CPU time 1.19 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:03:15 PM PDT 24
Peak memory 197232 kb
Host smart-d75c1d1c-df0f-4c83-ba26-d70639ed975a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259809297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3259809297
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.883112047
Short name T672
Test name
Test status
Simulation time 146986036 ps
CPU time 1.45 seconds
Started Jul 23 06:03:23 PM PDT 24
Finished Jul 23 06:03:25 PM PDT 24
Peak memory 196848 kb
Host smart-0f1abadd-0080-4e11-aed9-da8d070041b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883112047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.883112047
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1714157335
Short name T264
Test name
Test status
Simulation time 56291001 ps
CPU time 1.69 seconds
Started Jul 23 06:03:15 PM PDT 24
Finished Jul 23 06:03:18 PM PDT 24
Peak memory 196360 kb
Host smart-33e51a6b-0e8e-40a7-9d1e-8bfe097d1377
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714157335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1714157335
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.4149278158
Short name T665
Test name
Test status
Simulation time 39923884 ps
CPU time 0.63 seconds
Started Jul 23 06:03:07 PM PDT 24
Finished Jul 23 06:03:09 PM PDT 24
Peak memory 194804 kb
Host smart-4adacacb-b1c3-428a-ad96-ec381103a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149278158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.4149278158
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.583834830
Short name T636
Test name
Test status
Simulation time 106734779 ps
CPU time 1.17 seconds
Started Jul 23 06:03:15 PM PDT 24
Finished Jul 23 06:03:17 PM PDT 24
Peak memory 198608 kb
Host smart-d44bed89-6846-4c70-8b17-a229e35c1ded
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583834830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.583834830
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.4060142139
Short name T694
Test name
Test status
Simulation time 45552344 ps
CPU time 1.91 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:19 PM PDT 24
Peak memory 198448 kb
Host smart-b2c94c57-ee5e-4982-947c-e3f359b36e6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060142139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.4060142139
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.923499821
Short name T532
Test name
Test status
Simulation time 110757560 ps
CPU time 0.98 seconds
Started Jul 23 06:03:15 PM PDT 24
Finished Jul 23 06:03:17 PM PDT 24
Peak memory 196844 kb
Host smart-0d1a3bfe-f34b-4b06-8aaf-0b3bc82e5c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923499821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.923499821
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.4171623017
Short name T631
Test name
Test status
Simulation time 37623430 ps
CPU time 0.75 seconds
Started Jul 23 06:03:15 PM PDT 24
Finished Jul 23 06:03:17 PM PDT 24
Peak memory 195652 kb
Host smart-30b55e39-cfe4-4291-8acb-a2429f691a9c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171623017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.4171623017
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1222211687
Short name T279
Test name
Test status
Simulation time 8622972922 ps
CPU time 111.02 seconds
Started Jul 23 06:03:11 PM PDT 24
Finished Jul 23 06:05:03 PM PDT 24
Peak memory 198696 kb
Host smart-a2279895-6d02-40b7-a59f-6be89ec82298
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222211687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1222211687
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2546527763
Short name T20
Test name
Test status
Simulation time 40395442 ps
CPU time 0.53 seconds
Started Jul 23 06:03:14 PM PDT 24
Finished Jul 23 06:03:16 PM PDT 24
Peak memory 194408 kb
Host smart-24dd1bb2-9637-456d-a1a2-293542229156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546527763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2546527763
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.562581844
Short name T383
Test name
Test status
Simulation time 142459164 ps
CPU time 0.88 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:03:15 PM PDT 24
Peak memory 196680 kb
Host smart-ad18db7b-3178-449d-b62f-47d5b10684da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562581844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.562581844
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.773170416
Short name T133
Test name
Test status
Simulation time 180147963 ps
CPU time 3.29 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:25 PM PDT 24
Peak memory 196364 kb
Host smart-b2f24238-aff9-4459-a550-23181c554d65
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773170416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.773170416
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1204210569
Short name T108
Test name
Test status
Simulation time 585894601 ps
CPU time 0.79 seconds
Started Jul 23 06:03:22 PM PDT 24
Finished Jul 23 06:03:24 PM PDT 24
Peak memory 196920 kb
Host smart-8af76b8d-6b93-4f7e-89fb-10b64f4645f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204210569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1204210569
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1353514694
Short name T424
Test name
Test status
Simulation time 97203304 ps
CPU time 0.93 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:19 PM PDT 24
Peak memory 196656 kb
Host smart-45b0d401-1a0d-4f85-86cd-a137081a97e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353514694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1353514694
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3662919542
Short name T594
Test name
Test status
Simulation time 49572160 ps
CPU time 1.91 seconds
Started Jul 23 06:03:17 PM PDT 24
Finished Jul 23 06:03:20 PM PDT 24
Peak memory 198692 kb
Host smart-0f78b502-e9bc-4bd9-b5a4-dd4215d0ee31
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662919542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3662919542
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3176867231
Short name T476
Test name
Test status
Simulation time 70072200 ps
CPU time 2.08 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:03:15 PM PDT 24
Peak memory 197656 kb
Host smart-beb166df-9c0c-430d-aae0-b82705af3a20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176867231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3176867231
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3265476703
Short name T136
Test name
Test status
Simulation time 114070783 ps
CPU time 1.12 seconds
Started Jul 23 06:03:27 PM PDT 24
Finished Jul 23 06:03:29 PM PDT 24
Peak memory 197176 kb
Host smart-16503be7-dcfd-489c-b1dc-a086178b9786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265476703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3265476703
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.717565347
Short name T674
Test name
Test status
Simulation time 95407974 ps
CPU time 1.03 seconds
Started Jul 23 06:03:11 PM PDT 24
Finished Jul 23 06:03:12 PM PDT 24
Peak memory 196512 kb
Host smart-4d6c2b0e-ad8e-4c58-b2e8-f0a0868703f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717565347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.717565347
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3114772980
Short name T708
Test name
Test status
Simulation time 214392611 ps
CPU time 3.61 seconds
Started Jul 23 06:03:18 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 198476 kb
Host smart-312df75e-f2e5-45ff-93ac-3fb25ca49530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114772980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3114772980
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.403058652
Short name T324
Test name
Test status
Simulation time 154181035 ps
CPU time 0.86 seconds
Started Jul 23 06:03:06 PM PDT 24
Finished Jul 23 06:03:08 PM PDT 24
Peak memory 195976 kb
Host smart-bfb84fef-dc1a-4633-8a5a-4b7561196253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403058652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.403058652
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1547570836
Short name T259
Test name
Test status
Simulation time 82453380 ps
CPU time 1.05 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 196552 kb
Host smart-e3ea73ab-0d26-4bfb-b794-2b28b9b5bf4d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547570836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1547570836
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.3202969995
Short name T61
Test name
Test status
Simulation time 42908610128 ps
CPU time 145.74 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:05:40 PM PDT 24
Peak memory 198632 kb
Host smart-1b9bdde8-7345-4042-b7ca-bfc1fc65e19d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202969995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.3202969995
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.912919940
Short name T260
Test name
Test status
Simulation time 27699076 ps
CPU time 0.56 seconds
Started Jul 23 06:03:21 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 194444 kb
Host smart-3f7ac9af-4414-450e-a1a7-7f5193673e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912919940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.912919940
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1395890639
Short name T507
Test name
Test status
Simulation time 120422837 ps
CPU time 0.79 seconds
Started Jul 23 06:03:19 PM PDT 24
Finished Jul 23 06:03:21 PM PDT 24
Peak memory 195696 kb
Host smart-5a3dca84-f49e-4196-82c6-0d1c44e12e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395890639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1395890639
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1104358312
Short name T336
Test name
Test status
Simulation time 1888714099 ps
CPU time 13.91 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 197476 kb
Host smart-0593d290-8da2-4b53-bfae-fdef1439f033
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104358312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1104358312
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2149920595
Short name T220
Test name
Test status
Simulation time 177317117 ps
CPU time 0.88 seconds
Started Jul 23 06:03:18 PM PDT 24
Finished Jul 23 06:03:21 PM PDT 24
Peak memory 198428 kb
Host smart-6c889ab3-7d84-4845-8668-08f8f8a738e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149920595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2149920595
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2563332542
Short name T24
Test name
Test status
Simulation time 446688182 ps
CPU time 1.04 seconds
Started Jul 23 06:03:35 PM PDT 24
Finished Jul 23 06:03:36 PM PDT 24
Peak memory 196628 kb
Host smart-a28a4cc0-1a00-42e4-8711-9f3cd831bf10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563332542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2563332542
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2692988036
Short name T296
Test name
Test status
Simulation time 93231146 ps
CPU time 3.46 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:25 PM PDT 24
Peak memory 198548 kb
Host smart-28ac7b98-d318-425b-8778-43edf9b2113c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692988036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2692988036
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.468146966
Short name T295
Test name
Test status
Simulation time 268652510 ps
CPU time 3.3 seconds
Started Jul 23 06:03:18 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 197680 kb
Host smart-ad1f893a-3bfb-4bb2-80e7-769fb4c5fca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468146966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger.
468146966
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.716109635
Short name T196
Test name
Test status
Simulation time 21753976 ps
CPU time 0.69 seconds
Started Jul 23 06:03:18 PM PDT 24
Finished Jul 23 06:03:20 PM PDT 24
Peak memory 195816 kb
Host smart-fa381edf-f874-4ca1-b3e9-6309938b3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716109635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.716109635
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2367629525
Short name T314
Test name
Test status
Simulation time 208887707 ps
CPU time 1.3 seconds
Started Jul 23 06:03:17 PM PDT 24
Finished Jul 23 06:03:20 PM PDT 24
Peak memory 198580 kb
Host smart-3999d221-6b75-4939-96e0-d465449fc51f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367629525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2367629525
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2985041280
Short name T450
Test name
Test status
Simulation time 71690962 ps
CPU time 1.25 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:03:15 PM PDT 24
Peak memory 198460 kb
Host smart-ecd6b61e-ac10-43be-913e-311f9875f208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985041280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2985041280
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1712633454
Short name T605
Test name
Test status
Simulation time 458069818 ps
CPU time 1.12 seconds
Started Jul 23 06:03:25 PM PDT 24
Finished Jul 23 06:03:27 PM PDT 24
Peak memory 196992 kb
Host smart-a67685d2-a25a-44ce-8dc7-edeb70e07b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712633454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1712633454
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.3679118932
Short name T539
Test name
Test status
Simulation time 35629829 ps
CPU time 0.96 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:19 PM PDT 24
Peak memory 196372 kb
Host smart-b2ae0d91-191f-4a74-9e53-cec9a0f08a38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679118932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.3679118932
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2448905625
Short name T166
Test name
Test status
Simulation time 22066976115 ps
CPU time 64.93 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:04:23 PM PDT 24
Peak memory 198620 kb
Host smart-d923e25c-39ef-4d21-8227-2113ea56a5d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448905625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2448905625
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1025982398
Short name T411
Test name
Test status
Simulation time 27224398 ps
CPU time 0.55 seconds
Started Jul 23 06:03:22 PM PDT 24
Finished Jul 23 06:03:24 PM PDT 24
Peak memory 193168 kb
Host smart-27b8a8f1-ce26-44a8-942b-ced3144c0236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025982398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1025982398
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3286730799
Short name T522
Test name
Test status
Simulation time 18424149 ps
CPU time 0.6 seconds
Started Jul 23 06:03:22 PM PDT 24
Finished Jul 23 06:03:29 PM PDT 24
Peak memory 194332 kb
Host smart-2c30c6dd-1a29-4b29-9bff-41da16980d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286730799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3286730799
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.410365608
Short name T375
Test name
Test status
Simulation time 573960320 ps
CPU time 21.24 seconds
Started Jul 23 06:03:12 PM PDT 24
Finished Jul 23 06:03:34 PM PDT 24
Peak memory 197520 kb
Host smart-9ff59263-f624-4b5b-82ac-3f8c2126919a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410365608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.410365608
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.82277624
Short name T628
Test name
Test status
Simulation time 69301589 ps
CPU time 0.91 seconds
Started Jul 23 06:03:30 PM PDT 24
Finished Jul 23 06:03:32 PM PDT 24
Peak memory 197236 kb
Host smart-c07293f4-338f-4e24-a7b2-8a6b1ea5615f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82277624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.82277624
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2334143531
Short name T149
Test name
Test status
Simulation time 90148877 ps
CPU time 0.77 seconds
Started Jul 23 06:03:21 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 196796 kb
Host smart-6cd172fa-0521-49b6-affc-ad79d4275527
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334143531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2334143531
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3160763139
Short name T538
Test name
Test status
Simulation time 42419530 ps
CPU time 1.12 seconds
Started Jul 23 06:03:21 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 197592 kb
Host smart-2db61f5e-27e7-43cd-a8b0-286c522f0ddd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160763139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3160763139
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3607442803
Short name T230
Test name
Test status
Simulation time 151074587 ps
CPU time 3.15 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:25 PM PDT 24
Peak memory 198524 kb
Host smart-26b804d6-24aa-449e-9a71-44b77ea89260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607442803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3607442803
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1144652808
Short name T187
Test name
Test status
Simulation time 56427482 ps
CPU time 1.19 seconds
Started Jul 23 06:03:17 PM PDT 24
Finished Jul 23 06:03:20 PM PDT 24
Peak memory 197076 kb
Host smart-5638313f-977d-418b-8a11-ae29337349a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144652808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1144652808
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3673244663
Short name T381
Test name
Test status
Simulation time 271334771 ps
CPU time 1.22 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:22 PM PDT 24
Peak memory 196368 kb
Host smart-f80719a8-b2a6-41be-b229-d962051ea314
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673244663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3673244663
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2730465432
Short name T648
Test name
Test status
Simulation time 1245531755 ps
CPU time 5.17 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:03:19 PM PDT 24
Peak memory 198508 kb
Host smart-99511c59-01b4-4847-8481-256efff87b4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730465432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2730465432
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2934197634
Short name T451
Test name
Test status
Simulation time 187048024 ps
CPU time 1.04 seconds
Started Jul 23 06:03:28 PM PDT 24
Finished Jul 23 06:03:30 PM PDT 24
Peak memory 196284 kb
Host smart-e26bd0af-bc2f-4032-92d6-d02408e6d6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934197634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2934197634
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2944783663
Short name T362
Test name
Test status
Simulation time 57872047 ps
CPU time 0.94 seconds
Started Jul 23 06:03:23 PM PDT 24
Finished Jul 23 06:03:25 PM PDT 24
Peak memory 196608 kb
Host smart-77d0c8d4-0f3f-47f9-a0fe-d0efc557ecdf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944783663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2944783663
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.4244722329
Short name T242
Test name
Test status
Simulation time 9409087985 ps
CPU time 100.43 seconds
Started Jul 23 06:03:13 PM PDT 24
Finished Jul 23 06:04:54 PM PDT 24
Peak memory 198636 kb
Host smart-0a09a575-e277-46a6-b3d2-d1919896a8f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244722329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.4244722329
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1205191045
Short name T462
Test name
Test status
Simulation time 22958621 ps
CPU time 0.57 seconds
Started Jul 23 06:01:30 PM PDT 24
Finished Jul 23 06:01:42 PM PDT 24
Peak memory 194444 kb
Host smart-1abe3aea-77a4-4cf3-8e9b-0025d92e9292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205191045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1205191045
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.117123865
Short name T590
Test name
Test status
Simulation time 26649412 ps
CPU time 0.7 seconds
Started Jul 23 06:01:35 PM PDT 24
Finished Jul 23 06:01:37 PM PDT 24
Peak memory 194728 kb
Host smart-8e30d949-7141-4b9a-baed-0062b2482ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117123865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.117123865
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1115658364
Short name T376
Test name
Test status
Simulation time 4562340601 ps
CPU time 21.41 seconds
Started Jul 23 06:01:30 PM PDT 24
Finished Jul 23 06:01:53 PM PDT 24
Peak memory 196912 kb
Host smart-f87ed12d-294d-40e0-8b4d-cc63a76042f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115658364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1115658364
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1716707942
Short name T352
Test name
Test status
Simulation time 184163912 ps
CPU time 0.8 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:01:34 PM PDT 24
Peak memory 196544 kb
Host smart-017971d1-8c0f-4a10-b32b-cf8fe3ff2760
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716707942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1716707942
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1676220040
Short name T571
Test name
Test status
Simulation time 36753913 ps
CPU time 1.12 seconds
Started Jul 23 06:01:25 PM PDT 24
Finished Jul 23 06:01:27 PM PDT 24
Peak memory 197036 kb
Host smart-4f92842a-7496-4660-a487-afc6aec0357b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676220040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1676220040
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1278806149
Short name T642
Test name
Test status
Simulation time 52896332 ps
CPU time 1.93 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:01:35 PM PDT 24
Peak memory 198520 kb
Host smart-1352103f-ec2f-4136-a2c2-a2ad618b999d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278806149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1278806149
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2261025262
Short name T172
Test name
Test status
Simulation time 660762093 ps
CPU time 2.34 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:01:36 PM PDT 24
Peak memory 197456 kb
Host smart-042e5c29-fb78-49cc-a906-02ff4991ece3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261025262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2261025262
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3934128330
Short name T247
Test name
Test status
Simulation time 29243079 ps
CPU time 0.63 seconds
Started Jul 23 06:01:28 PM PDT 24
Finished Jul 23 06:01:30 PM PDT 24
Peak memory 194708 kb
Host smart-d0bcfde9-f5b9-4588-8636-d9e799878f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934128330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3934128330
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4024889934
Short name T389
Test name
Test status
Simulation time 118473815 ps
CPU time 0.8 seconds
Started Jul 23 06:01:31 PM PDT 24
Finished Jul 23 06:01:32 PM PDT 24
Peak memory 196088 kb
Host smart-97c0e956-97c3-4ac5-ae07-ffce0b0a65f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024889934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4024889934
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.18134840
Short name T192
Test name
Test status
Simulation time 504894138 ps
CPU time 5.54 seconds
Started Jul 23 06:01:33 PM PDT 24
Finished Jul 23 06:01:40 PM PDT 24
Peak memory 198548 kb
Host smart-7d1dafa2-d7af-442d-a4a4-0d2ca1651a39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18134840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rando
m_long_reg_writes_reg_reads.18134840
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1160361826
Short name T42
Test name
Test status
Simulation time 95976953 ps
CPU time 0.95 seconds
Started Jul 23 06:01:37 PM PDT 24
Finished Jul 23 06:01:39 PM PDT 24
Peak memory 215520 kb
Host smart-e5893175-0b71-445b-b3ad-a65b24c526bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160361826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1160361826
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2814468463
Short name T454
Test name
Test status
Simulation time 77095786 ps
CPU time 1.35 seconds
Started Jul 23 06:01:31 PM PDT 24
Finished Jul 23 06:01:33 PM PDT 24
Peak memory 198480 kb
Host smart-60f96bf5-b4f4-4d59-bdb7-05dd1451ac3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814468463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2814468463
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.43100184
Short name T155
Test name
Test status
Simulation time 57240970 ps
CPU time 1.27 seconds
Started Jul 23 06:01:29 PM PDT 24
Finished Jul 23 06:01:31 PM PDT 24
Peak memory 197044 kb
Host smart-e16508b1-6e98-4d45-84f7-19eff94eee7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43100184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.43100184
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2051834337
Short name T557
Test name
Test status
Simulation time 15191579628 ps
CPU time 29.46 seconds
Started Jul 23 06:01:34 PM PDT 24
Finished Jul 23 06:02:04 PM PDT 24
Peak memory 198584 kb
Host smart-8384de8c-5b0e-45ce-a80a-d1acf21a049c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051834337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2051834337
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1955264360
Short name T516
Test name
Test status
Simulation time 54115019513 ps
CPU time 381.64 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:07:55 PM PDT 24
Peak memory 198748 kb
Host smart-42e361f7-2775-456a-8deb-93a9d83845ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1955264360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1955264360
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3921199464
Short name T14
Test name
Test status
Simulation time 34974635 ps
CPU time 0.55 seconds
Started Jul 23 06:03:17 PM PDT 24
Finished Jul 23 06:03:19 PM PDT 24
Peak memory 194432 kb
Host smart-0bcebeb0-9904-4249-91e9-934e44770f0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921199464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3921199464
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3424562046
Short name T489
Test name
Test status
Simulation time 675765563 ps
CPU time 0.87 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:22 PM PDT 24
Peak memory 196640 kb
Host smart-9c57ba3e-6474-47bd-98d7-36950be85940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424562046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3424562046
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.4008048941
Short name T680
Test name
Test status
Simulation time 362866402 ps
CPU time 18.14 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:36 PM PDT 24
Peak memory 196032 kb
Host smart-1871c0f1-e63b-486c-bddd-b64026009590
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008048941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.4008048941
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.4059319015
Short name T214
Test name
Test status
Simulation time 55204438 ps
CPU time 0.65 seconds
Started Jul 23 06:03:39 PM PDT 24
Finished Jul 23 06:03:40 PM PDT 24
Peak memory 194944 kb
Host smart-4659f92e-72d4-478e-b8a3-cbff9c9a7962
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059319015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.4059319015
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2758768223
Short name T321
Test name
Test status
Simulation time 82006903 ps
CPU time 1.13 seconds
Started Jul 23 06:03:21 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 196288 kb
Host smart-9f7480c3-2b1f-4b2b-9d77-ffab91800545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758768223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2758768223
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2012792035
Short name T651
Test name
Test status
Simulation time 61314190 ps
CPU time 2.38 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 198676 kb
Host smart-25087be1-8409-4527-8150-885eedb1e958
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012792035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2012792035
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3303987839
Short name T635
Test name
Test status
Simulation time 55514066 ps
CPU time 1.63 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:19 PM PDT 24
Peak memory 196328 kb
Host smart-4c5c29e6-5278-4c79-ab93-18d80b342e46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303987839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3303987839
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3428908231
Short name T623
Test name
Test status
Simulation time 169566966 ps
CPU time 1.04 seconds
Started Jul 23 06:03:09 PM PDT 24
Finished Jul 23 06:03:11 PM PDT 24
Peak memory 197092 kb
Host smart-0cee4e2d-1dcb-4a0a-be1a-d265642df00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428908231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3428908231
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2321387453
Short name T307
Test name
Test status
Simulation time 413498662 ps
CPU time 0.93 seconds
Started Jul 23 06:03:16 PM PDT 24
Finished Jul 23 06:03:18 PM PDT 24
Peak memory 197244 kb
Host smart-8b577293-3546-45d2-98f1-e68ec6bc1233
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321387453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2321387453
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.488347817
Short name T615
Test name
Test status
Simulation time 154971382 ps
CPU time 2.59 seconds
Started Jul 23 06:03:25 PM PDT 24
Finished Jul 23 06:03:28 PM PDT 24
Peak memory 198472 kb
Host smart-1016828b-e999-4864-8e44-3afe7ba604e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488347817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.488347817
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.212886163
Short name T256
Test name
Test status
Simulation time 122299521 ps
CPU time 0.76 seconds
Started Jul 23 06:03:21 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 195668 kb
Host smart-92a8ba20-8b81-407b-bd05-1f26fa85b3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212886163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.212886163
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1365728131
Short name T104
Test name
Test status
Simulation time 32837250 ps
CPU time 0.88 seconds
Started Jul 23 06:03:20 PM PDT 24
Finished Jul 23 06:03:22 PM PDT 24
Peak memory 195924 kb
Host smart-a8b836c0-5746-41d6-8478-0539114a6db2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365728131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1365728131
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3557146544
Short name T191
Test name
Test status
Simulation time 3616116059 ps
CPU time 84.94 seconds
Started Jul 23 06:03:39 PM PDT 24
Finished Jul 23 06:05:05 PM PDT 24
Peak memory 198568 kb
Host smart-73f81d7d-a617-4c9d-a840-628533bb0b82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557146544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3557146544
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.434345296
Short name T602
Test name
Test status
Simulation time 174687980268 ps
CPU time 1275.81 seconds
Started Jul 23 06:03:34 PM PDT 24
Finished Jul 23 06:24:51 PM PDT 24
Peak memory 198732 kb
Host smart-bf9d163f-8f32-4079-8fd7-f5ad78d1cd7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=434345296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.434345296
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1140614511
Short name T245
Test name
Test status
Simulation time 11468307 ps
CPU time 0.57 seconds
Started Jul 23 06:03:31 PM PDT 24
Finished Jul 23 06:03:32 PM PDT 24
Peak memory 194468 kb
Host smart-39dd2a87-424c-4df1-af0a-eeb44725bef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140614511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1140614511
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.737661361
Short name T129
Test name
Test status
Simulation time 38152219 ps
CPU time 0.8 seconds
Started Jul 23 06:03:38 PM PDT 24
Finished Jul 23 06:03:39 PM PDT 24
Peak memory 195884 kb
Host smart-5d24c674-01ed-4bc1-8686-77134dbcb25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737661361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.737661361
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1487333814
Short name T162
Test name
Test status
Simulation time 769174402 ps
CPU time 21.63 seconds
Started Jul 23 06:03:17 PM PDT 24
Finished Jul 23 06:03:41 PM PDT 24
Peak memory 197336 kb
Host smart-f8058edd-cb7c-42e3-a015-863db29b5c2f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487333814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1487333814
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.862750983
Short name T613
Test name
Test status
Simulation time 42405864 ps
CPU time 0.8 seconds
Started Jul 23 06:03:45 PM PDT 24
Finished Jul 23 06:03:46 PM PDT 24
Peak memory 197052 kb
Host smart-8ab73e4b-4a53-49b7-88d1-838881dcec2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862750983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.862750983
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.129286820
Short name T114
Test name
Test status
Simulation time 38697235 ps
CPU time 0.87 seconds
Started Jul 23 06:03:34 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 196156 kb
Host smart-663fea7f-64db-4eba-8c20-8c18833b4eb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129286820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.129286820
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2570850652
Short name T481
Test name
Test status
Simulation time 65199122 ps
CPU time 2.48 seconds
Started Jul 23 06:03:27 PM PDT 24
Finished Jul 23 06:03:30 PM PDT 24
Peak memory 197032 kb
Host smart-bd0decdd-db1a-460d-a5b1-68d65e55b848
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570850652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2570850652
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.4256756824
Short name T483
Test name
Test status
Simulation time 154088569 ps
CPU time 3.01 seconds
Started Jul 23 06:03:27 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 198540 kb
Host smart-1fdb89e2-1a0a-40db-8c1c-9f68f18def76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256756824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.4256756824
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2152947496
Short name T315
Test name
Test status
Simulation time 163106406 ps
CPU time 1.05 seconds
Started Jul 23 06:03:21 PM PDT 24
Finished Jul 23 06:03:23 PM PDT 24
Peak memory 196516 kb
Host smart-cd8e5f28-7d77-4973-b6fa-c5cf61d5b160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152947496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2152947496
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3289450666
Short name T128
Test name
Test status
Simulation time 49230548 ps
CPU time 1.07 seconds
Started Jul 23 06:03:18 PM PDT 24
Finished Jul 23 06:03:21 PM PDT 24
Peak memory 196496 kb
Host smart-c8376fe7-355e-4156-a501-88a5b97eec09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289450666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3289450666
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3861040255
Short name T163
Test name
Test status
Simulation time 287506134 ps
CPU time 3.45 seconds
Started Jul 23 06:03:50 PM PDT 24
Finished Jul 23 06:03:54 PM PDT 24
Peak memory 198496 kb
Host smart-35377e5d-5577-4bd3-b606-d6a70f3ec684
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861040255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3861040255
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1608837384
Short name T550
Test name
Test status
Simulation time 30138732 ps
CPU time 0.96 seconds
Started Jul 23 06:03:33 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 196224 kb
Host smart-8b34a56b-d68b-4c15-8940-f9247aaa5349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608837384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1608837384
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3115560853
Short name T553
Test name
Test status
Simulation time 30384019 ps
CPU time 0.71 seconds
Started Jul 23 06:03:29 PM PDT 24
Finished Jul 23 06:03:31 PM PDT 24
Peak memory 195304 kb
Host smart-010a5bad-743d-4087-adda-84379628a6df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115560853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3115560853
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3584501414
Short name T574
Test name
Test status
Simulation time 27448991355 ps
CPU time 162.61 seconds
Started Jul 23 06:03:30 PM PDT 24
Finished Jul 23 06:06:13 PM PDT 24
Peak memory 198560 kb
Host smart-c1d33d88-4410-4005-9b29-9971eadb95a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584501414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3584501414
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1610254447
Short name T396
Test name
Test status
Simulation time 21592531 ps
CPU time 0.58 seconds
Started Jul 23 06:04:07 PM PDT 24
Finished Jul 23 06:04:08 PM PDT 24
Peak memory 194416 kb
Host smart-2d34e258-9054-425b-b36f-24442e0bb31a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610254447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1610254447
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1530734071
Short name T219
Test name
Test status
Simulation time 151038155 ps
CPU time 0.84 seconds
Started Jul 23 06:03:33 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 197016 kb
Host smart-f7ecc2e5-69a2-4180-8f76-e5f802ddfecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530734071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1530734071
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3205682463
Short name T339
Test name
Test status
Simulation time 119728140 ps
CPU time 4.09 seconds
Started Jul 23 06:03:37 PM PDT 24
Finished Jul 23 06:03:42 PM PDT 24
Peak memory 196904 kb
Host smart-af050dba-2f62-4f42-a95f-c03a3e02ea7b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205682463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3205682463
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2522512229
Short name T586
Test name
Test status
Simulation time 164647446 ps
CPU time 1.05 seconds
Started Jul 23 06:03:46 PM PDT 24
Finished Jul 23 06:03:48 PM PDT 24
Peak memory 198344 kb
Host smart-90cc6725-ff86-48ee-91e2-e52f0135d32c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522512229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2522512229
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2051779302
Short name T188
Test name
Test status
Simulation time 42527207 ps
CPU time 1.23 seconds
Started Jul 23 06:03:34 PM PDT 24
Finished Jul 23 06:03:36 PM PDT 24
Peak memory 197324 kb
Host smart-2a8f0612-2fed-4f6c-a981-9dce97f4b686
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051779302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2051779302
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3002905443
Short name T51
Test name
Test status
Simulation time 567216322 ps
CPU time 3 seconds
Started Jul 23 06:03:30 PM PDT 24
Finished Jul 23 06:03:33 PM PDT 24
Peak memory 197540 kb
Host smart-bb7764ea-697e-42f2-8d75-503a4075469f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002905443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3002905443
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3243851960
Short name T439
Test name
Test status
Simulation time 57979187 ps
CPU time 1.27 seconds
Started Jul 23 06:03:33 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 197560 kb
Host smart-c5c40bdf-59b2-4c91-b7a4-516c8e4b12c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243851960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3243851960
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.929996595
Short name T45
Test name
Test status
Simulation time 55004887 ps
CPU time 1.13 seconds
Started Jul 23 06:03:46 PM PDT 24
Finished Jul 23 06:03:47 PM PDT 24
Peak memory 197876 kb
Host smart-982aa72f-dfe0-49b8-8e10-c6c6d90e77eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929996595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.929996595
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.88250844
Short name T7
Test name
Test status
Simulation time 1361501067 ps
CPU time 3.43 seconds
Started Jul 23 06:03:31 PM PDT 24
Finished Jul 23 06:03:35 PM PDT 24
Peak memory 198536 kb
Host smart-603a6ad0-a9ea-4707-aa51-3ed837c2836f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88250844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand
om_long_reg_writes_reg_reads.88250844
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2527652564
Short name T603
Test name
Test status
Simulation time 98411977 ps
CPU time 0.8 seconds
Started Jul 23 06:03:23 PM PDT 24
Finished Jul 23 06:03:25 PM PDT 24
Peak memory 196376 kb
Host smart-3273425f-1b12-408b-a490-3a13f6f1f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527652564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2527652564
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2909519102
Short name T584
Test name
Test status
Simulation time 329185754 ps
CPU time 0.95 seconds
Started Jul 23 06:03:48 PM PDT 24
Finished Jul 23 06:03:50 PM PDT 24
Peak memory 196828 kb
Host smart-a1ae86f4-2eb6-419b-90b6-d04f0f1f7642
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909519102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2909519102
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2545984203
Short name T137
Test name
Test status
Simulation time 42510995518 ps
CPU time 144.87 seconds
Started Jul 23 06:03:33 PM PDT 24
Finished Jul 23 06:05:59 PM PDT 24
Peak memory 198640 kb
Host smart-70aa6919-2bb9-4ea4-a588-c8dbcbaeb8ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545984203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2545984203
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1147150100
Short name T699
Test name
Test status
Simulation time 11571185 ps
CPU time 0.56 seconds
Started Jul 23 06:03:43 PM PDT 24
Finished Jul 23 06:03:44 PM PDT 24
Peak memory 194428 kb
Host smart-8051e329-c5a9-47e2-8f97-5e9a2e656225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147150100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1147150100
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.660395320
Short name T508
Test name
Test status
Simulation time 26436077 ps
CPU time 0.85 seconds
Started Jul 23 06:03:39 PM PDT 24
Finished Jul 23 06:03:40 PM PDT 24
Peak memory 195908 kb
Host smart-ab10c81d-1b3a-47d4-9d07-968384511f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660395320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.660395320
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2633497123
Short name T673
Test name
Test status
Simulation time 3503972237 ps
CPU time 25.15 seconds
Started Jul 23 06:03:50 PM PDT 24
Finished Jul 23 06:04:16 PM PDT 24
Peak memory 197512 kb
Host smart-01da8fde-4253-491d-bee8-b2cb1cbdaa3f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633497123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2633497123
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3647814091
Short name T158
Test name
Test status
Simulation time 267279001 ps
CPU time 1.08 seconds
Started Jul 23 06:03:53 PM PDT 24
Finished Jul 23 06:03:55 PM PDT 24
Peak memory 197108 kb
Host smart-1b0c2af3-d47f-4764-8da6-90610428d106
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647814091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3647814091
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3354677738
Short name T436
Test name
Test status
Simulation time 468314966 ps
CPU time 1.15 seconds
Started Jul 23 06:03:51 PM PDT 24
Finished Jul 23 06:03:53 PM PDT 24
Peak memory 197240 kb
Host smart-4a0fe73f-bad4-44ba-9434-80c06357b3ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354677738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3354677738
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2535313244
Short name T59
Test name
Test status
Simulation time 60207126 ps
CPU time 1.29 seconds
Started Jul 23 06:03:46 PM PDT 24
Finished Jul 23 06:03:48 PM PDT 24
Peak memory 197040 kb
Host smart-3a94cdae-9311-464c-91c1-53a450883fa5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535313244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2535313244
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1661879317
Short name T446
Test name
Test status
Simulation time 410548629 ps
CPU time 2.57 seconds
Started Jul 23 06:03:42 PM PDT 24
Finished Jul 23 06:03:45 PM PDT 24
Peak memory 196392 kb
Host smart-c7b73561-1eec-4ffa-afd0-2c60a68b2e87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661879317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1661879317
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3653687303
Short name T216
Test name
Test status
Simulation time 122143598 ps
CPU time 0.82 seconds
Started Jul 23 06:03:45 PM PDT 24
Finished Jul 23 06:03:47 PM PDT 24
Peak memory 197096 kb
Host smart-fb1c7f27-5d7c-47b3-a839-f3613c9fe8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653687303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3653687303
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.938825813
Short name T347
Test name
Test status
Simulation time 268798825 ps
CPU time 1.28 seconds
Started Jul 23 06:03:51 PM PDT 24
Finished Jul 23 06:03:53 PM PDT 24
Peak memory 197424 kb
Host smart-e035df38-e4c1-404b-9495-eb8f1caeada4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938825813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.938825813
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.846231014
Short name T366
Test name
Test status
Simulation time 589075629 ps
CPU time 2.71 seconds
Started Jul 23 06:03:38 PM PDT 24
Finished Jul 23 06:03:41 PM PDT 24
Peak memory 198448 kb
Host smart-187991fc-d535-4c14-b322-01a14c3358d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846231014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.846231014
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2423243863
Short name T205
Test name
Test status
Simulation time 48381596 ps
CPU time 1.25 seconds
Started Jul 23 06:03:50 PM PDT 24
Finished Jul 23 06:03:52 PM PDT 24
Peak memory 196076 kb
Host smart-0e87f2ab-9fa9-4ed2-8d12-c86bbc6f5106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423243863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2423243863
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1062835968
Short name T405
Test name
Test status
Simulation time 119017737 ps
CPU time 1.1 seconds
Started Jul 23 06:03:42 PM PDT 24
Finished Jul 23 06:03:43 PM PDT 24
Peak memory 196196 kb
Host smart-903cb425-ceae-4dae-881b-4e3197bd2c96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062835968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1062835968
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3302536469
Short name T690
Test name
Test status
Simulation time 4193268061 ps
CPU time 46.75 seconds
Started Jul 23 06:03:40 PM PDT 24
Finished Jul 23 06:04:27 PM PDT 24
Peak memory 198488 kb
Host smart-ae1aadaf-f507-4238-9489-3d71eb7d09a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302536469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3302536469
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.592827284
Short name T57
Test name
Test status
Simulation time 27754961211 ps
CPU time 356.81 seconds
Started Jul 23 06:03:41 PM PDT 24
Finished Jul 23 06:09:39 PM PDT 24
Peak memory 198788 kb
Host smart-eed17323-455b-4e00-b056-8f09c14463d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=592827284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.592827284
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2117607737
Short name T269
Test name
Test status
Simulation time 44549369 ps
CPU time 0.56 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:13 PM PDT 24
Peak memory 194456 kb
Host smart-459477d2-23c6-44b6-a3e8-bfa24f310019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117607737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2117607737
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3655124971
Short name T528
Test name
Test status
Simulation time 88801504 ps
CPU time 0.7 seconds
Started Jul 23 06:03:47 PM PDT 24
Finished Jul 23 06:03:48 PM PDT 24
Peak memory 195376 kb
Host smart-790513e3-d34f-4226-9e76-deb2c4d1f027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655124971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3655124971
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2278967079
Short name T607
Test name
Test status
Simulation time 168237737 ps
CPU time 4.47 seconds
Started Jul 23 06:03:56 PM PDT 24
Finished Jul 23 06:04:01 PM PDT 24
Peak memory 196468 kb
Host smart-e9dae9e0-a005-4ce3-af90-565d9e07e0d8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278967079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2278967079
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1008804356
Short name T495
Test name
Test status
Simulation time 39279986 ps
CPU time 0.77 seconds
Started Jul 23 06:03:58 PM PDT 24
Finished Jul 23 06:03:59 PM PDT 24
Peak memory 195008 kb
Host smart-ce278dbc-8956-4359-89da-5c4a55923746
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008804356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1008804356
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3024011665
Short name T330
Test name
Test status
Simulation time 151184504 ps
CPU time 0.88 seconds
Started Jul 23 06:03:59 PM PDT 24
Finished Jul 23 06:04:00 PM PDT 24
Peak memory 197076 kb
Host smart-79eafaf1-9f44-419c-ae1c-82eae9bc9b8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024011665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3024011665
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1942308980
Short name T534
Test name
Test status
Simulation time 59430384 ps
CPU time 2.37 seconds
Started Jul 23 06:03:51 PM PDT 24
Finished Jul 23 06:03:54 PM PDT 24
Peak memory 198464 kb
Host smart-c98a4c03-7222-49ad-ad8e-9f6eba88c287
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942308980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1942308980
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2457603907
Short name T266
Test name
Test status
Simulation time 279841796 ps
CPU time 2.15 seconds
Started Jul 23 06:04:13 PM PDT 24
Finished Jul 23 06:04:17 PM PDT 24
Peak memory 197464 kb
Host smart-f7d7ddd5-8346-4968-a213-b79c2842daed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457603907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2457603907
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1439000186
Short name T235
Test name
Test status
Simulation time 498293662 ps
CPU time 1.19 seconds
Started Jul 23 06:03:49 PM PDT 24
Finished Jul 23 06:03:51 PM PDT 24
Peak memory 196564 kb
Host smart-20d26683-5528-43ee-aeb0-286c5f74e264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439000186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1439000186
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.4192361743
Short name T183
Test name
Test status
Simulation time 113257528 ps
CPU time 1.25 seconds
Started Jul 23 06:03:52 PM PDT 24
Finished Jul 23 06:03:54 PM PDT 24
Peak memory 196368 kb
Host smart-136efa49-60cc-4b97-ad2d-1eb72c815873
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192361743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.4192361743
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1357801555
Short name T464
Test name
Test status
Simulation time 703155893 ps
CPU time 4.14 seconds
Started Jul 23 06:03:35 PM PDT 24
Finished Jul 23 06:03:40 PM PDT 24
Peak memory 198512 kb
Host smart-79956155-fd49-4134-89f2-43175c6edb70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357801555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1357801555
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2357335201
Short name T252
Test name
Test status
Simulation time 28695504 ps
CPU time 0.81 seconds
Started Jul 23 06:03:48 PM PDT 24
Finished Jul 23 06:03:55 PM PDT 24
Peak memory 195808 kb
Host smart-fdaa82c5-dbe7-4dae-98ff-810af064e604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357335201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2357335201
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.480280529
Short name T13
Test name
Test status
Simulation time 31394616 ps
CPU time 0.75 seconds
Started Jul 23 06:03:41 PM PDT 24
Finished Jul 23 06:03:42 PM PDT 24
Peak memory 195772 kb
Host smart-411dff65-0301-482c-933c-857f448cc2e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480280529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.480280529
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1842350984
Short name T273
Test name
Test status
Simulation time 11898208334 ps
CPU time 151.04 seconds
Started Jul 23 06:03:52 PM PDT 24
Finished Jul 23 06:06:24 PM PDT 24
Peak memory 198624 kb
Host smart-a5c4caef-726a-4a24-9468-7d47c6fdda8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842350984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1842350984
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1640790769
Short name T109
Test name
Test status
Simulation time 14301009 ps
CPU time 0.56 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 194472 kb
Host smart-aab2eb5d-84ad-43cc-854a-c238c5dee516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640790769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1640790769
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3526531182
Short name T374
Test name
Test status
Simulation time 34458156 ps
CPU time 0.71 seconds
Started Jul 23 06:04:04 PM PDT 24
Finished Jul 23 06:04:05 PM PDT 24
Peak memory 196256 kb
Host smart-e64793a1-e1ff-4bf2-84ce-5630ee044e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526531182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3526531182
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1563383926
Short name T228
Test name
Test status
Simulation time 1090923982 ps
CPU time 10.47 seconds
Started Jul 23 06:03:46 PM PDT 24
Finished Jul 23 06:03:58 PM PDT 24
Peak memory 197424 kb
Host smart-505d71e8-97c4-4e1f-9f11-d88b96ff8dfa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563383926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1563383926
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.400399128
Short name T165
Test name
Test status
Simulation time 85080858 ps
CPU time 0.64 seconds
Started Jul 23 06:03:49 PM PDT 24
Finished Jul 23 06:03:51 PM PDT 24
Peak memory 194884 kb
Host smart-927a73f3-eff9-4192-944a-19b9719e64fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400399128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.400399128
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.936749616
Short name T610
Test name
Test status
Simulation time 83646585 ps
CPU time 0.81 seconds
Started Jul 23 06:03:50 PM PDT 24
Finished Jul 23 06:03:52 PM PDT 24
Peak memory 196148 kb
Host smart-75a5e801-4e83-40db-92f9-60e70a35893d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936749616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.936749616
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2413469438
Short name T60
Test name
Test status
Simulation time 406665060 ps
CPU time 2.39 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:15 PM PDT 24
Peak memory 196760 kb
Host smart-8e1e6396-deec-41d6-8782-e900479c03de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413469438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2413469438
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.4274283223
Short name T678
Test name
Test status
Simulation time 224092755 ps
CPU time 3.72 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:13 PM PDT 24
Peak memory 196352 kb
Host smart-1737713e-a940-40e4-b1a7-c62e101a5fa0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274283223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.4274283223
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.4224947634
Short name T545
Test name
Test status
Simulation time 150078843 ps
CPU time 1.35 seconds
Started Jul 23 06:03:54 PM PDT 24
Finished Jul 23 06:03:56 PM PDT 24
Peak memory 198556 kb
Host smart-ae51c318-ca52-4a8d-8e9e-fad0e9cc9652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224947634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.4224947634
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.4022142154
Short name T477
Test name
Test status
Simulation time 70415203 ps
CPU time 1.34 seconds
Started Jul 23 06:03:58 PM PDT 24
Finished Jul 23 06:04:00 PM PDT 24
Peak memory 197620 kb
Host smart-bd0456cc-89fc-4cec-a0b4-339339238fab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022142154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.4022142154
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2250533777
Short name T373
Test name
Test status
Simulation time 325814126 ps
CPU time 5.14 seconds
Started Jul 23 06:04:04 PM PDT 24
Finished Jul 23 06:04:10 PM PDT 24
Peak memory 198400 kb
Host smart-72105277-30df-424c-bf90-69dd8f60468c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250533777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2250533777
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3456130725
Short name T596
Test name
Test status
Simulation time 477515470 ps
CPU time 0.82 seconds
Started Jul 23 06:03:53 PM PDT 24
Finished Jul 23 06:03:55 PM PDT 24
Peak memory 195672 kb
Host smart-3cf49b65-000c-4500-86ad-1cb361813e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456130725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3456130725
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.321193098
Short name T629
Test name
Test status
Simulation time 86637873 ps
CPU time 1.41 seconds
Started Jul 23 06:03:44 PM PDT 24
Finished Jul 23 06:03:46 PM PDT 24
Peak memory 196800 kb
Host smart-a578f9d8-a53c-4fb7-bb9f-0ccc99a25758
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321193098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.321193098
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4108228335
Short name T298
Test name
Test status
Simulation time 44195833593 ps
CPU time 122.42 seconds
Started Jul 23 06:04:04 PM PDT 24
Finished Jul 23 06:06:07 PM PDT 24
Peak memory 198640 kb
Host smart-6ac5b532-fe25-448c-a349-2e05321ce5ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108228335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4108228335
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1497449097
Short name T29
Test name
Test status
Simulation time 185742650834 ps
CPU time 1326.16 seconds
Started Jul 23 06:04:14 PM PDT 24
Finished Jul 23 06:26:22 PM PDT 24
Peak memory 198680 kb
Host smart-546b4274-598f-459b-9a78-f88ab4ec4721
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1497449097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1497449097
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2792897631
Short name T140
Test name
Test status
Simulation time 29920439 ps
CPU time 0.57 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 193236 kb
Host smart-784ef89a-34f3-45ba-8f5a-65ed5ccb600f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792897631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2792897631
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.409452660
Short name T304
Test name
Test status
Simulation time 35364752 ps
CPU time 0.6 seconds
Started Jul 23 06:03:53 PM PDT 24
Finished Jul 23 06:03:54 PM PDT 24
Peak memory 194480 kb
Host smart-03ce3a10-c3a1-4d12-9ce9-0a40b898407d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409452660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.409452660
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3946921030
Short name T361
Test name
Test status
Simulation time 948215453 ps
CPU time 13.05 seconds
Started Jul 23 06:03:57 PM PDT 24
Finished Jul 23 06:04:11 PM PDT 24
Peak memory 197296 kb
Host smart-48a9739c-b9d0-435c-971e-01b148b332b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946921030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3946921030
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.962750116
Short name T614
Test name
Test status
Simulation time 104840551 ps
CPU time 1.02 seconds
Started Jul 23 06:03:54 PM PDT 24
Finished Jul 23 06:03:56 PM PDT 24
Peak memory 197192 kb
Host smart-ea13af28-aecf-4ad7-9f6f-f0909fcd8d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962750116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.962750116
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.850897271
Short name T113
Test name
Test status
Simulation time 140317438 ps
CPU time 0.66 seconds
Started Jul 23 06:04:15 PM PDT 24
Finished Jul 23 06:04:22 PM PDT 24
Peak memory 195464 kb
Host smart-5e245014-afd6-4e0a-9e81-2152bbde4f3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850897271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.850897271
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2947176840
Short name T644
Test name
Test status
Simulation time 108234320 ps
CPU time 2.25 seconds
Started Jul 23 06:04:03 PM PDT 24
Finished Jul 23 06:04:07 PM PDT 24
Peak memory 198336 kb
Host smart-625e6e81-d687-4d79-b0b3-44e666427c23
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947176840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2947176840
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.4167198954
Short name T199
Test name
Test status
Simulation time 363671265 ps
CPU time 2.79 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 197504 kb
Host smart-37a4b99d-cbc3-49bf-8080-f960a245296c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167198954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.4167198954
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1122266622
Short name T564
Test name
Test status
Simulation time 158837788 ps
CPU time 0.75 seconds
Started Jul 23 06:03:55 PM PDT 24
Finished Jul 23 06:03:56 PM PDT 24
Peak memory 195844 kb
Host smart-effe48fa-ad67-4d91-80fd-de8eabe8b1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122266622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1122266622
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.732777174
Short name T486
Test name
Test status
Simulation time 103617915 ps
CPU time 0.83 seconds
Started Jul 23 06:03:55 PM PDT 24
Finished Jul 23 06:03:56 PM PDT 24
Peak memory 197048 kb
Host smart-d3730bb1-65b7-4687-b543-92e99a00d840
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732777174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.732777174
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.734935092
Short name T668
Test name
Test status
Simulation time 2397722570 ps
CPU time 3.57 seconds
Started Jul 23 06:03:56 PM PDT 24
Finished Jul 23 06:04:01 PM PDT 24
Peak memory 198520 kb
Host smart-ab8669ac-c432-45ea-8f51-514a6dc1062f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734935092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ran
dom_long_reg_writes_reg_reads.734935092
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3115579615
Short name T89
Test name
Test status
Simulation time 264900295 ps
CPU time 1.23 seconds
Started Jul 23 06:03:51 PM PDT 24
Finished Jul 23 06:03:54 PM PDT 24
Peak memory 196892 kb
Host smart-cdc6dced-eecc-4dcd-b468-a22c1354cfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115579615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3115579615
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1346175268
Short name T145
Test name
Test status
Simulation time 123694744 ps
CPU time 0.75 seconds
Started Jul 23 06:04:12 PM PDT 24
Finished Jul 23 06:04:14 PM PDT 24
Peak memory 195688 kb
Host smart-038be5a5-5ab2-4849-a28c-6adcfa016c03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346175268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1346175268
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2695786722
Short name T585
Test name
Test status
Simulation time 36657196993 ps
CPU time 98.73 seconds
Started Jul 23 06:04:04 PM PDT 24
Finished Jul 23 06:05:44 PM PDT 24
Peak memory 198548 kb
Host smart-778d5815-4c71-45a6-91fa-5264f9945844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695786722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2695786722
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2252903626
Short name T305
Test name
Test status
Simulation time 11718786 ps
CPU time 0.58 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:13 PM PDT 24
Peak memory 194428 kb
Host smart-2e12e68b-65fb-48f4-a2d1-8669b119e670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252903626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2252903626
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.150170456
Short name T536
Test name
Test status
Simulation time 484994157 ps
CPU time 0.88 seconds
Started Jul 23 06:03:57 PM PDT 24
Finished Jul 23 06:03:59 PM PDT 24
Peak memory 196996 kb
Host smart-539560df-8e48-4114-9195-a497f4c3f094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150170456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.150170456
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.935675797
Short name T139
Test name
Test status
Simulation time 116748352 ps
CPU time 6.03 seconds
Started Jul 23 06:03:51 PM PDT 24
Finished Jul 23 06:03:58 PM PDT 24
Peak memory 196136 kb
Host smart-3ccf3ef0-35a0-43f0-8346-98dc13c38a71
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935675797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.935675797
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3050898382
Short name T591
Test name
Test status
Simulation time 339677008 ps
CPU time 1.08 seconds
Started Jul 23 06:03:51 PM PDT 24
Finished Jul 23 06:03:52 PM PDT 24
Peak memory 196976 kb
Host smart-9ee75852-36cf-4e8b-9676-ca56312d3376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050898382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3050898382
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1489033965
Short name T115
Test name
Test status
Simulation time 166312403 ps
CPU time 1.25 seconds
Started Jul 23 06:03:50 PM PDT 24
Finished Jul 23 06:03:52 PM PDT 24
Peak memory 198520 kb
Host smart-3f9fc1bc-79a9-4e3d-bf06-505499bf9fae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489033965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1489033965
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.647446056
Short name T283
Test name
Test status
Simulation time 137936185 ps
CPU time 3.38 seconds
Started Jul 23 06:04:09 PM PDT 24
Finished Jul 23 06:04:14 PM PDT 24
Peak memory 198564 kb
Host smart-5f7bd67d-21ed-4ef2-8e6f-9095789346bd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647446056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.647446056
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3279365122
Short name T627
Test name
Test status
Simulation time 196908897 ps
CPU time 2.21 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 196328 kb
Host smart-087939c3-7e80-494a-ad7f-962488be4e57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279365122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3279365122
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2385673097
Short name T501
Test name
Test status
Simulation time 51257996 ps
CPU time 0.87 seconds
Started Jul 23 06:03:50 PM PDT 24
Finished Jul 23 06:03:52 PM PDT 24
Peak memory 197732 kb
Host smart-a1039a7a-47cb-4785-91c0-7e0585697e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385673097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2385673097
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3666336510
Short name T662
Test name
Test status
Simulation time 112820743 ps
CPU time 1.08 seconds
Started Jul 23 06:04:09 PM PDT 24
Finished Jul 23 06:04:11 PM PDT 24
Peak memory 196496 kb
Host smart-0dbb81c9-a619-471a-b07b-e5f8f6225e7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666336510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3666336510
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3898508363
Short name T358
Test name
Test status
Simulation time 542833065 ps
CPU time 4.25 seconds
Started Jul 23 06:04:15 PM PDT 24
Finished Jul 23 06:04:21 PM PDT 24
Peak memory 198544 kb
Host smart-9715e4ef-7105-4967-bd07-194b3fee26d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898508363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3898508363
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2020752866
Short name T46
Test name
Test status
Simulation time 161718507 ps
CPU time 1.18 seconds
Started Jul 23 06:03:57 PM PDT 24
Finished Jul 23 06:03:59 PM PDT 24
Peak memory 197124 kb
Host smart-3f131743-5d97-40ad-8ca9-fd72790a801c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020752866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2020752866
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3224323590
Short name T647
Test name
Test status
Simulation time 93214150 ps
CPU time 1.23 seconds
Started Jul 23 06:03:50 PM PDT 24
Finished Jul 23 06:03:52 PM PDT 24
Peak memory 196388 kb
Host smart-73f83d43-906d-40d2-b04a-e8468f132693
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224323590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3224323590
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1190179501
Short name T126
Test name
Test status
Simulation time 7956324979 ps
CPU time 54.93 seconds
Started Jul 23 06:04:04 PM PDT 24
Finished Jul 23 06:05:00 PM PDT 24
Peak memory 198652 kb
Host smart-302292b2-29c2-4587-979d-df666cde4bde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190179501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1190179501
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2636582234
Short name T355
Test name
Test status
Simulation time 235270380377 ps
CPU time 2479.98 seconds
Started Jul 23 06:03:51 PM PDT 24
Finished Jul 23 06:45:12 PM PDT 24
Peak memory 198836 kb
Host smart-98d100a1-ab9b-47bd-91fa-09750ca3470a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2636582234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2636582234
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2667445404
Short name T356
Test name
Test status
Simulation time 14364345 ps
CPU time 0.54 seconds
Started Jul 23 06:04:28 PM PDT 24
Finished Jul 23 06:04:29 PM PDT 24
Peak memory 193232 kb
Host smart-00762376-b715-4e5b-a13b-37d823e2cd2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667445404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2667445404
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1238497827
Short name T448
Test name
Test status
Simulation time 15307184 ps
CPU time 0.69 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 194592 kb
Host smart-e832856d-e3f3-48a9-b59f-5dba4a5e550f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238497827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1238497827
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1861045880
Short name T168
Test name
Test status
Simulation time 555371848 ps
CPU time 27.43 seconds
Started Jul 23 06:04:15 PM PDT 24
Finished Jul 23 06:04:45 PM PDT 24
Peak memory 197244 kb
Host smart-c652c610-23f5-49d4-8647-8842880b5d07
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861045880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1861045880
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1715961993
Short name T533
Test name
Test status
Simulation time 63986120 ps
CPU time 0.59 seconds
Started Jul 23 06:04:13 PM PDT 24
Finished Jul 23 06:04:16 PM PDT 24
Peak memory 194532 kb
Host smart-e9903b07-65b7-4204-a098-ac4ebf79d643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715961993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1715961993
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.239633985
Short name T582
Test name
Test status
Simulation time 43255593 ps
CPU time 0.82 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:13 PM PDT 24
Peak memory 196876 kb
Host smart-e3a29193-59c2-403b-b79a-1752937812e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239633985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.239633985
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2537522889
Short name T348
Test name
Test status
Simulation time 650922531 ps
CPU time 2.82 seconds
Started Jul 23 06:04:14 PM PDT 24
Finished Jul 23 06:04:19 PM PDT 24
Peak memory 196868 kb
Host smart-070701a7-5e69-4f13-8f07-6d54ff39eb1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537522889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2537522889
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2902197039
Short name T581
Test name
Test status
Simulation time 158942047 ps
CPU time 1.81 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:14 PM PDT 24
Peak memory 197380 kb
Host smart-b7bff7d5-e6da-45d0-afcc-e4edff276231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902197039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2902197039
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.263147927
Short name T159
Test name
Test status
Simulation time 23969112 ps
CPU time 0.7 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:09 PM PDT 24
Peak memory 196608 kb
Host smart-74cc4148-8bf6-4231-ac07-5c7b50748883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263147927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.263147927
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3482479638
Short name T185
Test name
Test status
Simulation time 63921382 ps
CPU time 0.76 seconds
Started Jul 23 06:04:09 PM PDT 24
Finished Jul 23 06:04:11 PM PDT 24
Peak memory 196568 kb
Host smart-c5a962d5-65ae-4de5-aba5-573f977a22d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482479638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3482479638
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.381853844
Short name T346
Test name
Test status
Simulation time 564337460 ps
CPU time 6.62 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:15 PM PDT 24
Peak memory 198432 kb
Host smart-37472040-de31-4afe-9627-dc1128c13ce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381853844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ran
dom_long_reg_writes_reg_reads.381853844
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3345867029
Short name T526
Test name
Test status
Simulation time 254514156 ps
CPU time 1.11 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:10 PM PDT 24
Peak memory 196388 kb
Host smart-096e95bd-6ef5-43c1-b9a6-c84eccbfc10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345867029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3345867029
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1110267774
Short name T223
Test name
Test status
Simulation time 45521907 ps
CPU time 0.99 seconds
Started Jul 23 06:03:58 PM PDT 24
Finished Jul 23 06:04:00 PM PDT 24
Peak memory 196036 kb
Host smart-0daab8c0-f085-4ccf-aae7-a44fb867b8f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110267774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1110267774
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1402970842
Short name T712
Test name
Test status
Simulation time 10021623990 ps
CPU time 108.82 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:06:02 PM PDT 24
Peak memory 198644 kb
Host smart-812e7927-ea68-4613-9e4c-3313b3eba39b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402970842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1402970842
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1615849184
Short name T641
Test name
Test status
Simulation time 37361730 ps
CPU time 0.55 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 194620 kb
Host smart-fb1ca8b6-5248-4aae-ba9f-3bde05462879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615849184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1615849184
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.467944180
Short name T143
Test name
Test status
Simulation time 19656374 ps
CPU time 0.66 seconds
Started Jul 23 06:04:09 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 195300 kb
Host smart-5b0a3d9a-c9cb-405e-a069-afa4abd64395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467944180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.467944180
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1890546680
Short name T23
Test name
Test status
Simulation time 2830149879 ps
CPU time 20.99 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:34 PM PDT 24
Peak memory 197944 kb
Host smart-0dbd3f16-476f-4e27-8647-2d04841e6b2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890546680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1890546680
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2001367932
Short name T236
Test name
Test status
Simulation time 74173454 ps
CPU time 0.97 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:10 PM PDT 24
Peak memory 198156 kb
Host smart-aee8ff41-f4f3-4dfe-9486-4c6c7ef50769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001367932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2001367932
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3704959353
Short name T640
Test name
Test status
Simulation time 111709438 ps
CPU time 1.05 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 196540 kb
Host smart-9cd3b636-54cf-4d90-8799-45da8665b625
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704959353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3704959353
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2402342062
Short name T621
Test name
Test status
Simulation time 231257113 ps
CPU time 2.54 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:16 PM PDT 24
Peak memory 198472 kb
Host smart-e7fdfd8d-ea08-4f44-a7c1-a21aa31e2539
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402342062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2402342062
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4282893313
Short name T198
Test name
Test status
Simulation time 1557139818 ps
CPU time 3.34 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:15 PM PDT 24
Peak memory 197600 kb
Host smart-c2da58bc-734b-4571-af28-2eb113232f9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282893313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4282893313
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2317318745
Short name T353
Test name
Test status
Simulation time 40622859 ps
CPU time 1 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:10 PM PDT 24
Peak memory 196524 kb
Host smart-8a2c7e77-1024-4357-ba7a-027ff14c26db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317318745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2317318745
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2654061163
Short name T98
Test name
Test status
Simulation time 44015954 ps
CPU time 1.03 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:10 PM PDT 24
Peak memory 196504 kb
Host smart-d6015c03-1c66-44cc-9a47-39df00cb7894
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654061163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2654061163
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1798440253
Short name T682
Test name
Test status
Simulation time 237862360 ps
CPU time 3.23 seconds
Started Jul 23 06:04:14 PM PDT 24
Finished Jul 23 06:04:19 PM PDT 24
Peak memory 198500 kb
Host smart-7936896e-7aea-4330-b969-9ea6010765ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798440253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1798440253
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1845751291
Short name T171
Test name
Test status
Simulation time 82211880 ps
CPU time 1.48 seconds
Started Jul 23 06:04:05 PM PDT 24
Finished Jul 23 06:04:07 PM PDT 24
Peak memory 196112 kb
Host smart-0ca7463a-ee2c-4bfb-8378-149aa8d8c48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845751291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1845751291
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.367679141
Short name T397
Test name
Test status
Simulation time 176871217 ps
CPU time 1.23 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:04:10 PM PDT 24
Peak memory 197112 kb
Host smart-6cb08bd1-adda-44b8-bfc1-3c6b263c601e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367679141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.367679141
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3193073768
Short name T17
Test name
Test status
Simulation time 5479789034 ps
CPU time 154.12 seconds
Started Jul 23 06:04:08 PM PDT 24
Finished Jul 23 06:06:43 PM PDT 24
Peak memory 198644 kb
Host smart-70d0868d-bc8a-4be6-87c5-9b5b94248ee0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193073768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3193073768
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.2995628539
Short name T56
Test name
Test status
Simulation time 24936237101 ps
CPU time 52.27 seconds
Started Jul 23 06:04:13 PM PDT 24
Finished Jul 23 06:05:06 PM PDT 24
Peak memory 198780 kb
Host smart-340d8bf8-0c36-4c66-a73d-f1f0520d60cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2995628539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.2995628539
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2958213693
Short name T332
Test name
Test status
Simulation time 33910698 ps
CPU time 0.56 seconds
Started Jul 23 06:01:39 PM PDT 24
Finished Jul 23 06:01:41 PM PDT 24
Peak memory 195064 kb
Host smart-3bbf5b42-a882-4397-9647-5f7c15625ec2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958213693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2958213693
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.147800049
Short name T588
Test name
Test status
Simulation time 21490218 ps
CPU time 0.71 seconds
Started Jul 23 06:01:35 PM PDT 24
Finished Jul 23 06:01:37 PM PDT 24
Peak memory 195768 kb
Host smart-3005ecd0-9d5d-40ac-b36b-21bab64c1b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147800049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.147800049
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2633032817
Short name T334
Test name
Test status
Simulation time 857683601 ps
CPU time 15.31 seconds
Started Jul 23 06:01:33 PM PDT 24
Finished Jul 23 06:01:50 PM PDT 24
Peak memory 198512 kb
Host smart-a52e3a5c-5b76-46c3-a48f-ea63ae43ae48
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633032817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2633032817
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3904428564
Short name T177
Test name
Test status
Simulation time 77806360 ps
CPU time 0.7 seconds
Started Jul 23 06:01:35 PM PDT 24
Finished Jul 23 06:01:36 PM PDT 24
Peak memory 195944 kb
Host smart-1dbaa575-409e-49ce-889b-75a90d58e5ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904428564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3904428564
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1075063186
Short name T626
Test name
Test status
Simulation time 36480032 ps
CPU time 0.8 seconds
Started Jul 23 06:01:35 PM PDT 24
Finished Jul 23 06:01:37 PM PDT 24
Peak memory 196608 kb
Host smart-c59cde33-306c-40a6-9c8b-7574472e1ff1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075063186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1075063186
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1802661701
Short name T201
Test name
Test status
Simulation time 78678656 ps
CPU time 3.07 seconds
Started Jul 23 06:01:30 PM PDT 24
Finished Jul 23 06:01:34 PM PDT 24
Peak memory 198228 kb
Host smart-db771cb1-89da-417a-a3d4-6bb0b087b14a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802661701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1802661701
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2850531706
Short name T669
Test name
Test status
Simulation time 45408567 ps
CPU time 0.93 seconds
Started Jul 23 06:01:31 PM PDT 24
Finished Jul 23 06:01:33 PM PDT 24
Peak memory 196576 kb
Host smart-db0e0aae-ea35-4824-bc09-a270ecf49061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850531706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2850531706
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.368578704
Short name T293
Test name
Test status
Simulation time 56307205 ps
CPU time 0.79 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:01:39 PM PDT 24
Peak memory 196572 kb
Host smart-28bf369d-da39-4936-a84b-db88a4ac3eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368578704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.368578704
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2881421372
Short name T308
Test name
Test status
Simulation time 153277540 ps
CPU time 0.9 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:01:34 PM PDT 24
Peak memory 196160 kb
Host smart-b7a937fb-6963-42cc-ab1b-1322b2b8ec25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881421372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2881421372
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2637630389
Short name T150
Test name
Test status
Simulation time 204659602 ps
CPU time 2.7 seconds
Started Jul 23 06:01:36 PM PDT 24
Finished Jul 23 06:01:45 PM PDT 24
Peak memory 198524 kb
Host smart-c987ed92-8867-44f9-8975-ddbc28bc1d2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637630389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2637630389
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1871821537
Short name T35
Test name
Test status
Simulation time 139266231 ps
CPU time 0.76 seconds
Started Jul 23 06:01:39 PM PDT 24
Finished Jul 23 06:01:41 PM PDT 24
Peak memory 214284 kb
Host smart-a0d94a10-b3f4-4226-9f06-aa185130cb4c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871821537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1871821537
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2299039288
Short name T542
Test name
Test status
Simulation time 42620392 ps
CPU time 1.34 seconds
Started Jul 23 06:01:29 PM PDT 24
Finished Jul 23 06:01:32 PM PDT 24
Peak memory 196804 kb
Host smart-c423aa14-7e73-4562-b74e-c224dbc2a9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299039288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2299039288
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1739454469
Short name T227
Test name
Test status
Simulation time 32117562 ps
CPU time 0.99 seconds
Started Jul 23 06:01:30 PM PDT 24
Finished Jul 23 06:01:32 PM PDT 24
Peak memory 196248 kb
Host smart-66f54ab6-6a56-4303-aee0-f9df44e92c7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739454469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1739454469
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1418942735
Short name T18
Test name
Test status
Simulation time 70527762700 ps
CPU time 150.61 seconds
Started Jul 23 06:01:40 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 198648 kb
Host smart-dbc66f4f-acec-4faf-ba9c-9ef6737c0917
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418942735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1418942735
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1308099358
Short name T400
Test name
Test status
Simulation time 320658632217 ps
CPU time 1838.68 seconds
Started Jul 23 06:01:42 PM PDT 24
Finished Jul 23 06:32:22 PM PDT 24
Peak memory 198732 kb
Host smart-68dbb4ff-d49b-40aa-8813-beac59c626c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1308099358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1308099358
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.600549166
Short name T385
Test name
Test status
Simulation time 53379789 ps
CPU time 0.56 seconds
Started Jul 23 06:04:14 PM PDT 24
Finished Jul 23 06:04:17 PM PDT 24
Peak memory 194472 kb
Host smart-a8b42f23-0e0c-4fa7-aad1-484ea21c25cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600549166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.600549166
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1803723631
Short name T340
Test name
Test status
Simulation time 82947683 ps
CPU time 0.7 seconds
Started Jul 23 06:04:27 PM PDT 24
Finished Jul 23 06:04:28 PM PDT 24
Peak memory 196440 kb
Host smart-c97772d7-aeda-4782-89f5-7a95d978b091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803723631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1803723631
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3776656859
Short name T416
Test name
Test status
Simulation time 541288883 ps
CPU time 26.33 seconds
Started Jul 23 06:04:09 PM PDT 24
Finished Jul 23 06:04:36 PM PDT 24
Peak memory 197200 kb
Host smart-7f31e02a-3f6b-42c3-ab8e-e285575a105f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776656859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3776656859
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3946224998
Short name T608
Test name
Test status
Simulation time 86656904 ps
CPU time 0.65 seconds
Started Jul 23 06:04:15 PM PDT 24
Finished Jul 23 06:04:18 PM PDT 24
Peak memory 194980 kb
Host smart-77d40a43-7f27-422b-a393-f72f6a80b11b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946224998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3946224998
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1886929808
Short name T335
Test name
Test status
Simulation time 252733292 ps
CPU time 0.98 seconds
Started Jul 23 06:04:16 PM PDT 24
Finished Jul 23 06:04:19 PM PDT 24
Peak memory 196672 kb
Host smart-db8d9452-e5b4-4630-bc7e-51a9abb65ed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886929808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1886929808
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3313910896
Short name T251
Test name
Test status
Simulation time 237319561 ps
CPU time 2.32 seconds
Started Jul 23 06:04:31 PM PDT 24
Finished Jul 23 06:04:34 PM PDT 24
Peak memory 197748 kb
Host smart-23bbcb34-8da5-4692-ac32-18dbb7890d28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313910896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3313910896
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.21918029
Short name T278
Test name
Test status
Simulation time 684400149 ps
CPU time 2.96 seconds
Started Jul 23 06:04:09 PM PDT 24
Finished Jul 23 06:04:13 PM PDT 24
Peak memory 196364 kb
Host smart-ccb5b538-72f7-4c4b-b9bf-292267ea34ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21918029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger.21918029
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3106579198
Short name T156
Test name
Test status
Simulation time 177329903 ps
CPU time 0.97 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:13 PM PDT 24
Peak memory 196332 kb
Host smart-4ca928b7-c828-4add-b7a9-77f62107d0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106579198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3106579198
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.4205631438
Short name T689
Test name
Test status
Simulation time 195166950 ps
CPU time 0.71 seconds
Started Jul 23 06:04:12 PM PDT 24
Finished Jul 23 06:04:14 PM PDT 24
Peak memory 196572 kb
Host smart-faf99b02-03bf-48ff-923e-5d546a2a9515
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205631438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.4205631438
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2713485544
Short name T125
Test name
Test status
Simulation time 3364605579 ps
CPU time 5.78 seconds
Started Jul 23 06:04:13 PM PDT 24
Finished Jul 23 06:04:21 PM PDT 24
Peak memory 198544 kb
Host smart-bdfeb6f9-5ed9-4872-bd80-2d5275478158
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713485544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2713485544
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1009613787
Short name T488
Test name
Test status
Simulation time 218388343 ps
CPU time 1.26 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:14 PM PDT 24
Peak memory 196328 kb
Host smart-c423d0b6-58b4-4523-9c2e-300bfea98f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009613787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1009613787
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1626221542
Short name T433
Test name
Test status
Simulation time 318775359 ps
CPU time 0.85 seconds
Started Jul 23 06:04:04 PM PDT 24
Finished Jul 23 06:04:06 PM PDT 24
Peak memory 196484 kb
Host smart-96d2397b-8b49-49d4-a746-9b7c28c14531
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626221542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1626221542
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.435216499
Short name T419
Test name
Test status
Simulation time 15879079414 ps
CPU time 142.82 seconds
Started Jul 23 06:04:29 PM PDT 24
Finished Jul 23 06:06:52 PM PDT 24
Peak memory 198644 kb
Host smart-3d2447b1-3557-4db8-bb89-e276a6cc0463
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435216499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.435216499
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1032850555
Short name T55
Test name
Test status
Simulation time 177152784451 ps
CPU time 696.68 seconds
Started Jul 23 06:04:14 PM PDT 24
Finished Jul 23 06:15:53 PM PDT 24
Peak memory 198808 kb
Host smart-ee1e494e-fedd-4d70-864e-7f3c17cf327d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1032850555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1032850555
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3468759015
Short name T663
Test name
Test status
Simulation time 20646776 ps
CPU time 0.59 seconds
Started Jul 23 06:04:31 PM PDT 24
Finished Jul 23 06:04:32 PM PDT 24
Peak memory 194468 kb
Host smart-edf87769-93f1-40f6-b25c-d9af9735253b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468759015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3468759015
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2697274980
Short name T646
Test name
Test status
Simulation time 50256358 ps
CPU time 0.89 seconds
Started Jul 23 06:04:29 PM PDT 24
Finished Jul 23 06:04:31 PM PDT 24
Peak memory 196980 kb
Host smart-b799b686-1c49-43b3-8175-31f7c9ecfce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697274980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2697274980
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.4166816016
Short name T425
Test name
Test status
Simulation time 1077622472 ps
CPU time 18.85 seconds
Started Jul 23 06:04:32 PM PDT 24
Finished Jul 23 06:04:51 PM PDT 24
Peak memory 198480 kb
Host smart-36774ad5-33ec-43a1-b571-77d00703e744
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166816016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.4166816016
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1799055233
Short name T19
Test name
Test status
Simulation time 502262824 ps
CPU time 0.92 seconds
Started Jul 23 06:04:40 PM PDT 24
Finished Jul 23 06:04:42 PM PDT 24
Peak memory 196596 kb
Host smart-a813384a-b622-47b5-918c-056441f919ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799055233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1799055233
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3090971846
Short name T432
Test name
Test status
Simulation time 237652198 ps
CPU time 1.17 seconds
Started Jul 23 06:04:13 PM PDT 24
Finished Jul 23 06:04:17 PM PDT 24
Peak memory 196776 kb
Host smart-bd08328a-a8ab-407b-9e15-a055e48ca3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090971846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3090971846
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.4161298168
Short name T11
Test name
Test status
Simulation time 63229273 ps
CPU time 2.67 seconds
Started Jul 23 06:04:31 PM PDT 24
Finished Jul 23 06:04:34 PM PDT 24
Peak memory 198556 kb
Host smart-cb3583df-ed54-4ce0-8700-933907993479
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161298168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.4161298168
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.10309770
Short name T116
Test name
Test status
Simulation time 148617967 ps
CPU time 2.68 seconds
Started Jul 23 06:04:23 PM PDT 24
Finished Jul 23 06:04:26 PM PDT 24
Peak memory 197676 kb
Host smart-daaebf17-59e8-4a34-a5bd-3188be73a9e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10309770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.10309770
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2813431977
Short name T388
Test name
Test status
Simulation time 1012496505 ps
CPU time 1.33 seconds
Started Jul 23 06:04:11 PM PDT 24
Finished Jul 23 06:04:15 PM PDT 24
Peak memory 197436 kb
Host smart-45bc8a13-f04c-4417-8f4b-546702bbbdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813431977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2813431977
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1015338514
Short name T231
Test name
Test status
Simulation time 23958836 ps
CPU time 0.66 seconds
Started Jul 23 06:04:37 PM PDT 24
Finished Jul 23 06:04:38 PM PDT 24
Peak memory 194772 kb
Host smart-d728a04f-8bd7-415d-b665-0d966c874fc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015338514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1015338514
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1515820829
Short name T239
Test name
Test status
Simulation time 1153401719 ps
CPU time 4.74 seconds
Started Jul 23 06:04:12 PM PDT 24
Finished Jul 23 06:04:18 PM PDT 24
Peak memory 198456 kb
Host smart-de0ada14-e4a3-4f65-a3ce-9cef54b25f57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515820829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1515820829
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.742798047
Short name T498
Test name
Test status
Simulation time 108039962 ps
CPU time 0.83 seconds
Started Jul 23 06:04:19 PM PDT 24
Finished Jul 23 06:04:21 PM PDT 24
Peak memory 196908 kb
Host smart-de7c9ce8-8b90-477a-be18-833642ccc8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742798047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.742798047
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3876253253
Short name T379
Test name
Test status
Simulation time 39279563 ps
CPU time 1.12 seconds
Started Jul 23 06:04:15 PM PDT 24
Finished Jul 23 06:04:18 PM PDT 24
Peak memory 196168 kb
Host smart-7f81c146-544b-4149-bbe7-57b6d09bcb5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876253253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3876253253
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2114284472
Short name T691
Test name
Test status
Simulation time 5997221970 ps
CPU time 130.22 seconds
Started Jul 23 06:04:24 PM PDT 24
Finished Jul 23 06:06:35 PM PDT 24
Peak memory 198652 kb
Host smart-73109407-5503-475c-b342-4199f8e7289d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114284472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2114284472
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.812825647
Short name T399
Test name
Test status
Simulation time 20274805 ps
CPU time 0.58 seconds
Started Jul 23 06:04:12 PM PDT 24
Finished Jul 23 06:04:14 PM PDT 24
Peak memory 195428 kb
Host smart-70a04d36-6a78-463c-996a-29dbacb6bf62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812825647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.812825647
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.273555483
Short name T675
Test name
Test status
Simulation time 54406118 ps
CPU time 0.65 seconds
Started Jul 23 06:04:15 PM PDT 24
Finished Jul 23 06:04:17 PM PDT 24
Peak memory 195344 kb
Host smart-d5724dae-dfc1-4ead-8f6c-42d6fe0e17ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273555483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.273555483
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.874936733
Short name T123
Test name
Test status
Simulation time 536322371 ps
CPU time 8.27 seconds
Started Jul 23 06:04:23 PM PDT 24
Finished Jul 23 06:04:32 PM PDT 24
Peak memory 196812 kb
Host smart-17a2f0ab-97d4-4244-8bc7-cad52c0dfc91
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874936733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.874936733
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1728815170
Short name T684
Test name
Test status
Simulation time 62640243 ps
CPU time 0.96 seconds
Started Jul 23 06:04:17 PM PDT 24
Finished Jul 23 06:04:19 PM PDT 24
Peak memory 197764 kb
Host smart-b2cfb826-12ea-49b1-b31f-f2f05922014a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728815170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1728815170
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2326905161
Short name T272
Test name
Test status
Simulation time 629421256 ps
CPU time 1.32 seconds
Started Jul 23 06:04:13 PM PDT 24
Finished Jul 23 06:04:16 PM PDT 24
Peak memory 198620 kb
Host smart-ab15cea4-9744-46eb-8907-15dba58587fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326905161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2326905161
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.4127922377
Short name T630
Test name
Test status
Simulation time 306736156 ps
CPU time 3.07 seconds
Started Jul 23 06:04:15 PM PDT 24
Finished Jul 23 06:04:20 PM PDT 24
Peak memory 198616 kb
Host smart-1b24adb9-e052-402d-84dd-d39ac703a284
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127922377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.4127922377
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1064615800
Short name T503
Test name
Test status
Simulation time 127171310 ps
CPU time 2.56 seconds
Started Jul 23 06:04:14 PM PDT 24
Finished Jul 23 06:04:19 PM PDT 24
Peak memory 198568 kb
Host smart-2892ecf1-f20b-4bcf-a9f6-37be2b718ae2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064615800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1064615800
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2192501696
Short name T698
Test name
Test status
Simulation time 174814627 ps
CPU time 1.02 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:13 PM PDT 24
Peak memory 196560 kb
Host smart-daad0c6e-5415-4337-8f06-df69b61fad1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192501696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2192501696
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.44535982
Short name T652
Test name
Test status
Simulation time 104736257 ps
CPU time 0.97 seconds
Started Jul 23 06:04:10 PM PDT 24
Finished Jul 23 06:04:12 PM PDT 24
Peak memory 196368 kb
Host smart-0362e138-ea71-4878-b1a6-c3361f2d246f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44535982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup_
pulldown.44535982
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.992322584
Short name T570
Test name
Test status
Simulation time 92979629 ps
CPU time 1.73 seconds
Started Jul 23 06:04:25 PM PDT 24
Finished Jul 23 06:04:28 PM PDT 24
Peak memory 198488 kb
Host smart-b23dedc1-6173-4f48-a13c-fb74c8cd31c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992322584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.992322584
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1390678693
Short name T320
Test name
Test status
Simulation time 135086576 ps
CPU time 0.94 seconds
Started Jul 23 06:04:48 PM PDT 24
Finished Jul 23 06:04:49 PM PDT 24
Peak memory 197020 kb
Host smart-a76d12ed-0080-48d9-87f8-1a7e1e96812c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390678693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1390678693
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.4287643
Short name T93
Test name
Test status
Simulation time 45111609 ps
CPU time 0.91 seconds
Started Jul 23 06:04:07 PM PDT 24
Finished Jul 23 06:04:08 PM PDT 24
Peak memory 197604 kb
Host smart-e03a0dff-b1db-4c46-860e-9a391c3e4cb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.4287643
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3234370406
Short name T480
Test name
Test status
Simulation time 49583920740 ps
CPU time 84.21 seconds
Started Jul 23 06:04:20 PM PDT 24
Finished Jul 23 06:05:45 PM PDT 24
Peak memory 198664 kb
Host smart-5de6933b-1739-46ef-96a4-cbee3bf7a914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234370406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3234370406
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3999448337
Short name T401
Test name
Test status
Simulation time 262392656213 ps
CPU time 945.81 seconds
Started Jul 23 06:04:24 PM PDT 24
Finished Jul 23 06:20:10 PM PDT 24
Peak memory 198788 kb
Host smart-dcec340d-1d59-414b-84ee-03b40e7e3515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3999448337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3999448337
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1430311729
Short name T170
Test name
Test status
Simulation time 15221551 ps
CPU time 0.59 seconds
Started Jul 23 06:04:46 PM PDT 24
Finished Jul 23 06:04:47 PM PDT 24
Peak memory 194660 kb
Host smart-82b7789a-a3d4-4314-82ad-1729fef195c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430311729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1430311729
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2536202896
Short name T180
Test name
Test status
Simulation time 81899169 ps
CPU time 0.91 seconds
Started Jul 23 06:04:46 PM PDT 24
Finished Jul 23 06:04:48 PM PDT 24
Peak memory 197020 kb
Host smart-2a760240-8faf-4909-8603-952f07b37416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536202896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2536202896
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1198328299
Short name T274
Test name
Test status
Simulation time 1042328739 ps
CPU time 12.52 seconds
Started Jul 23 06:04:46 PM PDT 24
Finished Jul 23 06:05:00 PM PDT 24
Peak memory 197444 kb
Host smart-0821e97a-1bca-4882-967e-f481450f9e5a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198328299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1198328299
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2626279456
Short name T5
Test name
Test status
Simulation time 81126805 ps
CPU time 1.02 seconds
Started Jul 23 06:04:39 PM PDT 24
Finished Jul 23 06:04:40 PM PDT 24
Peak memory 198408 kb
Host smart-29191933-63b9-4a26-8414-b9995fd9c6ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626279456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2626279456
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4105868226
Short name T409
Test name
Test status
Simulation time 39585396 ps
CPU time 0.82 seconds
Started Jul 23 06:04:22 PM PDT 24
Finished Jul 23 06:04:23 PM PDT 24
Peak memory 196816 kb
Host smart-579c9634-07d6-4256-b630-d97edb71547b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105868226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4105868226
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.792754516
Short name T558
Test name
Test status
Simulation time 34430245 ps
CPU time 1.46 seconds
Started Jul 23 06:04:31 PM PDT 24
Finished Jul 23 06:04:33 PM PDT 24
Peak memory 197012 kb
Host smart-6367c317-137e-4a91-9ca8-c6ac779a0ad2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792754516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.792754516
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4210566087
Short name T467
Test name
Test status
Simulation time 198785928 ps
CPU time 1.64 seconds
Started Jul 23 06:04:21 PM PDT 24
Finished Jul 23 06:04:23 PM PDT 24
Peak memory 196348 kb
Host smart-f499ae3d-a07e-4ba9-b0b9-7b96394e86be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210566087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4210566087
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2878824738
Short name T157
Test name
Test status
Simulation time 31430109 ps
CPU time 0.75 seconds
Started Jul 23 06:04:29 PM PDT 24
Finished Jul 23 06:04:30 PM PDT 24
Peak memory 195888 kb
Host smart-7b2168d1-38e1-4a1d-ab49-a02838d4ccbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878824738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2878824738
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2910760286
Short name T443
Test name
Test status
Simulation time 391401728 ps
CPU time 0.9 seconds
Started Jul 23 06:04:29 PM PDT 24
Finished Jul 23 06:04:31 PM PDT 24
Peak memory 197256 kb
Host smart-8d195f82-089f-471f-921a-6a273026d252
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910760286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2910760286
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3753371367
Short name T403
Test name
Test status
Simulation time 1434678349 ps
CPU time 6.03 seconds
Started Jul 23 06:04:27 PM PDT 24
Finished Jul 23 06:04:34 PM PDT 24
Peak memory 198508 kb
Host smart-e9bedd02-f8b8-43d7-bf5b-6eae817be74c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753371367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3753371367
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1660962952
Short name T471
Test name
Test status
Simulation time 27716078 ps
CPU time 1.01 seconds
Started Jul 23 06:04:26 PM PDT 24
Finished Jul 23 06:04:28 PM PDT 24
Peak memory 196024 kb
Host smart-e941b1e1-4140-42d7-80d3-0f4fd3244f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660962952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1660962952
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1501039471
Short name T707
Test name
Test status
Simulation time 233175725 ps
CPU time 1.21 seconds
Started Jul 23 06:04:35 PM PDT 24
Finished Jul 23 06:04:36 PM PDT 24
Peak memory 196348 kb
Host smart-5b7abbc0-c7b2-41c3-85ff-5f9159557565
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501039471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1501039471
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.2714976286
Short name T6
Test name
Test status
Simulation time 3522953607 ps
CPU time 37.17 seconds
Started Jul 23 06:04:45 PM PDT 24
Finished Jul 23 06:05:23 PM PDT 24
Peak memory 198668 kb
Host smart-0f9a25a6-7ab8-4c6f-b158-43e3a09810a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714976286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.2714976286
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.331244643
Short name T497
Test name
Test status
Simulation time 15753950 ps
CPU time 0.63 seconds
Started Jul 23 06:04:40 PM PDT 24
Finished Jul 23 06:04:41 PM PDT 24
Peak memory 194640 kb
Host smart-3bd01cf6-d389-4148-807e-3fa9a373cdf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331244643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.331244643
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3791583209
Short name T380
Test name
Test status
Simulation time 45111849 ps
CPU time 0.91 seconds
Started Jul 23 06:04:26 PM PDT 24
Finished Jul 23 06:04:27 PM PDT 24
Peak memory 196932 kb
Host smart-89dd43dc-9c90-42a5-b893-358ad0a886a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791583209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3791583209
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.962633148
Short name T175
Test name
Test status
Simulation time 7378135320 ps
CPU time 26.5 seconds
Started Jul 23 06:04:35 PM PDT 24
Finished Jul 23 06:05:02 PM PDT 24
Peak memory 197360 kb
Host smart-b70a2fc4-ee74-4323-b04a-52d77516e4a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962633148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.962633148
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1722439505
Short name T515
Test name
Test status
Simulation time 53722604 ps
CPU time 0.82 seconds
Started Jul 23 06:04:40 PM PDT 24
Finished Jul 23 06:04:41 PM PDT 24
Peak memory 196408 kb
Host smart-f547ba0c-acb7-4ffb-8c82-58c1a64933d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722439505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1722439505
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2969659491
Short name T579
Test name
Test status
Simulation time 236526204 ps
CPU time 1.05 seconds
Started Jul 23 06:04:32 PM PDT 24
Finished Jul 23 06:04:34 PM PDT 24
Peak memory 197240 kb
Host smart-a3383b90-4cf3-4bdc-b053-1dee6e625b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969659491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2969659491
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1299612522
Short name T120
Test name
Test status
Simulation time 154401548 ps
CPU time 3.02 seconds
Started Jul 23 06:04:39 PM PDT 24
Finished Jul 23 06:04:43 PM PDT 24
Peak memory 198488 kb
Host smart-18073dae-1355-47fc-82e4-e5bb397bda9e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299612522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1299612522
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.35690664
Short name T643
Test name
Test status
Simulation time 267883561 ps
CPU time 2.16 seconds
Started Jul 23 06:04:28 PM PDT 24
Finished Jul 23 06:04:30 PM PDT 24
Peak memory 196348 kb
Host smart-9382d2b7-853c-4069-a1bf-099ab6a428a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35690664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.35690664
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2615159156
Short name T697
Test name
Test status
Simulation time 218637122 ps
CPU time 1.15 seconds
Started Jul 23 06:04:41 PM PDT 24
Finished Jul 23 06:04:43 PM PDT 24
Peak memory 197208 kb
Host smart-d927c169-cabb-424e-91be-e46501c22675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615159156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2615159156
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3756261197
Short name T445
Test name
Test status
Simulation time 140632949 ps
CPU time 1.33 seconds
Started Jul 23 06:04:37 PM PDT 24
Finished Jul 23 06:04:38 PM PDT 24
Peak memory 197164 kb
Host smart-20cf6c5a-507c-4c69-afa4-d4ce1d1bcc31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756261197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3756261197
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2718363431
Short name T408
Test name
Test status
Simulation time 69576195 ps
CPU time 2.97 seconds
Started Jul 23 06:04:36 PM PDT 24
Finished Jul 23 06:04:40 PM PDT 24
Peak memory 198324 kb
Host smart-603a4945-ee20-4815-b252-0e8b18ef62b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718363431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2718363431
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.4022522458
Short name T15
Test name
Test status
Simulation time 613062927 ps
CPU time 1.25 seconds
Started Jul 23 06:04:30 PM PDT 24
Finished Jul 23 06:04:32 PM PDT 24
Peak memory 196988 kb
Host smart-1d863905-c706-4989-9014-c481a4082699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022522458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.4022522458
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2731586877
Short name T345
Test name
Test status
Simulation time 44508349 ps
CPU time 0.93 seconds
Started Jul 23 06:04:54 PM PDT 24
Finished Jul 23 06:04:56 PM PDT 24
Peak memory 196572 kb
Host smart-2f2d8d35-01ae-49d4-a881-c3406f4fde34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731586877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2731586877
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1490790724
Short name T206
Test name
Test status
Simulation time 21158943086 ps
CPU time 142.49 seconds
Started Jul 23 06:04:24 PM PDT 24
Finished Jul 23 06:06:47 PM PDT 24
Peak memory 198644 kb
Host smart-ab9404c3-ed8d-492f-abf6-556515a2824c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490790724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1490790724
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.4226420440
Short name T421
Test name
Test status
Simulation time 70327487139 ps
CPU time 1640.38 seconds
Started Jul 23 06:04:24 PM PDT 24
Finished Jul 23 06:31:45 PM PDT 24
Peak memory 198728 kb
Host smart-fed4a007-0273-46f3-842e-321a00087a77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4226420440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.4226420440
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3277178734
Short name T246
Test name
Test status
Simulation time 14367288 ps
CPU time 0.59 seconds
Started Jul 23 06:04:41 PM PDT 24
Finished Jul 23 06:04:47 PM PDT 24
Peak memory 194596 kb
Host smart-279d8d2f-38b1-4441-bf32-7195fcc2e1ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277178734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3277178734
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.863488800
Short name T290
Test name
Test status
Simulation time 80550016 ps
CPU time 0.72 seconds
Started Jul 23 06:04:43 PM PDT 24
Finished Jul 23 06:04:44 PM PDT 24
Peak memory 194632 kb
Host smart-456c7480-e5ed-4273-b462-70adefb75357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863488800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.863488800
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3838660206
Short name T527
Test name
Test status
Simulation time 83662370 ps
CPU time 4.46 seconds
Started Jul 23 06:04:50 PM PDT 24
Finished Jul 23 06:04:55 PM PDT 24
Peak memory 196444 kb
Host smart-5780336d-8afb-4d39-bc7f-2e2d97856aee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838660206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3838660206
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1793026008
Short name T265
Test name
Test status
Simulation time 209944763 ps
CPU time 0.95 seconds
Started Jul 23 06:04:57 PM PDT 24
Finished Jul 23 06:04:59 PM PDT 24
Peak memory 197104 kb
Host smart-3ce12c75-80df-490d-9658-4b253612ea3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793026008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1793026008
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.2980016281
Short name T341
Test name
Test status
Simulation time 44749640 ps
CPU time 0.87 seconds
Started Jul 23 06:04:46 PM PDT 24
Finished Jul 23 06:04:48 PM PDT 24
Peak memory 196216 kb
Host smart-cc0aa295-949c-4ae1-800b-f3553c9a8f7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980016281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.2980016281
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1363344402
Short name T457
Test name
Test status
Simulation time 208870767 ps
CPU time 2.3 seconds
Started Jul 23 06:04:47 PM PDT 24
Finished Jul 23 06:04:51 PM PDT 24
Peak memory 198652 kb
Host smart-21ac9b5f-17ba-4b9f-be15-cc6d1da721fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363344402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1363344402
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1836792155
Short name T637
Test name
Test status
Simulation time 268880244 ps
CPU time 2.05 seconds
Started Jul 23 06:04:39 PM PDT 24
Finished Jul 23 06:04:42 PM PDT 24
Peak memory 197392 kb
Host smart-27b3d047-3827-4470-b5db-0afa6c91d044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836792155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1836792155
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1076374457
Short name T473
Test name
Test status
Simulation time 56971098 ps
CPU time 1.17 seconds
Started Jul 23 06:04:32 PM PDT 24
Finished Jul 23 06:04:34 PM PDT 24
Peak memory 196472 kb
Host smart-15378027-8311-4f32-addb-2e4ceb4981f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076374457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1076374457
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.999794019
Short name T710
Test name
Test status
Simulation time 244475478 ps
CPU time 1.24 seconds
Started Jul 23 06:04:30 PM PDT 24
Finished Jul 23 06:04:32 PM PDT 24
Peak memory 197632 kb
Host smart-c9ee52b7-70b3-4a7a-ab35-bb8352135472
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999794019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.999794019
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3535245417
Short name T463
Test name
Test status
Simulation time 498268449 ps
CPU time 3.01 seconds
Started Jul 23 06:04:33 PM PDT 24
Finished Jul 23 06:04:37 PM PDT 24
Peak memory 198476 kb
Host smart-9c9d31bc-a43f-4473-a663-219cee4bfb19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535245417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3535245417
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2045564370
Short name T164
Test name
Test status
Simulation time 57596296 ps
CPU time 1.07 seconds
Started Jul 23 06:04:28 PM PDT 24
Finished Jul 23 06:04:30 PM PDT 24
Peak memory 196096 kb
Host smart-ce2a5d78-3442-4d36-8c00-7cb587e58bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045564370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2045564370
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1031527384
Short name T703
Test name
Test status
Simulation time 56178015 ps
CPU time 1.06 seconds
Started Jul 23 06:04:52 PM PDT 24
Finished Jul 23 06:04:54 PM PDT 24
Peak memory 196772 kb
Host smart-fb27b98b-efcb-4713-897a-ec85832ad71f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031527384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1031527384
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2672293713
Short name T202
Test name
Test status
Simulation time 7463305396 ps
CPU time 102.5 seconds
Started Jul 23 06:04:42 PM PDT 24
Finished Jul 23 06:06:25 PM PDT 24
Peak memory 198584 kb
Host smart-c813d737-cec5-41bb-b385-019fb2cbc015
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672293713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2672293713
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1686597217
Short name T36
Test name
Test status
Simulation time 24460378 ps
CPU time 0.59 seconds
Started Jul 23 06:04:48 PM PDT 24
Finished Jul 23 06:04:49 PM PDT 24
Peak memory 194648 kb
Host smart-ede128f5-2b6d-4f9d-9fa3-748f71aa4a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686597217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1686597217
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.606743380
Short name T240
Test name
Test status
Simulation time 43988147 ps
CPU time 0.86 seconds
Started Jul 23 06:04:44 PM PDT 24
Finished Jul 23 06:04:45 PM PDT 24
Peak memory 197800 kb
Host smart-eab2b9d9-9da2-4d9b-a92d-56c303058537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606743380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.606743380
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3078486361
Short name T350
Test name
Test status
Simulation time 165775990 ps
CPU time 5.94 seconds
Started Jul 23 06:04:42 PM PDT 24
Finished Jul 23 06:04:49 PM PDT 24
Peak memory 197496 kb
Host smart-2da3b6e5-48e1-447f-b6af-fd048831ac77
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078486361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3078486361
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.394469991
Short name T620
Test name
Test status
Simulation time 52944227 ps
CPU time 0.95 seconds
Started Jul 23 06:04:51 PM PDT 24
Finished Jul 23 06:04:52 PM PDT 24
Peak memory 197520 kb
Host smart-75a208a1-ed15-43a7-ba67-9ed54a82a467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394469991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.394469991
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.4051991584
Short name T238
Test name
Test status
Simulation time 418896382 ps
CPU time 1.14 seconds
Started Jul 23 06:04:41 PM PDT 24
Finished Jul 23 06:04:43 PM PDT 24
Peak memory 196584 kb
Host smart-89565eb7-38c5-4299-a2fe-4408d18589d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051991584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.4051991584
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3212001579
Short name T103
Test name
Test status
Simulation time 56692715 ps
CPU time 1.26 seconds
Started Jul 23 06:04:45 PM PDT 24
Finished Jul 23 06:04:47 PM PDT 24
Peak memory 197228 kb
Host smart-2a67a707-2e9d-42cb-b43f-f01ad0319975
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212001579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3212001579
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1777832912
Short name T551
Test name
Test status
Simulation time 459971797 ps
CPU time 3.2 seconds
Started Jul 23 06:04:44 PM PDT 24
Finished Jul 23 06:04:48 PM PDT 24
Peak memory 197580 kb
Host smart-89a92bd9-e327-4073-a424-ea5820bb658d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777832912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1777832912
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.70599752
Short name T148
Test name
Test status
Simulation time 75008735 ps
CPU time 1.34 seconds
Started Jul 23 06:04:36 PM PDT 24
Finished Jul 23 06:04:38 PM PDT 24
Peak memory 197588 kb
Host smart-f0f0ad06-e02b-4c17-bd6e-03bcb817b630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70599752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.70599752
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1907868685
Short name T622
Test name
Test status
Simulation time 54618644 ps
CPU time 1.1 seconds
Started Jul 23 06:04:41 PM PDT 24
Finished Jul 23 06:04:43 PM PDT 24
Peak memory 196400 kb
Host smart-9775f719-7cdc-47d0-8a9d-496d8c2998f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907868685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1907868685
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1178847390
Short name T431
Test name
Test status
Simulation time 105789950 ps
CPU time 2.53 seconds
Started Jul 23 06:04:48 PM PDT 24
Finished Jul 23 06:04:52 PM PDT 24
Peak memory 198432 kb
Host smart-206e7ff1-c6c5-4adf-bc78-5c1309f7b603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178847390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1178847390
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.371689610
Short name T122
Test name
Test status
Simulation time 42319443 ps
CPU time 0.81 seconds
Started Jul 23 06:04:45 PM PDT 24
Finished Jul 23 06:04:47 PM PDT 24
Peak memory 195832 kb
Host smart-826de3aa-bf55-4c15-a1d3-4e5b6bd812d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371689610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.371689610
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3422875700
Short name T160
Test name
Test status
Simulation time 36045734 ps
CPU time 0.86 seconds
Started Jul 23 06:04:46 PM PDT 24
Finished Jul 23 06:04:48 PM PDT 24
Peak memory 196600 kb
Host smart-158e1166-c661-49e0-a83a-28b9c20dd29b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422875700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3422875700
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1150512480
Short name T592
Test name
Test status
Simulation time 2436190438 ps
CPU time 58.39 seconds
Started Jul 23 06:04:57 PM PDT 24
Finished Jul 23 06:05:56 PM PDT 24
Peak memory 198604 kb
Host smart-a19c87e8-3f81-4b3e-b3af-3f75077e235e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150512480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1150512480
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3537249235
Short name T54
Test name
Test status
Simulation time 243707374085 ps
CPU time 1537.38 seconds
Started Jul 23 06:05:00 PM PDT 24
Finished Jul 23 06:30:38 PM PDT 24
Peak memory 206956 kb
Host smart-04a55353-1015-4261-9f43-58a339c61221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3537249235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3537249235
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.72419795
Short name T611
Test name
Test status
Simulation time 13349808 ps
CPU time 0.58 seconds
Started Jul 23 06:04:49 PM PDT 24
Finished Jul 23 06:04:51 PM PDT 24
Peak memory 195144 kb
Host smart-0570680d-bd45-4b42-9918-b29d117e6d28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72419795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.72419795
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.155444709
Short name T530
Test name
Test status
Simulation time 20235294 ps
CPU time 0.69 seconds
Started Jul 23 06:04:50 PM PDT 24
Finished Jul 23 06:04:51 PM PDT 24
Peak memory 194708 kb
Host smart-7a43d898-fd9f-4664-abf5-cbdf48e95df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155444709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.155444709
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1427181922
Short name T666
Test name
Test status
Simulation time 1171258632 ps
CPU time 12.39 seconds
Started Jul 23 06:04:59 PM PDT 24
Finished Jul 23 06:05:12 PM PDT 24
Peak memory 197664 kb
Host smart-6789d57b-9b15-4fea-b721-db9fdb99f79c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427181922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1427181922
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1136664133
Short name T95
Test name
Test status
Simulation time 132944507 ps
CPU time 0.98 seconds
Started Jul 23 06:04:54 PM PDT 24
Finished Jul 23 06:04:55 PM PDT 24
Peak memory 197340 kb
Host smart-e090b436-54b3-441b-860d-83aa44dff242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136664133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1136664133
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3874077259
Short name T211
Test name
Test status
Simulation time 137764522 ps
CPU time 1.05 seconds
Started Jul 23 06:05:04 PM PDT 24
Finished Jul 23 06:05:06 PM PDT 24
Peak memory 196532 kb
Host smart-e195f6d8-3450-4bed-8537-2dba397bf2e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874077259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3874077259
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.870267346
Short name T423
Test name
Test status
Simulation time 77055260 ps
CPU time 2.91 seconds
Started Jul 23 06:04:56 PM PDT 24
Finished Jul 23 06:04:59 PM PDT 24
Peak memory 198592 kb
Host smart-9ad69a5b-c7da-4a2d-9ecb-ab9b061e5b1f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870267346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.870267346
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2791229418
Short name T618
Test name
Test status
Simulation time 67543804 ps
CPU time 0.99 seconds
Started Jul 23 06:04:56 PM PDT 24
Finished Jul 23 06:04:57 PM PDT 24
Peak memory 196044 kb
Host smart-5fae71ea-c442-44b8-b94c-b3f0eaf94b04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791229418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2791229418
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.660070464
Short name T204
Test name
Test status
Simulation time 31373772 ps
CPU time 1.12 seconds
Started Jul 23 06:04:47 PM PDT 24
Finished Jul 23 06:04:50 PM PDT 24
Peak memory 197340 kb
Host smart-80c67484-15c7-4961-95fc-6b037a1dcf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660070464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.660070464
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1904558193
Short name T653
Test name
Test status
Simulation time 38134297 ps
CPU time 0.81 seconds
Started Jul 23 06:04:57 PM PDT 24
Finished Jul 23 06:04:59 PM PDT 24
Peak memory 196732 kb
Host smart-05534f67-5b0e-4723-92f2-c3b62258256f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904558193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1904558193
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.4235095144
Short name T465
Test name
Test status
Simulation time 754287236 ps
CPU time 2.9 seconds
Started Jul 23 06:04:50 PM PDT 24
Finished Jul 23 06:04:54 PM PDT 24
Peak memory 198344 kb
Host smart-deb9482c-c9b6-4e47-8b88-40c06fea11fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235095144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.4235095144
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3380641532
Short name T209
Test name
Test status
Simulation time 77485675 ps
CPU time 0.92 seconds
Started Jul 23 06:04:47 PM PDT 24
Finished Jul 23 06:04:49 PM PDT 24
Peak memory 197044 kb
Host smart-ccf119b3-ea1d-4879-b9d6-b71022be6fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380641532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3380641532
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.857755049
Short name T184
Test name
Test status
Simulation time 101556586 ps
CPU time 1.11 seconds
Started Jul 23 06:04:59 PM PDT 24
Finished Jul 23 06:05:01 PM PDT 24
Peak memory 196184 kb
Host smart-62141737-b5b1-4fea-a44f-7b676f748307
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857755049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.857755049
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3803920333
Short name T505
Test name
Test status
Simulation time 6332742061 ps
CPU time 163.72 seconds
Started Jul 23 06:04:54 PM PDT 24
Finished Jul 23 06:07:38 PM PDT 24
Peak memory 198656 kb
Host smart-abcb6dc6-3219-4be3-bb41-d80ee0517264
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803920333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3803920333
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1576562194
Short name T619
Test name
Test status
Simulation time 48842409282 ps
CPU time 212.55 seconds
Started Jul 23 06:04:50 PM PDT 24
Finished Jul 23 06:08:24 PM PDT 24
Peak memory 206904 kb
Host smart-f01dd2d0-7646-4b58-aef4-1d20f691c74f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1576562194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1576562194
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.716800451
Short name T218
Test name
Test status
Simulation time 14414743 ps
CPU time 0.57 seconds
Started Jul 23 06:05:08 PM PDT 24
Finished Jul 23 06:05:09 PM PDT 24
Peak memory 194444 kb
Host smart-cbe86c50-dc6d-4553-9d1c-47d2de7aa290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716800451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.716800451
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1480385072
Short name T572
Test name
Test status
Simulation time 16581924 ps
CPU time 0.65 seconds
Started Jul 23 06:05:00 PM PDT 24
Finished Jul 23 06:05:02 PM PDT 24
Peak memory 195228 kb
Host smart-d2d69781-60a7-4c3e-9e02-885fd9ac8d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480385072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1480385072
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1515568333
Short name T390
Test name
Test status
Simulation time 294847688 ps
CPU time 15.28 seconds
Started Jul 23 06:04:45 PM PDT 24
Finished Jul 23 06:05:02 PM PDT 24
Peak memory 198504 kb
Host smart-83b812f6-0e0a-4093-9573-dc6ed22ab0db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515568333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1515568333
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1751070265
Short name T600
Test name
Test status
Simulation time 86666680 ps
CPU time 0.79 seconds
Started Jul 23 06:05:01 PM PDT 24
Finished Jul 23 06:05:03 PM PDT 24
Peak memory 197072 kb
Host smart-515d7dcd-d267-47ba-bf15-f8f8398b5f1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751070265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1751070265
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1445015175
Short name T625
Test name
Test status
Simulation time 105213744 ps
CPU time 0.74 seconds
Started Jul 23 06:05:02 PM PDT 24
Finished Jul 23 06:05:03 PM PDT 24
Peak memory 195900 kb
Host smart-1d9e8b5d-6b7d-4165-a756-f4474693f480
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445015175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1445015175
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3487034795
Short name T685
Test name
Test status
Simulation time 87643218 ps
CPU time 1.08 seconds
Started Jul 23 06:04:47 PM PDT 24
Finished Jul 23 06:04:49 PM PDT 24
Peak memory 197572 kb
Host smart-60a3baaf-9226-4999-b424-5e99c2ff3f0f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487034795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3487034795
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1738428115
Short name T382
Test name
Test status
Simulation time 280270291 ps
CPU time 3.5 seconds
Started Jul 23 06:05:02 PM PDT 24
Finished Jul 23 06:05:06 PM PDT 24
Peak memory 197644 kb
Host smart-959a9cfd-7151-4c1d-9703-4a2b4334dffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738428115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1738428115
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1290125140
Short name T700
Test name
Test status
Simulation time 124966139 ps
CPU time 0.65 seconds
Started Jul 23 06:04:58 PM PDT 24
Finished Jul 23 06:05:00 PM PDT 24
Peak memory 194800 kb
Host smart-36d14584-b7f8-470a-a077-ad960ebe2f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290125140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1290125140
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2316165252
Short name T134
Test name
Test status
Simulation time 60239555 ps
CPU time 1.15 seconds
Started Jul 23 06:05:04 PM PDT 24
Finished Jul 23 06:05:07 PM PDT 24
Peak memory 197140 kb
Host smart-8a11ea6b-e658-4ee2-83ef-508e3de4e07b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316165252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2316165252
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1417566149
Short name T428
Test name
Test status
Simulation time 443137018 ps
CPU time 5.74 seconds
Started Jul 23 06:05:00 PM PDT 24
Finished Jul 23 06:05:07 PM PDT 24
Peak memory 198496 kb
Host smart-9e94f5eb-96c6-4ac8-beca-2f6d9deff95e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417566149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1417566149
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3944418734
Short name T540
Test name
Test status
Simulation time 282652383 ps
CPU time 1.28 seconds
Started Jul 23 06:04:56 PM PDT 24
Finished Jul 23 06:04:58 PM PDT 24
Peak memory 197320 kb
Host smart-b29b9031-47c2-4c1b-8da5-b1e1bf189749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944418734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3944418734
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3927000802
Short name T695
Test name
Test status
Simulation time 82023686 ps
CPU time 1.52 seconds
Started Jul 23 06:05:02 PM PDT 24
Finished Jul 23 06:05:05 PM PDT 24
Peak memory 197268 kb
Host smart-8d56f3ad-c6e4-4f04-817c-468e036437ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927000802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3927000802
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1539760379
Short name T328
Test name
Test status
Simulation time 8774979963 ps
CPU time 124.22 seconds
Started Jul 23 06:04:52 PM PDT 24
Finished Jul 23 06:06:57 PM PDT 24
Peak memory 198656 kb
Host smart-c0a48983-8064-4060-94f4-3e24e5ebb5a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539760379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1539760379
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2965964334
Short name T583
Test name
Test status
Simulation time 14388437 ps
CPU time 0.56 seconds
Started Jul 23 06:05:12 PM PDT 24
Finished Jul 23 06:05:13 PM PDT 24
Peak memory 194464 kb
Host smart-aa0948db-e94d-4f12-8e48-a7ff9d1b0a5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965964334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2965964334
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2909806606
Short name T257
Test name
Test status
Simulation time 31602270 ps
CPU time 0.93 seconds
Started Jul 23 06:05:01 PM PDT 24
Finished Jul 23 06:05:02 PM PDT 24
Peak memory 197048 kb
Host smart-b0d73846-346d-426d-8e56-075de34f8a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909806606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2909806606
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3734615835
Short name T107
Test name
Test status
Simulation time 3045636734 ps
CPU time 27.01 seconds
Started Jul 23 06:04:47 PM PDT 24
Finished Jul 23 06:05:16 PM PDT 24
Peak memory 197960 kb
Host smart-4a008430-bf49-49af-bed7-0cba6fab8ac9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734615835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3734615835
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1033072237
Short name T595
Test name
Test status
Simulation time 36661919 ps
CPU time 0.78 seconds
Started Jul 23 06:04:45 PM PDT 24
Finished Jul 23 06:04:46 PM PDT 24
Peak memory 197160 kb
Host smart-ea0bbc98-c48f-4890-b895-77f912071dc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033072237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1033072237
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.591151133
Short name T151
Test name
Test status
Simulation time 91767628 ps
CPU time 0.96 seconds
Started Jul 23 06:04:50 PM PDT 24
Finished Jul 23 06:04:52 PM PDT 24
Peak memory 197700 kb
Host smart-177bb70a-3671-40ad-ac4b-c74f812c1ce2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591151133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.591151133
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.179017551
Short name T391
Test name
Test status
Simulation time 75600702 ps
CPU time 2.8 seconds
Started Jul 23 06:04:54 PM PDT 24
Finished Jul 23 06:04:58 PM PDT 24
Peak memory 198608 kb
Host smart-dbd457d5-c49d-4ee0-a5ff-caed98fec557
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179017551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.179017551
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.47427113
Short name T518
Test name
Test status
Simulation time 33305686 ps
CPU time 0.95 seconds
Started Jul 23 06:04:57 PM PDT 24
Finished Jul 23 06:04:58 PM PDT 24
Peak memory 194932 kb
Host smart-f7e6d918-07fe-42e2-a299-ced56a398c99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47427113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.47427113
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3668722832
Short name T127
Test name
Test status
Simulation time 181120600 ps
CPU time 0.76 seconds
Started Jul 23 06:05:02 PM PDT 24
Finished Jul 23 06:05:03 PM PDT 24
Peak memory 195960 kb
Host smart-7fdf93bb-a050-4930-89a4-256a8c89b6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668722832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3668722832
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1921368629
Short name T657
Test name
Test status
Simulation time 113189182 ps
CPU time 1.15 seconds
Started Jul 23 06:05:04 PM PDT 24
Finished Jul 23 06:05:07 PM PDT 24
Peak memory 197592 kb
Host smart-add80b04-c093-4844-9d5b-2c21d33eb569
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921368629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1921368629
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.40003608
Short name T360
Test name
Test status
Simulation time 100645424 ps
CPU time 4.38 seconds
Started Jul 23 06:04:48 PM PDT 24
Finished Jul 23 06:04:54 PM PDT 24
Peak memory 198480 kb
Host smart-bafc67fe-b532-4cba-bcac-4e7537aea5bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40003608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand
om_long_reg_writes_reg_reads.40003608
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2091231095
Short name T529
Test name
Test status
Simulation time 142752280 ps
CPU time 1.51 seconds
Started Jul 23 06:04:52 PM PDT 24
Finished Jul 23 06:04:54 PM PDT 24
Peak memory 197404 kb
Host smart-d185beaa-c933-454a-a71d-0732c030d546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091231095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2091231095
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2877968746
Short name T387
Test name
Test status
Simulation time 59570030 ps
CPU time 1.12 seconds
Started Jul 23 06:05:07 PM PDT 24
Finished Jul 23 06:05:09 PM PDT 24
Peak memory 196832 kb
Host smart-6f655f85-1a14-48c6-84b2-cea13f1d44b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877968746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2877968746
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.4201385799
Short name T377
Test name
Test status
Simulation time 14839879323 ps
CPU time 119.69 seconds
Started Jul 23 06:04:53 PM PDT 24
Finished Jul 23 06:06:53 PM PDT 24
Peak memory 198600 kb
Host smart-d600646e-d035-46ec-9845-92434277a517
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201385799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.4201385799
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3665279500
Short name T12
Test name
Test status
Simulation time 38861330876 ps
CPU time 665.37 seconds
Started Jul 23 06:05:06 PM PDT 24
Finished Jul 23 06:16:12 PM PDT 24
Peak memory 198804 kb
Host smart-3e45454a-7826-4c1f-9ff4-c32bd6bfa85e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3665279500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3665279500
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1225645387
Short name T193
Test name
Test status
Simulation time 12059567 ps
CPU time 0.58 seconds
Started Jul 23 06:01:37 PM PDT 24
Finished Jul 23 06:01:38 PM PDT 24
Peak memory 194524 kb
Host smart-9761a86a-5a81-4f78-9153-38a419774d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225645387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1225645387
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3119220622
Short name T537
Test name
Test status
Simulation time 97349826 ps
CPU time 0.72 seconds
Started Jul 23 06:01:41 PM PDT 24
Finished Jul 23 06:01:43 PM PDT 24
Peak memory 196424 kb
Host smart-9a1a095d-a151-4655-8fea-8ae30f99be3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119220622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3119220622
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.4048375021
Short name T617
Test name
Test status
Simulation time 210148813 ps
CPU time 7.39 seconds
Started Jul 23 06:01:39 PM PDT 24
Finished Jul 23 06:01:48 PM PDT 24
Peak memory 197328 kb
Host smart-31a1e5a5-02ee-498c-b943-dd7b9149a4c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048375021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.4048375021
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2532707989
Short name T267
Test name
Test status
Simulation time 139698926 ps
CPU time 0.83 seconds
Started Jul 23 06:01:37 PM PDT 24
Finished Jul 23 06:01:39 PM PDT 24
Peak memory 196484 kb
Host smart-3a629a79-4450-4275-823d-c8e4d6ed21e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532707989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2532707989
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2602482062
Short name T705
Test name
Test status
Simulation time 99768363 ps
CPU time 1.4 seconds
Started Jul 23 06:01:50 PM PDT 24
Finished Jul 23 06:01:52 PM PDT 24
Peak memory 197696 kb
Host smart-972e6913-7200-4c30-8d24-b102bf519dab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602482062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2602482062
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2932526810
Short name T48
Test name
Test status
Simulation time 74204679 ps
CPU time 1.63 seconds
Started Jul 23 06:01:35 PM PDT 24
Finished Jul 23 06:01:38 PM PDT 24
Peak memory 197344 kb
Host smart-e99b98d7-a555-4056-a796-0cfd62bd4ac0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932526810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2932526810
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1931428670
Short name T484
Test name
Test status
Simulation time 56898193 ps
CPU time 1.67 seconds
Started Jul 23 06:01:36 PM PDT 24
Finished Jul 23 06:01:39 PM PDT 24
Peak memory 196724 kb
Host smart-4e8a8401-de38-4208-84e2-84e4129d7c93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931428670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1931428670
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2906313163
Short name T190
Test name
Test status
Simulation time 83327707 ps
CPU time 1.01 seconds
Started Jul 23 06:01:31 PM PDT 24
Finished Jul 23 06:01:33 PM PDT 24
Peak memory 196428 kb
Host smart-582d2ed7-7539-4734-b134-58cec66ea7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906313163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2906313163
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4258618225
Short name T221
Test name
Test status
Simulation time 96625065 ps
CPU time 0.95 seconds
Started Jul 23 06:01:35 PM PDT 24
Finished Jul 23 06:01:37 PM PDT 24
Peak memory 196508 kb
Host smart-4f935fb8-9511-4e1d-9ccd-9c08f0beba29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258618225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4258618225
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.856613825
Short name T1
Test name
Test status
Simulation time 1009982136 ps
CPU time 3.3 seconds
Started Jul 23 06:01:54 PM PDT 24
Finished Jul 23 06:01:58 PM PDT 24
Peak memory 198500 kb
Host smart-52534ed9-fe5c-4435-86ff-071cfcada29e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856613825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.856613825
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2959562179
Short name T312
Test name
Test status
Simulation time 102135937 ps
CPU time 1.39 seconds
Started Jul 23 06:01:30 PM PDT 24
Finished Jul 23 06:01:33 PM PDT 24
Peak memory 198556 kb
Host smart-f1e8bf6a-186f-41e0-a362-eb08c7516a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959562179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2959562179
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.119585124
Short name T659
Test name
Test status
Simulation time 109195868 ps
CPU time 0.94 seconds
Started Jul 23 06:01:39 PM PDT 24
Finished Jul 23 06:01:42 PM PDT 24
Peak memory 197060 kb
Host smart-7f18b3ba-ebda-4719-93cc-049ec6809ae5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119585124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.119585124
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3757311602
Short name T167
Test name
Test status
Simulation time 15198603927 ps
CPU time 48.36 seconds
Started Jul 23 06:01:34 PM PDT 24
Finished Jul 23 06:02:23 PM PDT 24
Peak memory 198620 kb
Host smart-d27d3b4a-3498-4979-b3d3-62c92543dc9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757311602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3757311602
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2645014880
Short name T365
Test name
Test status
Simulation time 12000362 ps
CPU time 0.59 seconds
Started Jul 23 06:01:53 PM PDT 24
Finished Jul 23 06:01:59 PM PDT 24
Peak memory 194436 kb
Host smart-dab6b239-6cbc-490e-bdd4-20d14b6947fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645014880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2645014880
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3720429977
Short name T459
Test name
Test status
Simulation time 29568013 ps
CPU time 0.8 seconds
Started Jul 23 06:01:33 PM PDT 24
Finished Jul 23 06:01:35 PM PDT 24
Peak memory 196404 kb
Host smart-815be8ce-dc77-4a10-96e3-be341feec25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720429977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3720429977
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.1018704815
Short name T410
Test name
Test status
Simulation time 773750510 ps
CPU time 17.79 seconds
Started Jul 23 06:01:42 PM PDT 24
Finished Jul 23 06:02:00 PM PDT 24
Peak memory 198472 kb
Host smart-939a88cb-6b0c-4b26-83ad-b3216f913149
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018704815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.1018704815
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.318039202
Short name T535
Test name
Test status
Simulation time 49061494 ps
CPU time 0.83 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:01:34 PM PDT 24
Peak memory 196356 kb
Host smart-bb7fe5ce-2226-4549-90f0-ca031b0b4913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318039202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.318039202
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2184174742
Short name T161
Test name
Test status
Simulation time 86904955 ps
CPU time 1.16 seconds
Started Jul 23 06:01:33 PM PDT 24
Finished Jul 23 06:01:36 PM PDT 24
Peak memory 196464 kb
Host smart-912fec94-5274-495a-80da-be98c01ca7ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184174742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2184174742
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3830164508
Short name T27
Test name
Test status
Simulation time 409095841 ps
CPU time 1.56 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:01:35 PM PDT 24
Peak memory 198644 kb
Host smart-4d4b0574-0369-4028-9261-741210803511
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830164508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3830164508
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1118376152
Short name T461
Test name
Test status
Simulation time 225576283 ps
CPU time 1.43 seconds
Started Jul 23 06:01:37 PM PDT 24
Finished Jul 23 06:01:40 PM PDT 24
Peak memory 196636 kb
Host smart-ce0205ab-b752-4b8c-9f59-3ee7e398a14e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118376152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1118376152
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2906643976
Short name T229
Test name
Test status
Simulation time 45968139 ps
CPU time 0.9 seconds
Started Jul 23 06:01:54 PM PDT 24
Finished Jul 23 06:01:55 PM PDT 24
Peak memory 196576 kb
Host smart-0ab52a3d-f36c-4fb1-9c5c-6e58d9ed51a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906643976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2906643976
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1707439153
Short name T412
Test name
Test status
Simulation time 92518168 ps
CPU time 0.71 seconds
Started Jul 23 06:01:41 PM PDT 24
Finished Jul 23 06:01:43 PM PDT 24
Peak memory 195836 kb
Host smart-710afcd7-40be-4e78-9cdc-7f0fcf2b67a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707439153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1707439153
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_smoke.1902268398
Short name T683
Test name
Test status
Simulation time 36279733 ps
CPU time 1.08 seconds
Started Jul 23 06:01:36 PM PDT 24
Finished Jul 23 06:01:43 PM PDT 24
Peak memory 197000 kb
Host smart-05ce099b-b724-45ad-a8d0-61d4b40fb140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902268398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1902268398
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3054733652
Short name T99
Test name
Test status
Simulation time 260832859 ps
CPU time 1.31 seconds
Started Jul 23 06:01:50 PM PDT 24
Finished Jul 23 06:01:52 PM PDT 24
Peak memory 196032 kb
Host smart-e85fde54-abe6-4ac9-8a71-d271c9978c76
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054733652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3054733652
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2115543598
Short name T404
Test name
Test status
Simulation time 7207460985 ps
CPU time 181.96 seconds
Started Jul 23 06:01:32 PM PDT 24
Finished Jul 23 06:04:35 PM PDT 24
Peak memory 198640 kb
Host smart-0f22c953-3828-47f7-acf9-30c9b028ac6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115543598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2115543598
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3406100047
Short name T521
Test name
Test status
Simulation time 20386209 ps
CPU time 0.58 seconds
Started Jul 23 06:01:40 PM PDT 24
Finished Jul 23 06:01:42 PM PDT 24
Peak memory 194456 kb
Host smart-7adeef58-cda5-4eb8-a4ad-91175b8263b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406100047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3406100047
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4112043310
Short name T234
Test name
Test status
Simulation time 47322290 ps
CPU time 0.85 seconds
Started Jul 23 06:01:56 PM PDT 24
Finished Jul 23 06:01:57 PM PDT 24
Peak memory 196720 kb
Host smart-366e71c8-d822-4343-b169-78d6564906ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112043310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4112043310
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.4012361045
Short name T248
Test name
Test status
Simulation time 491283529 ps
CPU time 9.27 seconds
Started Jul 23 06:01:50 PM PDT 24
Finished Jul 23 06:02:00 PM PDT 24
Peak memory 197456 kb
Host smart-c13aee86-1f7d-4c4e-a0aa-9f909baa73b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012361045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.4012361045
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1580379926
Short name T593
Test name
Test status
Simulation time 74856914 ps
CPU time 0.73 seconds
Started Jul 23 06:01:36 PM PDT 24
Finished Jul 23 06:01:38 PM PDT 24
Peak memory 196264 kb
Host smart-d9ad8c66-8424-4c25-8a63-f5a350c9ee0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580379926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1580379926
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1673468166
Short name T414
Test name
Test status
Simulation time 70463760 ps
CPU time 1.12 seconds
Started Jul 23 06:02:03 PM PDT 24
Finished Jul 23 06:02:06 PM PDT 24
Peak memory 197092 kb
Host smart-88542914-151b-4a0d-8a91-cbb5087f095d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673468166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1673468166
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.4194753565
Short name T706
Test name
Test status
Simulation time 239864558 ps
CPU time 2.43 seconds
Started Jul 23 06:01:51 PM PDT 24
Finished Jul 23 06:01:54 PM PDT 24
Peak memory 198664 kb
Host smart-dd4c3515-f92a-4b0e-8166-22e56d605832
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194753565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.4194753565
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1575021651
Short name T222
Test name
Test status
Simulation time 539864522 ps
CPU time 2.87 seconds
Started Jul 23 06:01:57 PM PDT 24
Finished Jul 23 06:02:01 PM PDT 24
Peak memory 197692 kb
Host smart-87618578-c13a-4d7e-837b-6bff9835dcd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575021651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1575021651
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2331769841
Short name T281
Test name
Test status
Simulation time 48755084 ps
CPU time 1.14 seconds
Started Jul 23 06:01:37 PM PDT 24
Finished Jul 23 06:01:40 PM PDT 24
Peak memory 196492 kb
Host smart-fba2865b-f941-428e-ac17-4e64f4b88a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331769841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2331769841
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4158027849
Short name T692
Test name
Test status
Simulation time 97949833 ps
CPU time 1.15 seconds
Started Jul 23 06:01:40 PM PDT 24
Finished Jul 23 06:01:43 PM PDT 24
Peak memory 196600 kb
Host smart-58aee6e7-6a21-4393-9cdf-46758efb5fd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158027849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4158027849
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.768589889
Short name T369
Test name
Test status
Simulation time 127620649 ps
CPU time 2.19 seconds
Started Jul 23 06:01:40 PM PDT 24
Finished Jul 23 06:01:43 PM PDT 24
Peak memory 198256 kb
Host smart-bac3645a-c961-43c9-bac3-c56e08e29d89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768589889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand
om_long_reg_writes_reg_reads.768589889
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1490686253
Short name T523
Test name
Test status
Simulation time 38613632 ps
CPU time 0.98 seconds
Started Jul 23 06:01:57 PM PDT 24
Finished Jul 23 06:01:59 PM PDT 24
Peak memory 196696 kb
Host smart-46e121d7-37a9-48ae-b9ee-1add6960dd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490686253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1490686253
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1445118476
Short name T709
Test name
Test status
Simulation time 76468855 ps
CPU time 1.35 seconds
Started Jul 23 06:01:38 PM PDT 24
Finished Jul 23 06:01:41 PM PDT 24
Peak memory 198464 kb
Host smart-018868a3-2e2d-4615-9342-443ef0024c58
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445118476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1445118476
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.4129142230
Short name T270
Test name
Test status
Simulation time 4369916304 ps
CPU time 32.41 seconds
Started Jul 23 06:01:47 PM PDT 24
Finished Jul 23 06:02:20 PM PDT 24
Peak memory 198644 kb
Host smart-8b0a4aa5-6a06-484f-9dbe-ec1bdec88d5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129142230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.4129142230
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1219745113
Short name T287
Test name
Test status
Simulation time 14412103 ps
CPU time 0.57 seconds
Started Jul 23 06:01:53 PM PDT 24
Finished Jul 23 06:01:54 PM PDT 24
Peak memory 195124 kb
Host smart-74f62980-53a6-4566-8a77-f16f9c6c68f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219745113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1219745113
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1133594891
Short name T111
Test name
Test status
Simulation time 49045864 ps
CPU time 0.71 seconds
Started Jul 23 06:01:50 PM PDT 24
Finished Jul 23 06:01:51 PM PDT 24
Peak memory 194840 kb
Host smart-f596aa0d-a840-4ad7-9243-0f28646451af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133594891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1133594891
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.737305376
Short name T616
Test name
Test status
Simulation time 800817299 ps
CPU time 27.48 seconds
Started Jul 23 06:01:50 PM PDT 24
Finished Jul 23 06:02:18 PM PDT 24
Peak memory 196036 kb
Host smart-3cfd3c08-9544-4cd6-96af-e76b85459787
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737305376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.737305376
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.969554450
Short name T485
Test name
Test status
Simulation time 215817607 ps
CPU time 0.97 seconds
Started Jul 23 06:01:49 PM PDT 24
Finished Jul 23 06:01:51 PM PDT 24
Peak memory 198204 kb
Host smart-27991156-bd98-484d-a55b-c3acb7c4fc67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969554450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.969554450
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1645347288
Short name T597
Test name
Test status
Simulation time 264365495 ps
CPU time 1.03 seconds
Started Jul 23 06:01:47 PM PDT 24
Finished Jul 23 06:01:48 PM PDT 24
Peak memory 196604 kb
Host smart-d039b18b-ff8a-4098-bba6-0795c39121c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645347288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1645347288
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3392987168
Short name T510
Test name
Test status
Simulation time 24785084 ps
CPU time 1.11 seconds
Started Jul 23 06:01:42 PM PDT 24
Finished Jul 23 06:01:44 PM PDT 24
Peak memory 197664 kb
Host smart-d98385e2-9aed-4603-97d9-1213c6ed91d4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392987168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3392987168
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2387256301
Short name T394
Test name
Test status
Simulation time 51546302 ps
CPU time 1.56 seconds
Started Jul 23 06:01:43 PM PDT 24
Finished Jul 23 06:01:45 PM PDT 24
Peak memory 196524 kb
Host smart-408de9d7-88cb-4f9a-8660-80e22e279b5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387256301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2387256301
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2092889981
Short name T91
Test name
Test status
Simulation time 90178910 ps
CPU time 0.76 seconds
Started Jul 23 06:01:49 PM PDT 24
Finished Jul 23 06:01:51 PM PDT 24
Peak memory 195832 kb
Host smart-421e9118-75ee-4cb9-9294-6f51beb4ef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092889981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2092889981
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.802044557
Short name T344
Test name
Test status
Simulation time 59357197 ps
CPU time 1.04 seconds
Started Jul 23 06:01:59 PM PDT 24
Finished Jul 23 06:02:00 PM PDT 24
Peak memory 196340 kb
Host smart-1c70a8eb-5daf-4ad8-8cd7-0d40314ef822
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802044557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.802044557
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2108954227
Short name T87
Test name
Test status
Simulation time 707878893 ps
CPU time 3.11 seconds
Started Jul 23 06:01:48 PM PDT 24
Finished Jul 23 06:01:52 PM PDT 24
Peak memory 198736 kb
Host smart-efc081cf-d466-4711-b0cc-4fff644c2880
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108954227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2108954227
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.839037277
Short name T442
Test name
Test status
Simulation time 40366486 ps
CPU time 0.95 seconds
Started Jul 23 06:01:49 PM PDT 24
Finished Jul 23 06:01:51 PM PDT 24
Peak memory 196952 kb
Host smart-c3d53032-9bf5-4dfa-9c57-a1b127b037bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839037277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.839037277
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2099821444
Short name T667
Test name
Test status
Simulation time 90453392 ps
CPU time 0.84 seconds
Started Jul 23 06:02:00 PM PDT 24
Finished Jul 23 06:02:02 PM PDT 24
Peak memory 195872 kb
Host smart-91fde719-8f26-44ab-8e9d-7b9912e15629
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099821444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2099821444
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.757250362
Short name T317
Test name
Test status
Simulation time 54798503387 ps
CPU time 118.81 seconds
Started Jul 23 06:01:57 PM PDT 24
Finished Jul 23 06:03:57 PM PDT 24
Peak memory 198644 kb
Host smart-15585a27-52f7-46c8-9472-f403eecc49b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757250362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.757250362
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.405052511
Short name T398
Test name
Test status
Simulation time 14764714 ps
CPU time 0.58 seconds
Started Jul 23 06:01:58 PM PDT 24
Finished Jul 23 06:02:00 PM PDT 24
Peak memory 194468 kb
Host smart-5eb04808-29ad-4797-aa1e-eb3adb828d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405052511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.405052511
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2159068533
Short name T173
Test name
Test status
Simulation time 23563799 ps
CPU time 0.7 seconds
Started Jul 23 06:02:00 PM PDT 24
Finished Jul 23 06:02:02 PM PDT 24
Peak memory 194604 kb
Host smart-36c2a19b-2463-4cb0-8668-aa0cd9ee3929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159068533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2159068533
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3685540780
Short name T289
Test name
Test status
Simulation time 7137427874 ps
CPU time 24.7 seconds
Started Jul 23 06:01:38 PM PDT 24
Finished Jul 23 06:02:03 PM PDT 24
Peak memory 197220 kb
Host smart-425f7f8a-9cc3-454a-ba26-59b80a19aab5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685540780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3685540780
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.4259232989
Short name T632
Test name
Test status
Simulation time 147502575 ps
CPU time 1 seconds
Started Jul 23 06:01:38 PM PDT 24
Finished Jul 23 06:01:40 PM PDT 24
Peak memory 198272 kb
Host smart-ca4f6d6e-3d2e-4eda-a441-053abbc8a718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259232989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4259232989
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.938364036
Short name T152
Test name
Test status
Simulation time 259270528 ps
CPU time 0.95 seconds
Started Jul 23 06:01:36 PM PDT 24
Finished Jul 23 06:01:38 PM PDT 24
Peak memory 197308 kb
Host smart-0653f62e-9492-4f7e-9a22-a0fe5dd3c544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938364036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.938364036
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2645104644
Short name T517
Test name
Test status
Simulation time 397773964 ps
CPU time 2.35 seconds
Started Jul 23 06:01:39 PM PDT 24
Finished Jul 23 06:01:43 PM PDT 24
Peak memory 198576 kb
Host smart-a3040a6e-0287-41c7-9219-fb7e87b7e68f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645104644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2645104644
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2684580814
Short name T254
Test name
Test status
Simulation time 542423464 ps
CPU time 2.47 seconds
Started Jul 23 06:01:39 PM PDT 24
Finished Jul 23 06:01:43 PM PDT 24
Peak memory 198488 kb
Host smart-e191e782-4589-4adb-918e-2d13e07f9d9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684580814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2684580814
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1035852722
Short name T671
Test name
Test status
Simulation time 141611758 ps
CPU time 0.99 seconds
Started Jul 23 06:01:43 PM PDT 24
Finished Jul 23 06:01:45 PM PDT 24
Peak memory 197044 kb
Host smart-d65bca50-f23d-4e6a-9714-dab2d6c7b9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035852722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1035852722
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2554333198
Short name T693
Test name
Test status
Simulation time 40514010 ps
CPU time 0.93 seconds
Started Jul 23 06:01:52 PM PDT 24
Finished Jul 23 06:01:53 PM PDT 24
Peak memory 197276 kb
Host smart-9acb281c-f406-4da5-8eb0-d39aae61927e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554333198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2554333198
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2006761065
Short name T660
Test name
Test status
Simulation time 515797118 ps
CPU time 5.9 seconds
Started Jul 23 06:01:47 PM PDT 24
Finished Jul 23 06:01:53 PM PDT 24
Peak memory 198480 kb
Host smart-bcc11894-ba3d-4d35-b88a-ef981656c074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006761065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2006761065
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2066206170
Short name T276
Test name
Test status
Simulation time 159636150 ps
CPU time 1.29 seconds
Started Jul 23 06:01:44 PM PDT 24
Finished Jul 23 06:01:46 PM PDT 24
Peak memory 197380 kb
Host smart-1b358a58-f4a3-4203-9960-12a3f0095f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066206170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2066206170
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3321757530
Short name T500
Test name
Test status
Simulation time 96248656 ps
CPU time 1.14 seconds
Started Jul 23 06:01:44 PM PDT 24
Finished Jul 23 06:01:46 PM PDT 24
Peak memory 196336 kb
Host smart-9d8541b7-4196-4443-9056-20defb340989
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321757530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3321757530
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2810735801
Short name T303
Test name
Test status
Simulation time 4173796224 ps
CPU time 103.36 seconds
Started Jul 23 06:02:02 PM PDT 24
Finished Jul 23 06:03:47 PM PDT 24
Peak memory 198652 kb
Host smart-d6bd7227-1385-4938-8e38-8855d5f74d2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810735801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2810735801
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2879581590
Short name T492
Test name
Test status
Simulation time 243586075455 ps
CPU time 970.26 seconds
Started Jul 23 06:01:55 PM PDT 24
Finished Jul 23 06:18:06 PM PDT 24
Peak memory 198752 kb
Host smart-906eee6a-a99f-46f4-a376-3f5e35b59a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2879581590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2879581590
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3415940759
Short name T933
Test name
Test status
Simulation time 120198394 ps
CPU time 1.12 seconds
Started Jul 23 06:49:35 PM PDT 24
Finished Jul 23 06:49:37 PM PDT 24
Peak memory 191760 kb
Host smart-673e774e-21e1-449d-a524-8856488ecfc6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3415940759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3415940759
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.796009444
Short name T924
Test name
Test status
Simulation time 108525645 ps
CPU time 1.02 seconds
Started Jul 23 06:49:43 PM PDT 24
Finished Jul 23 06:49:46 PM PDT 24
Peak memory 191772 kb
Host smart-fe998cea-33a0-4955-8ed2-43ac5ff811db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796009444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.796009444
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.3716896824
Short name T846
Test name
Test status
Simulation time 1106268243 ps
CPU time 1.33 seconds
Started Jul 23 06:49:39 PM PDT 24
Finished Jul 23 06:49:40 PM PDT 24
Peak memory 191700 kb
Host smart-e0761b97-8cf1-44a9-978f-45f56f3be891
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3716896824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.3716896824
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1872357997
Short name T872
Test name
Test status
Simulation time 121156857 ps
CPU time 1.19 seconds
Started Jul 23 06:49:40 PM PDT 24
Finished Jul 23 06:49:42 PM PDT 24
Peak memory 198076 kb
Host smart-f3831d37-d635-46b2-8e33-78bfc7d8b701
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872357997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1872357997
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1290085685
Short name T874
Test name
Test status
Simulation time 230350757 ps
CPU time 1.5 seconds
Started Jul 23 06:49:48 PM PDT 24
Finished Jul 23 06:49:51 PM PDT 24
Peak memory 191792 kb
Host smart-47d29844-4b1d-4307-b24f-1426a4853701
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1290085685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1290085685
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4026406658
Short name T909
Test name
Test status
Simulation time 67323960 ps
CPU time 1.29 seconds
Started Jul 23 06:49:40 PM PDT 24
Finished Jul 23 06:49:43 PM PDT 24
Peak memory 198076 kb
Host smart-ab9eced6-aade-4936-bf2d-8004479d5683
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026406658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4026406658
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.499741149
Short name T927
Test name
Test status
Simulation time 241554117 ps
CPU time 0.97 seconds
Started Jul 23 06:49:44 PM PDT 24
Finished Jul 23 06:49:47 PM PDT 24
Peak memory 191768 kb
Host smart-442f2305-09c2-4565-b0ac-33fd14692332
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=499741149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.499741149
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3132414330
Short name T895
Test name
Test status
Simulation time 167336327 ps
CPU time 0.94 seconds
Started Jul 23 06:49:45 PM PDT 24
Finished Jul 23 06:49:48 PM PDT 24
Peak memory 196264 kb
Host smart-fadef90f-307e-4f0f-bb48-97c16a258617
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132414330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3132414330
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4069533324
Short name T907
Test name
Test status
Simulation time 308816304 ps
CPU time 1.28 seconds
Started Jul 23 06:49:37 PM PDT 24
Finished Jul 23 06:49:39 PM PDT 24
Peak memory 196648 kb
Host smart-60e8d546-ab7e-4e1f-b8cb-61d8405699bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4069533324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4069533324
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.830575927
Short name T870
Test name
Test status
Simulation time 43388318 ps
CPU time 0.91 seconds
Started Jul 23 06:49:42 PM PDT 24
Finished Jul 23 06:49:44 PM PDT 24
Peak memory 191528 kb
Host smart-3f3accd2-e0ff-4bc8-bb08-673c57b757cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830575927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.830575927
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.3322989994
Short name T912
Test name
Test status
Simulation time 81976525 ps
CPU time 1.13 seconds
Started Jul 23 06:49:44 PM PDT 24
Finished Jul 23 06:49:46 PM PDT 24
Peak memory 197624 kb
Host smart-e55ca9ea-b520-4cbe-81e2-50abae6d436b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3322989994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.3322989994
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3824516212
Short name T852
Test name
Test status
Simulation time 368667473 ps
CPU time 1.46 seconds
Started Jul 23 06:49:48 PM PDT 24
Finished Jul 23 06:49:51 PM PDT 24
Peak memory 191796 kb
Host smart-cadc2af2-f712-4335-b6e4-fba56257e53e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824516212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3824516212
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.4094824988
Short name T910
Test name
Test status
Simulation time 1148351364 ps
CPU time 1.38 seconds
Started Jul 23 06:49:49 PM PDT 24
Finished Jul 23 06:49:51 PM PDT 24
Peak memory 198100 kb
Host smart-e11bc90c-cbbe-4a72-8976-3e52552e8fcf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4094824988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.4094824988
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1645556280
Short name T883
Test name
Test status
Simulation time 119581201 ps
CPU time 1.02 seconds
Started Jul 23 06:49:48 PM PDT 24
Finished Jul 23 06:49:50 PM PDT 24
Peak memory 191836 kb
Host smart-30ce8b4c-b462-43e0-8715-e2687f0f9084
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645556280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1645556280
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2984920539
Short name T936
Test name
Test status
Simulation time 48956994 ps
CPU time 1.06 seconds
Started Jul 23 06:49:43 PM PDT 24
Finished Jul 23 06:49:46 PM PDT 24
Peak memory 191864 kb
Host smart-8d853690-013b-44c1-9193-b4f10eb47bf8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2984920539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2984920539
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4052053246
Short name T847
Test name
Test status
Simulation time 36003307 ps
CPU time 1.08 seconds
Started Jul 23 06:49:39 PM PDT 24
Finished Jul 23 06:49:41 PM PDT 24
Peak memory 197540 kb
Host smart-d8c17914-9e73-400c-97a5-28564f924812
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052053246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4052053246
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.904113791
Short name T855
Test name
Test status
Simulation time 131301189 ps
CPU time 0.96 seconds
Started Jul 23 06:49:48 PM PDT 24
Finished Jul 23 06:49:49 PM PDT 24
Peak memory 191792 kb
Host smart-3deff7f7-a95a-4570-ae8b-9dd00582562a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=904113791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.904113791
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2049871809
Short name T903
Test name
Test status
Simulation time 122749238 ps
CPU time 1.4 seconds
Started Jul 23 06:49:54 PM PDT 24
Finished Jul 23 06:49:56 PM PDT 24
Peak memory 191796 kb
Host smart-b29106d7-712f-40fc-9afe-aefd757bd90d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049871809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2049871809
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1165604428
Short name T904
Test name
Test status
Simulation time 82386180 ps
CPU time 0.89 seconds
Started Jul 23 06:49:50 PM PDT 24
Finished Jul 23 06:49:52 PM PDT 24
Peak memory 197244 kb
Host smart-6ac95e85-a3a8-4c6e-95a0-0988e38f0916
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1165604428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1165604428
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.29796407
Short name T885
Test name
Test status
Simulation time 67702336 ps
CPU time 1.14 seconds
Started Jul 23 06:49:51 PM PDT 24
Finished Jul 23 06:49:53 PM PDT 24
Peak memory 191756 kb
Host smart-3838c5c3-fe14-4a68-be91-2ee06ad93495
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.29796407
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2246065003
Short name T938
Test name
Test status
Simulation time 64821665 ps
CPU time 1.1 seconds
Started Jul 23 06:49:50 PM PDT 24
Finished Jul 23 06:49:52 PM PDT 24
Peak memory 191860 kb
Host smart-b2893e1c-8249-4ca3-a636-86200cf0b030
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2246065003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2246065003
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.525346498
Short name T921
Test name
Test status
Simulation time 115545940 ps
CPU time 0.99 seconds
Started Jul 23 06:49:49 PM PDT 24
Finished Jul 23 06:49:52 PM PDT 24
Peak memory 197640 kb
Host smart-f9ce968d-4632-4121-a943-8c4a39536115
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525346498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.525346498
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3685575849
Short name T861
Test name
Test status
Simulation time 203416725 ps
CPU time 0.98 seconds
Started Jul 23 06:49:48 PM PDT 24
Finished Jul 23 06:49:50 PM PDT 24
Peak memory 191772 kb
Host smart-3d48d801-413d-4613-8b6a-94a15d2411e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3685575849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3685575849
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2194770865
Short name T917
Test name
Test status
Simulation time 173252924 ps
CPU time 1.3 seconds
Started Jul 23 06:49:48 PM PDT 24
Finished Jul 23 06:49:50 PM PDT 24
Peak memory 191816 kb
Host smart-8f14bcad-fa08-48f4-9864-aca617d76dd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194770865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2194770865
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2100180044
Short name T859
Test name
Test status
Simulation time 72275403 ps
CPU time 1.14 seconds
Started Jul 23 06:49:39 PM PDT 24
Finished Jul 23 06:49:41 PM PDT 24
Peak memory 198180 kb
Host smart-9cf5b03f-9844-4804-a052-02623d477f24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2100180044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2100180044
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3148882773
Short name T889
Test name
Test status
Simulation time 38030983 ps
CPU time 0.83 seconds
Started Jul 23 06:49:34 PM PDT 24
Finished Jul 23 06:49:35 PM PDT 24
Peak memory 196260 kb
Host smart-4e8f2af5-923d-4263-aa07-e1e5b02c02ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148882773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3148882773
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.439933397
Short name T865
Test name
Test status
Simulation time 289175903 ps
CPU time 1.23 seconds
Started Jul 23 06:49:48 PM PDT 24
Finished Jul 23 06:49:51 PM PDT 24
Peak memory 191828 kb
Host smart-47de61f3-358a-4501-ae0b-feaf582d23dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=439933397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.439933397
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3069613518
Short name T929
Test name
Test status
Simulation time 35669357 ps
CPU time 1.07 seconds
Started Jul 23 06:49:49 PM PDT 24
Finished Jul 23 06:49:51 PM PDT 24
Peak memory 191784 kb
Host smart-ab142174-eb02-451a-84b2-471d3f2891d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069613518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3069613518
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3000147565
Short name T935
Test name
Test status
Simulation time 42284119 ps
CPU time 0.89 seconds
Started Jul 23 06:49:50 PM PDT 24
Finished Jul 23 06:49:52 PM PDT 24
Peak memory 191592 kb
Host smart-e1092576-d61d-4449-b10e-b70b7ec618db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3000147565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3000147565
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3837673154
Short name T937
Test name
Test status
Simulation time 129317770 ps
CPU time 0.72 seconds
Started Jul 23 06:49:50 PM PDT 24
Finished Jul 23 06:49:52 PM PDT 24
Peak memory 195320 kb
Host smart-aeadca4c-bed3-4bfe-b7fa-273b53a69b66
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837673154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3837673154
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1878373706
Short name T934
Test name
Test status
Simulation time 63113129 ps
CPU time 1.27 seconds
Started Jul 23 06:49:52 PM PDT 24
Finished Jul 23 06:49:54 PM PDT 24
Peak memory 191776 kb
Host smart-c4f1edf7-0ed5-46e7-949f-105fbd09fbc7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1878373706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1878373706
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1785246334
Short name T864
Test name
Test status
Simulation time 43894168 ps
CPU time 1.15 seconds
Started Jul 23 06:49:46 PM PDT 24
Finished Jul 23 06:49:49 PM PDT 24
Peak memory 198132 kb
Host smart-a4ebe09b-7384-4b99-a8e8-f65b1de08556
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785246334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1785246334
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3147804193
Short name T866
Test name
Test status
Simulation time 270160859 ps
CPU time 0.87 seconds
Started Jul 23 06:49:58 PM PDT 24
Finished Jul 23 06:50:00 PM PDT 24
Peak memory 191572 kb
Host smart-3c8d04dd-e37a-4a7f-8d7c-c8a948a5d214
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3147804193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3147804193
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.194908930
Short name T942
Test name
Test status
Simulation time 265656116 ps
CPU time 1.1 seconds
Started Jul 23 06:49:50 PM PDT 24
Finished Jul 23 06:49:52 PM PDT 24
Peak memory 191792 kb
Host smart-2471e06e-38ec-45f0-93f0-699cda37eefb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194908930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.194908930
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.504881376
Short name T915
Test name
Test status
Simulation time 36449020 ps
CPU time 0.76 seconds
Started Jul 23 06:50:02 PM PDT 24
Finished Jul 23 06:50:03 PM PDT 24
Peak memory 196136 kb
Host smart-e35b9b09-0ac8-4c5e-9ea5-47e0d495c780
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=504881376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.504881376
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4232823865
Short name T857
Test name
Test status
Simulation time 47578624 ps
CPU time 1.15 seconds
Started Jul 23 06:49:46 PM PDT 24
Finished Jul 23 06:49:49 PM PDT 24
Peak memory 191780 kb
Host smart-13a60ac4-46e6-4e82-bb16-4c57532e55c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232823865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4232823865
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1684461341
Short name T943
Test name
Test status
Simulation time 226898425 ps
CPU time 1.19 seconds
Started Jul 23 06:49:58 PM PDT 24
Finished Jul 23 06:50:00 PM PDT 24
Peak memory 191840 kb
Host smart-d03f52ff-c22b-443e-b7fc-d292bed98b2d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1684461341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1684461341
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.835053535
Short name T871
Test name
Test status
Simulation time 152561430 ps
CPU time 0.97 seconds
Started Jul 23 06:49:53 PM PDT 24
Finished Jul 23 06:49:55 PM PDT 24
Peak memory 191536 kb
Host smart-21a08c8a-2e68-4acd-8f2f-cc976cf3f68d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835053535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.835053535
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.4189757246
Short name T939
Test name
Test status
Simulation time 30907786 ps
CPU time 0.96 seconds
Started Jul 23 06:49:54 PM PDT 24
Finished Jul 23 06:49:55 PM PDT 24
Peak memory 191776 kb
Host smart-bffb51ac-71be-48ef-b524-ab1b865cabd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4189757246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.4189757246
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2831600466
Short name T930
Test name
Test status
Simulation time 83643790 ps
CPU time 1.28 seconds
Started Jul 23 06:49:58 PM PDT 24
Finished Jul 23 06:50:00 PM PDT 24
Peak memory 191720 kb
Host smart-88a1258e-39df-4283-9e90-b47c819216c2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831600466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2831600466
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3759073924
Short name T928
Test name
Test status
Simulation time 36586895 ps
CPU time 1.17 seconds
Started Jul 23 06:50:00 PM PDT 24
Finished Jul 23 06:50:02 PM PDT 24
Peak memory 197736 kb
Host smart-28589c5b-2532-4fca-a5dc-3c052fc9b6fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3759073924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3759073924
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1603789394
Short name T884
Test name
Test status
Simulation time 228372296 ps
CPU time 1.31 seconds
Started Jul 23 06:49:58 PM PDT 24
Finished Jul 23 06:50:00 PM PDT 24
Peak memory 198220 kb
Host smart-43da135e-a1a5-46f4-a909-2a8f3784a510
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603789394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1603789394
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1786969005
Short name T877
Test name
Test status
Simulation time 141450712 ps
CPU time 1.29 seconds
Started Jul 23 06:50:05 PM PDT 24
Finished Jul 23 06:50:07 PM PDT 24
Peak memory 191992 kb
Host smart-80e3fbf7-4450-452b-a987-82c639645ba4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1786969005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1786969005
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3136039479
Short name T858
Test name
Test status
Simulation time 59111820 ps
CPU time 1.02 seconds
Started Jul 23 06:49:59 PM PDT 24
Finished Jul 23 06:50:01 PM PDT 24
Peak memory 197400 kb
Host smart-754dfabe-0a1a-4a40-8a00-c6c233452a74
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136039479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3136039479
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.672225048
Short name T886
Test name
Test status
Simulation time 295007909 ps
CPU time 1.34 seconds
Started Jul 23 06:49:58 PM PDT 24
Finished Jul 23 06:50:00 PM PDT 24
Peak memory 198156 kb
Host smart-b08bb027-330f-4116-93cd-d9e7dccfd1b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=672225048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.672225048
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1517491958
Short name T892
Test name
Test status
Simulation time 54148128 ps
CPU time 1.39 seconds
Started Jul 23 06:49:58 PM PDT 24
Finished Jul 23 06:50:00 PM PDT 24
Peak memory 198204 kb
Host smart-a420758a-28be-46ea-911a-b64f4b76ade0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517491958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1517491958
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.538583943
Short name T863
Test name
Test status
Simulation time 57246707 ps
CPU time 1.06 seconds
Started Jul 23 06:49:41 PM PDT 24
Finished Jul 23 06:49:43 PM PDT 24
Peak memory 191776 kb
Host smart-8904ba8b-d288-4abd-8b50-57b14c191d4d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=538583943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.538583943
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1089904756
Short name T890
Test name
Test status
Simulation time 46633835 ps
CPU time 1.06 seconds
Started Jul 23 06:49:33 PM PDT 24
Finished Jul 23 06:49:35 PM PDT 24
Peak memory 191780 kb
Host smart-39803de8-1797-4849-925f-d0b1cee0fa7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089904756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1089904756
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3313429546
Short name T875
Test name
Test status
Simulation time 198998456 ps
CPU time 1.23 seconds
Started Jul 23 06:49:59 PM PDT 24
Finished Jul 23 06:50:01 PM PDT 24
Peak memory 191836 kb
Host smart-2028bbe1-c386-4f2c-aced-bf1a8f0417be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3313429546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3313429546
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.118205759
Short name T925
Test name
Test status
Simulation time 796411119 ps
CPU time 0.98 seconds
Started Jul 23 06:49:58 PM PDT 24
Finished Jul 23 06:50:00 PM PDT 24
Peak memory 191792 kb
Host smart-b6b43713-8970-4e16-b94e-1d6e6e6bf559
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118205759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.118205759
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.990645995
Short name T891
Test name
Test status
Simulation time 117190232 ps
CPU time 1.04 seconds
Started Jul 23 06:50:00 PM PDT 24
Finished Jul 23 06:50:02 PM PDT 24
Peak memory 198196 kb
Host smart-1988c3a1-9f18-49a3-9057-f1f5eace2422
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=990645995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.990645995
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1628288708
Short name T896
Test name
Test status
Simulation time 154771677 ps
CPU time 1.11 seconds
Started Jul 23 06:50:05 PM PDT 24
Finished Jul 23 06:50:07 PM PDT 24
Peak memory 191780 kb
Host smart-a2173c6e-e275-4feb-824c-b116d22087c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628288708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1628288708
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2934800973
Short name T893
Test name
Test status
Simulation time 41281829 ps
CPU time 1.25 seconds
Started Jul 23 06:50:05 PM PDT 24
Finished Jul 23 06:50:07 PM PDT 24
Peak memory 198192 kb
Host smart-6721d3b6-0989-48fc-82e1-fb7b5a1580d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2934800973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2934800973
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2901993243
Short name T854
Test name
Test status
Simulation time 44243104 ps
CPU time 1.27 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:15 PM PDT 24
Peak memory 191764 kb
Host smart-ea31997e-92ca-4179-b3ef-75549ebeb258
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901993243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2901993243
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.913355223
Short name T919
Test name
Test status
Simulation time 330326125 ps
CPU time 1.33 seconds
Started Jul 23 06:50:08 PM PDT 24
Finished Jul 23 06:50:10 PM PDT 24
Peak memory 191796 kb
Host smart-50593421-2d6e-47ec-9ae6-f97bac8fbf1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=913355223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.913355223
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1163165075
Short name T869
Test name
Test status
Simulation time 232990673 ps
CPU time 1.47 seconds
Started Jul 23 06:50:09 PM PDT 24
Finished Jul 23 06:50:12 PM PDT 24
Peak memory 191660 kb
Host smart-9105c9eb-b064-4e11-b057-2d774ee47864
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163165075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1163165075
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2573257045
Short name T900
Test name
Test status
Simulation time 85498642 ps
CPU time 1.51 seconds
Started Jul 23 06:50:08 PM PDT 24
Finished Jul 23 06:50:10 PM PDT 24
Peak memory 191800 kb
Host smart-8cc97937-7607-4dd6-83e5-267fd4c81703
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2573257045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2573257045
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.446437043
Short name T913
Test name
Test status
Simulation time 119286233 ps
CPU time 1.1 seconds
Started Jul 23 06:50:09 PM PDT 24
Finished Jul 23 06:50:11 PM PDT 24
Peak memory 197352 kb
Host smart-08a10f80-4277-4afa-920f-a51653ef3ed9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446437043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.446437043
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2217534045
Short name T906
Test name
Test status
Simulation time 58352259 ps
CPU time 1.23 seconds
Started Jul 23 06:50:08 PM PDT 24
Finished Jul 23 06:50:10 PM PDT 24
Peak memory 191796 kb
Host smart-6adadd9d-08bb-46ac-870b-39f75b31ab4f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2217534045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2217534045
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.110436426
Short name T941
Test name
Test status
Simulation time 95458429 ps
CPU time 0.75 seconds
Started Jul 23 06:50:05 PM PDT 24
Finished Jul 23 06:50:07 PM PDT 24
Peak memory 191584 kb
Host smart-cd8aeed1-043b-4a64-958a-49da972a99c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110436426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.110436426
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2285089836
Short name T897
Test name
Test status
Simulation time 64913953 ps
CPU time 1.2 seconds
Started Jul 23 06:50:04 PM PDT 24
Finished Jul 23 06:50:05 PM PDT 24
Peak memory 191812 kb
Host smart-3c9d8775-c22b-47db-a037-aa50b3c03987
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2285089836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2285089836
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1098519807
Short name T932
Test name
Test status
Simulation time 425521725 ps
CPU time 1.65 seconds
Started Jul 23 06:50:09 PM PDT 24
Finished Jul 23 06:50:11 PM PDT 24
Peak memory 191624 kb
Host smart-bdc03e2c-2b17-4dc9-9432-b43f3892b679
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098519807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1098519807
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2718085343
Short name T931
Test name
Test status
Simulation time 165472993 ps
CPU time 1 seconds
Started Jul 23 06:50:03 PM PDT 24
Finished Jul 23 06:50:05 PM PDT 24
Peak memory 191724 kb
Host smart-b24c5af3-3597-4c92-9f37-314a5fdff932
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2718085343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2718085343
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.9911778
Short name T920
Test name
Test status
Simulation time 508940079 ps
CPU time 1.18 seconds
Started Jul 23 06:50:03 PM PDT 24
Finished Jul 23 06:50:05 PM PDT 24
Peak memory 191828 kb
Host smart-0c06da37-b9fb-4012-b7b4-d709418e495f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9911778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.9911778
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1816930980
Short name T876
Test name
Test status
Simulation time 202496588 ps
CPU time 1.11 seconds
Started Jul 23 06:50:02 PM PDT 24
Finished Jul 23 06:50:03 PM PDT 24
Peak memory 191788 kb
Host smart-7f1e1734-4c79-41ac-afb9-cc6306e8a7ce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1816930980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1816930980
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.861042238
Short name T901
Test name
Test status
Simulation time 146596328 ps
CPU time 1.4 seconds
Started Jul 23 06:50:01 PM PDT 24
Finished Jul 23 06:50:03 PM PDT 24
Peak memory 191768 kb
Host smart-9616c01e-1551-4556-8618-0b1f4e91fdae
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861042238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.861042238
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1412534974
Short name T879
Test name
Test status
Simulation time 254303891 ps
CPU time 1.17 seconds
Started Jul 23 06:50:05 PM PDT 24
Finished Jul 23 06:50:07 PM PDT 24
Peak memory 191812 kb
Host smart-df3e9f30-5bf5-403d-ad9f-3db80457afe4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1412534974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1412534974
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3065555650
Short name T905
Test name
Test status
Simulation time 52368056 ps
CPU time 1.07 seconds
Started Jul 23 06:50:15 PM PDT 24
Finished Jul 23 06:50:17 PM PDT 24
Peak memory 191784 kb
Host smart-e1d7c5d4-1cf6-42c6-a2c6-cd8eb1e21ad9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065555650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3065555650
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2583275788
Short name T899
Test name
Test status
Simulation time 49860447 ps
CPU time 1.02 seconds
Started Jul 23 06:49:47 PM PDT 24
Finished Jul 23 06:49:49 PM PDT 24
Peak memory 191772 kb
Host smart-abbd1dba-e859-495d-9204-7228e1c9f2b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2583275788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2583275788
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2128183665
Short name T908
Test name
Test status
Simulation time 42909837 ps
CPU time 0.81 seconds
Started Jul 23 06:49:41 PM PDT 24
Finished Jul 23 06:49:42 PM PDT 24
Peak memory 191588 kb
Host smart-b176ab65-2c86-4e64-ba7e-7579b6a72367
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128183665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2128183665
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.679781817
Short name T914
Test name
Test status
Simulation time 191424260 ps
CPU time 1.28 seconds
Started Jul 23 06:50:08 PM PDT 24
Finished Jul 23 06:50:10 PM PDT 24
Peak memory 191812 kb
Host smart-276007a6-3ce8-48f4-8c43-9f99f0942086
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=679781817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.679781817
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.411759534
Short name T888
Test name
Test status
Simulation time 83895044 ps
CPU time 1.46 seconds
Started Jul 23 06:50:12 PM PDT 24
Finished Jul 23 06:50:14 PM PDT 24
Peak memory 198188 kb
Host smart-d27a7418-e1ec-4909-8529-b3b3df14666e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411759534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.411759534
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1494571484
Short name T916
Test name
Test status
Simulation time 33798712 ps
CPU time 0.76 seconds
Started Jul 23 06:50:11 PM PDT 24
Finished Jul 23 06:50:12 PM PDT 24
Peak memory 191612 kb
Host smart-72bf8de0-8869-40d1-a0ad-a4ab6c33987b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1494571484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1494571484
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2724582200
Short name T849
Test name
Test status
Simulation time 49262914 ps
CPU time 1.21 seconds
Started Jul 23 06:50:08 PM PDT 24
Finished Jul 23 06:50:10 PM PDT 24
Peak memory 191824 kb
Host smart-fcfc7aac-1922-48b6-8de3-d89acf0d7bd6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724582200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2724582200
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4003036537
Short name T898
Test name
Test status
Simulation time 30008869 ps
CPU time 0.96 seconds
Started Jul 23 06:50:09 PM PDT 24
Finished Jul 23 06:50:11 PM PDT 24
Peak memory 197468 kb
Host smart-197d6dbf-430c-44f0-be01-82dcbef13dd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4003036537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4003036537
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1438711543
Short name T878
Test name
Test status
Simulation time 65422794 ps
CPU time 1.31 seconds
Started Jul 23 06:50:09 PM PDT 24
Finished Jul 23 06:50:12 PM PDT 24
Peak memory 191700 kb
Host smart-4846043f-32cb-40ca-8d8e-8524ea8f9559
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438711543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1438711543
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3562086536
Short name T862
Test name
Test status
Simulation time 29280453 ps
CPU time 0.74 seconds
Started Jul 23 06:50:08 PM PDT 24
Finished Jul 23 06:50:09 PM PDT 24
Peak memory 196128 kb
Host smart-425e9c29-0d2e-4171-b241-5cc1809c1570
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3562086536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3562086536
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3430314906
Short name T845
Test name
Test status
Simulation time 36259944 ps
CPU time 0.86 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:15 PM PDT 24
Peak memory 191600 kb
Host smart-545cf707-e323-4760-ad7e-faea0b45a035
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430314906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3430314906
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4207563169
Short name T881
Test name
Test status
Simulation time 491788686 ps
CPU time 1.35 seconds
Started Jul 23 06:50:12 PM PDT 24
Finished Jul 23 06:50:15 PM PDT 24
Peak memory 191804 kb
Host smart-ac03b714-3919-4e03-adb0-e88cbe89015e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4207563169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4207563169
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.554262222
Short name T922
Test name
Test status
Simulation time 374479669 ps
CPU time 1.5 seconds
Started Jul 23 06:50:17 PM PDT 24
Finished Jul 23 06:50:19 PM PDT 24
Peak memory 198172 kb
Host smart-d9dfb8d2-a668-4f1a-859a-499955f175b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554262222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.554262222
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1750548350
Short name T853
Test name
Test status
Simulation time 161441342 ps
CPU time 1.34 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:16 PM PDT 24
Peak memory 191792 kb
Host smart-e3e6a193-26c0-4746-86cd-b5f29b163c4e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1750548350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1750548350
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2645239165
Short name T911
Test name
Test status
Simulation time 162532125 ps
CPU time 0.98 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:15 PM PDT 24
Peak memory 191860 kb
Host smart-b829cd34-c2de-43b3-943f-059515b960f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645239165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2645239165
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1854741636
Short name T940
Test name
Test status
Simulation time 27458231 ps
CPU time 0.82 seconds
Started Jul 23 06:50:24 PM PDT 24
Finished Jul 23 06:50:28 PM PDT 24
Peak memory 196272 kb
Host smart-bc88d823-d653-40de-a0a2-30ce88e0d7cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1854741636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1854741636
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1967820389
Short name T848
Test name
Test status
Simulation time 354833208 ps
CPU time 1.05 seconds
Started Jul 23 06:50:16 PM PDT 24
Finished Jul 23 06:50:18 PM PDT 24
Peak memory 197420 kb
Host smart-c850465d-9445-406e-b20a-816d2e6d5038
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967820389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1967820389
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1633411687
Short name T882
Test name
Test status
Simulation time 108452743 ps
CPU time 0.96 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:15 PM PDT 24
Peak memory 197656 kb
Host smart-7d7260b9-a5c6-4d55-8514-93dd8af04d8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1633411687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1633411687
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3453608534
Short name T860
Test name
Test status
Simulation time 112731097 ps
CPU time 1.07 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:16 PM PDT 24
Peak memory 191560 kb
Host smart-b60b1a02-4052-47c4-b1d0-a66bd7a5482d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453608534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3453608534
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.387714592
Short name T902
Test name
Test status
Simulation time 187980638 ps
CPU time 1.31 seconds
Started Jul 23 06:50:11 PM PDT 24
Finished Jul 23 06:50:13 PM PDT 24
Peak memory 191836 kb
Host smart-8f2718f4-d2b4-4f31-b6f6-75e850a120a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=387714592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.387714592
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.153386174
Short name T851
Test name
Test status
Simulation time 29260729 ps
CPU time 0.99 seconds
Started Jul 23 06:50:12 PM PDT 24
Finished Jul 23 06:50:13 PM PDT 24
Peak memory 197324 kb
Host smart-7a920f4e-b2db-4b67-b920-e8423c16cac9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153386174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.153386174
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3476690272
Short name T850
Test name
Test status
Simulation time 167298694 ps
CPU time 1.06 seconds
Started Jul 23 06:50:13 PM PDT 24
Finished Jul 23 06:50:16 PM PDT 24
Peak memory 191840 kb
Host smart-4c2d86d3-d500-4a2c-a662-1ed19da46e51
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3476690272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3476690272
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1348036771
Short name T918
Test name
Test status
Simulation time 79167717 ps
CPU time 1.31 seconds
Started Jul 23 06:50:15 PM PDT 24
Finished Jul 23 06:50:17 PM PDT 24
Peak memory 191712 kb
Host smart-1c127114-b325-477d-beb3-d7a9e80ac404
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348036771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1348036771
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3183461014
Short name T880
Test name
Test status
Simulation time 41472463 ps
CPU time 1.11 seconds
Started Jul 23 06:49:43 PM PDT 24
Finished Jul 23 06:49:46 PM PDT 24
Peak memory 198184 kb
Host smart-92214ff6-6645-40c6-a74a-a8a421d3edef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3183461014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3183461014
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3975459668
Short name T844
Test name
Test status
Simulation time 182515253 ps
CPU time 0.9 seconds
Started Jul 23 06:49:44 PM PDT 24
Finished Jul 23 06:49:46 PM PDT 24
Peak memory 191588 kb
Host smart-b02679b4-342b-4dbf-91cc-676f1e1f26af
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975459668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3975459668
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.434989012
Short name T867
Test name
Test status
Simulation time 352600643 ps
CPU time 1.42 seconds
Started Jul 23 06:49:44 PM PDT 24
Finished Jul 23 06:49:47 PM PDT 24
Peak memory 198156 kb
Host smart-6fd8e524-1c48-477e-b89a-aa4c66e39701
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=434989012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.434989012
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.540987203
Short name T856
Test name
Test status
Simulation time 257543755 ps
CPU time 0.98 seconds
Started Jul 23 06:49:44 PM PDT 24
Finished Jul 23 06:49:46 PM PDT 24
Peak memory 191700 kb
Host smart-a4816253-8e74-44fa-8b56-60c57fd0f01d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540987203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.540987203
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1239386335
Short name T926
Test name
Test status
Simulation time 240396222 ps
CPU time 1.1 seconds
Started Jul 23 06:49:43 PM PDT 24
Finished Jul 23 06:49:45 PM PDT 24
Peak memory 191780 kb
Host smart-72bd5caf-20ae-469c-9ba6-c62f9c2f9550
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1239386335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1239386335
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2710853464
Short name T887
Test name
Test status
Simulation time 40069513 ps
CPU time 1.03 seconds
Started Jul 23 06:49:48 PM PDT 24
Finished Jul 23 06:49:50 PM PDT 24
Peak memory 191776 kb
Host smart-26090b7d-33a4-42f1-8c31-d37a84ca3b46
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710853464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2710853464
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.426992967
Short name T873
Test name
Test status
Simulation time 130211557 ps
CPU time 1.28 seconds
Started Jul 23 06:49:34 PM PDT 24
Finished Jul 23 06:49:35 PM PDT 24
Peak memory 191956 kb
Host smart-80a7f4d9-ea0d-4b1a-bb91-9b7a8143d20b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=426992967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.426992967
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4078616498
Short name T868
Test name
Test status
Simulation time 176373561 ps
CPU time 1.19 seconds
Started Jul 23 06:49:43 PM PDT 24
Finished Jul 23 06:49:45 PM PDT 24
Peak memory 196784 kb
Host smart-709b0fde-db9a-4324-a35c-e6d2cd7a22ce
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078616498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4078616498
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.859691532
Short name T894
Test name
Test status
Simulation time 67642525 ps
CPU time 1.19 seconds
Started Jul 23 06:49:41 PM PDT 24
Finished Jul 23 06:49:44 PM PDT 24
Peak memory 191716 kb
Host smart-9df40bfd-ad10-4e59-9a20-471c7a4a9740
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=859691532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.859691532
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1553521720
Short name T923
Test name
Test status
Simulation time 244807907 ps
CPU time 1.07 seconds
Started Jul 23 06:49:50 PM PDT 24
Finished Jul 23 06:49:53 PM PDT 24
Peak memory 191772 kb
Host smart-aa0487f7-92b0-4adb-887c-fe50668f6913
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553521720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1553521720
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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